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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
8
9maintainers:
10 - Jonathan Marek <jonathan@marek.ca>
11
12description: |
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains on SM8150 and SM8250.
15
16 See also:
17 dt-bindings/clock/qcom,dispcc-sm8150.h
18 dt-bindings/clock/qcom,dispcc-sm8250.h
19
20properties:
21 compatible:
22 enum:
23 - qcom,sc8180x-dispcc
24 - qcom,sm8150-dispcc
25 - qcom,sm8250-dispcc
26
27 clocks:
28 items:
29 - description: Board XO source
30 - description: Byte clock from DSI PHY0
31 - description: Pixel clock from DSI PHY0
32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1
34 - description: Link clock from DP PHY
35 - description: VCO DIV clock from DP PHY
36
37 clock-names:
38 items:
39 - const: bi_tcxo
40 - const: dsi0_phy_pll_out_byteclk
41 - const: dsi0_phy_pll_out_dsiclk
42 - const: dsi1_phy_pll_out_byteclk
43 - const: dsi1_phy_pll_out_dsiclk
44 - const: dp_phy_pll_link_clk
45 - const: dp_phy_pll_vco_div_clk
46
47 '#clock-cells':
48 const: 1
49
50 '#reset-cells':
51 const: 1
52
53 '#power-domain-cells':
54 const: 1
55
56 reg:
57 maxItems: 1
58
59required:
60 - compatible
61 - reg
62 - clocks
63 - clock-names
64 - '#clock-cells'
65 - '#reset-cells'
66 - '#power-domain-cells'
67
68additionalProperties: false
69
70examples:
71 - |
72 #include <dt-bindings/clock/qcom,rpmh.h>
73 clock-controller@af00000 {
74 compatible = "qcom,sm8250-dispcc";
75 reg = <0x0af00000 0x10000>;
76 clocks = <&rpmhcc RPMH_CXO_CLK>,
77 <&dsi0_phy 0>,
78 <&dsi0_phy 1>,
79 <&dsi1_phy 0>,
80 <&dsi1_phy 1>,
81 <&dp_phy 0>,
82 <&dp_phy 1>;
83 clock-names = "bi_tcxo",
84 "dsi0_phy_pll_out_byteclk",
85 "dsi0_phy_pll_out_dsiclk",
86 "dsi1_phy_pll_out_byteclk",
87 "dsi1_phy_pll_out_dsiclk",
88 "dp_phy_pll_link_clk",
89 "dp_phy_pll_vco_div_clk";
90 #clock-cells = <1>;
91 #reset-cells = <1>;
92 #power-domain-cells = <1>;
93 };
94...