tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/N1 Pin Controller
8
9maintainers:
10 - Gareth Williams <gareth.williams.jx@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
12
13properties:
14 compatible:
15 items:
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
20
21 reg:
22 items:
23 - description: GPIO Multiplexing Level1 Register Block
24 - description: GPIO Multiplexing Level2 Register Block
25
26 clocks:
27 maxItems: 1
28
29 clock-names:
30 const: bus
31 description:
32 The bus clock, sometimes described as pclk, for register accesses.
33
34required:
35 - compatible
36 - reg
37 - clocks
38 - clock-names
39
40additionalProperties:
41 anyOf:
42 - type: object
43 allOf:
44 - $ref: pincfg-node.yaml#
45 - $ref: pinmux-node.yaml#
46
47 description:
48 A pin multiplexing sub-node describes how to configure a set of (or a
49 single) pin in some desired alternate function mode.
50 A single sub-node may define several pin configurations.
51
52 properties:
53 pinmux:
54 description: |
55 Integer array representing pin number and pin multiplexing
56 configuration.
57 When a pin has to be configured in alternate function mode, use
58 this property to identify the pin by its global index, and provide
59 its alternate function configuration number along with it.
60 When multiple pins are required to be configured as part of the
61 same alternate function they shall be specified as members of the
62 same argument list of a single "pinmux" property.
63 Integers values in the "pinmux" argument list are assembled as:
64 (PIN | MUX_FUNC << 8)
65 where PIN directly corresponds to the pl_gpio pin number and
66 MUX_FUNC is one of the alternate function identifiers defined in:
67 <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
68 These identifiers collapse the IO Multiplex Configuration Level 1
69 and Level 2 numbers that are detailed in the hardware reference
70 manual into a single number. The identifiers for Level 2 are simply
71 offset by 10. Additional identifiers are provided to specify the
72 MDIO source peripheral.
73
74 phandle: true
75 bias-disable: true
76 bias-pull-up:
77 description: Pull up the pin with 50 kOhm
78 bias-pull-down:
79 description: Pull down the pin with 50 kOhm
80 bias-high-impedance: true
81 drive-strength:
82 enum: [ 4, 6, 8, 12 ]
83
84 required:
85 - pinmux
86
87 additionalProperties:
88 $ref: "#/additionalProperties/anyOf/0"
89
90 - type: object
91 properties:
92 phandle: true
93
94 additionalProperties:
95 $ref: "#/additionalProperties/anyOf/0"
96
97examples:
98 - |
99 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
100 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
101 pinctrl: pinctrl@40067000 {
102 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
103 reg = <0x40067000 0x1000>, <0x51000000 0x480>;
104 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
105 clock-names = "bus";
106
107 /*
108 * A serial communication interface with a TX output pin and an RX
109 * input pin.
110 */
111 pins_uart0: pins_uart0 {
112 pinmux = <
113 RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
114 RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
115 >;
116 };
117
118 /*
119 * Set the pull-up on the RXD pin of the UART.
120 */
121 pins_uart0_alt: pins_uart0_alt {
122 pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;
123
124 pins_uart6_rx {
125 pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
126 bias-pull-up;
127 };
128 };
129 };