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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
8
9maintainers:
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13 On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
14 Standby Mode share the same register block.
15
16 They provide the following functionalities:
17 - The CPG block generates various core clocks,
18 - The Module Standby Mode block provides two functions:
19 1. Module Standby, providing a Clock Domain to control the clock supply
20 to individual SoC devices,
21 2. Reset Control, to perform a software reset of individual SoC devices.
22
23properties:
24 compatible:
25 const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
26
27 reg:
28 maxItems: 1
29
30 clocks:
31 maxItems: 1
32
33 clock-names:
34 description:
35 Clock source to CPG can be either from external clock input (EXCLK) or
36 crystal oscillator (XIN/XOUT).
37 const: extal
38
39 '#clock-cells':
40 description: |
41 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
42 and a core clock reference, as defined in
43 <dt-bindings/clock/r9a07g044-cpg.h>
44 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
45 a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
46 const: 2
47
48 '#power-domain-cells':
49 description:
50 SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
51 can be power-managed through Module Standby should refer to the CPG device
52 node in their "power-domains" property, as documented by the generic PM
53 Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
54 const: 0
55
56 '#reset-cells':
57 description:
58 The single reset specifier cell must be the module number, as defined in
59 the <dt-bindings/clock/r9a07g044-cpg.h>.
60 const: 1
61
62required:
63 - compatible
64 - reg
65 - clocks
66 - clock-names
67 - '#clock-cells'
68 - '#power-domain-cells'
69 - '#reset-cells'
70
71additionalProperties: false
72
73examples:
74 - |
75 cpg: clock-controller@11010000 {
76 compatible = "renesas,r9a07g044-cpg";
77 reg = <0x11010000 0x10000>;
78 clocks = <&extal_clk>;
79 clock-names = "extal";
80 #clock-cells = <2>;
81 #power-domain-cells = <0>;
82 #reset-cells = <1>;
83 };