tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32/* QPHY_START_CONTROL bits */
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36/* QPHY_PCS_STATUS bit */
37#define PHYSTATUS BIT(6)
38#define PHYSTATUS_4_20 BIT(7)
39/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
40#define PCS_READY BIT(0)
41
42/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
43/* DP PHY soft reset */
44#define SW_DPPHY_RESET BIT(0)
45/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
46#define SW_DPPHY_RESET_MUX BIT(1)
47/* USB3 PHY soft reset */
48#define SW_USB3PHY_RESET BIT(2)
49/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
50#define SW_USB3PHY_RESET_MUX BIT(3)
51
52/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
53#define USB3_MODE BIT(0) /* enables USB3 mode */
54#define DP_MODE BIT(1) /* enables DP mode */
55
56/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
57#define ARCVR_DTCT_EN BIT(0)
58#define ALFPS_DTCT_EN BIT(1)
59#define ARCVR_DTCT_EVENT_SEL BIT(4)
60
61/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
62#define IRQ_CLEAR BIT(0)
63
64/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
65#define RCVR_DETECT BIT(0)
66
67/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
68#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
69
70#define PHY_INIT_COMPLETE_TIMEOUT 10000
71#define POWER_DOWN_DELAY_US_MIN 10
72#define POWER_DOWN_DELAY_US_MAX 11
73
74#define MAX_PROP_NAME 32
75
76/* Define the assumed distance between lanes for underspecified device trees. */
77#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
78
79struct qmp_phy_init_tbl {
80 unsigned int offset;
81 unsigned int val;
82 /*
83 * register part of layout ?
84 * if yes, then offset gives index in the reg-layout
85 */
86 bool in_layout;
87 /*
88 * mask of lanes for which this register is written
89 * for cases when second lane needs different values
90 */
91 u8 lane_mask;
92};
93
94#define QMP_PHY_INIT_CFG(o, v) \
95 { \
96 .offset = o, \
97 .val = v, \
98 .lane_mask = 0xff, \
99 }
100
101#define QMP_PHY_INIT_CFG_L(o, v) \
102 { \
103 .offset = o, \
104 .val = v, \
105 .in_layout = true, \
106 .lane_mask = 0xff, \
107 }
108
109#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
110 { \
111 .offset = o, \
112 .val = v, \
113 .lane_mask = l, \
114 }
115
116/* set of registers with offsets different per-PHY */
117enum qphy_reg_layout {
118 /* Common block control registers */
119 QPHY_COM_SW_RESET,
120 QPHY_COM_POWER_DOWN_CONTROL,
121 QPHY_COM_START_CONTROL,
122 QPHY_COM_PCS_READY_STATUS,
123 /* PCS registers */
124 QPHY_PLL_LOCK_CHK_DLY_TIME,
125 QPHY_FLL_CNTRL1,
126 QPHY_FLL_CNTRL2,
127 QPHY_FLL_CNT_VAL_L,
128 QPHY_FLL_CNT_VAL_H_TOL,
129 QPHY_FLL_MAN_CODE,
130 QPHY_SW_RESET,
131 QPHY_START_CTRL,
132 QPHY_PCS_READY_STATUS,
133 QPHY_PCS_STATUS,
134 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
135 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
136 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
137 QPHY_PCS_POWER_DOWN_CONTROL,
138 /* Keep last to ensure regs_layout arrays are properly initialized */
139 QPHY_LAYOUT_SIZE
140};
141
142static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
143 [QPHY_START_CTRL] = 0x00,
144 [QPHY_PCS_READY_STATUS] = 0x168,
145};
146
147static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
148 [QPHY_SW_RESET] = 0x00,
149 [QPHY_START_CTRL] = 0x44,
150 [QPHY_PCS_STATUS] = 0x14,
151 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
152};
153
154static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
155 [QPHY_COM_SW_RESET] = 0x400,
156 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
157 [QPHY_COM_START_CONTROL] = 0x408,
158 [QPHY_COM_PCS_READY_STATUS] = 0x448,
159 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
160 [QPHY_FLL_CNTRL1] = 0xc4,
161 [QPHY_FLL_CNTRL2] = 0xc8,
162 [QPHY_FLL_CNT_VAL_L] = 0xcc,
163 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
164 [QPHY_FLL_MAN_CODE] = 0xd4,
165 [QPHY_SW_RESET] = 0x00,
166 [QPHY_START_CTRL] = 0x08,
167 [QPHY_PCS_STATUS] = 0x174,
168};
169
170static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
171 [QPHY_FLL_CNTRL1] = 0xc0,
172 [QPHY_FLL_CNTRL2] = 0xc4,
173 [QPHY_FLL_CNT_VAL_L] = 0xc8,
174 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
175 [QPHY_FLL_MAN_CODE] = 0xd0,
176 [QPHY_SW_RESET] = 0x00,
177 [QPHY_START_CTRL] = 0x08,
178 [QPHY_PCS_STATUS] = 0x17c,
179 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
180 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
181 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
182};
183
184static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
185 [QPHY_SW_RESET] = 0x00,
186 [QPHY_START_CTRL] = 0x08,
187 [QPHY_PCS_STATUS] = 0x174,
188 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
189 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
190 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
191};
192
193static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
194 [QPHY_SW_RESET] = 0x00,
195 [QPHY_START_CTRL] = 0x08,
196 [QPHY_PCS_STATUS] = 0x174,
197};
198
199static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
200 [QPHY_SW_RESET] = 0x00,
201 [QPHY_START_CTRL] = 0x08,
202 [QPHY_PCS_STATUS] = 0x2ac,
203};
204
205static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
206 [QPHY_SW_RESET] = 0x00,
207 [QPHY_START_CTRL] = 0x44,
208 [QPHY_PCS_STATUS] = 0x14,
209 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
210 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
211 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
212};
213
214static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
215 [QPHY_SW_RESET] = 0x00,
216 [QPHY_START_CTRL] = 0x44,
217 [QPHY_PCS_STATUS] = 0x14,
218 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
219 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
220 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
221};
222
223static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
224 [QPHY_SW_RESET] = 0x00,
225 [QPHY_START_CTRL] = 0x44,
226 [QPHY_PCS_STATUS] = 0x14,
227 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
228 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
229 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
230};
231
232static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
233 [QPHY_START_CTRL] = 0x00,
234 [QPHY_PCS_READY_STATUS] = 0x160,
235};
236
237static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
238 [QPHY_SW_RESET] = 0x00,
239 [QPHY_START_CTRL] = 0x44,
240 [QPHY_PCS_STATUS] = 0x14,
241 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
242};
243
244static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
245 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
246 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
247 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
248};
249
250static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
251 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
252 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
253 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
254 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
255 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
256 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
257 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
258 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
259 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
260 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
261 /* PLL and Loop filter settings */
262 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
263 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
264 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
265 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
266 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
267 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
268 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
269 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
270 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
271 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
272 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
273 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
274 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
275 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
276 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
277 /* SSC settings */
278 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
279 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
280 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
281 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
282 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
283 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
284 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
285};
286
287static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
288 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
289 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
290 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
291 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
292 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
293 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
294 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
295 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
296 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
297};
298
299static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
323};
324
325static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
326 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
327 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
328 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
329 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
330 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
331 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
332 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
333 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
334 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
335 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
336 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
337 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
338 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
339 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
340 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
341 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
342 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
343 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
344 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
345 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
346 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
347 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
348 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
349 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
350 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
351 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
352 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
353 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
354 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
355 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
356 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
357 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
358 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
359 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
360 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
361 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
362 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
363 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
364 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
365 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
366 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
367 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
368 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
369};
370
371static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
372 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
373 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
374};
375
376static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
377 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
378 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
379 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
380 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
381 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
382 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
383 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
384 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
385 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
386 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
387};
388
389static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
390 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
391 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
392 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
393
394 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
395
396 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
397 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
398 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
399 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
400 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
401};
402
403static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
446};
447
448static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
449 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
450 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
451 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
452 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
453};
454
455static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
457 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
458 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
459 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
460 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
462 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
463 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
465 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
466 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
467 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
468 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
469 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
470};
471
472static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
483};
484
485static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
486 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
487 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
488 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
489 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
490 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
491 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
492 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
493 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
494 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
495 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
496 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
497 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
498 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
499 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
500 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
501 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
502 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
503 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
504 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
505 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
506 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
507 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
508 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
509 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
510 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
511 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
512 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
513 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
514 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
515 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
516 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
517 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
518 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
519 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
520 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
521 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
522 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
523 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
524 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
525 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
526 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
527 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
528 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
529 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
530 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
531 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
532 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
533};
534
535static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
536 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
537 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
538};
539
540static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
541 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
542 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
543 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
544 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
545 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
546 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
547 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
548 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
549 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
550 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
551 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
552};
553
554static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
555 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
556 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
557 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
558 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
559 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
560 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
561 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
562 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
563 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
564 /* PLL and Loop filter settings */
565 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
566 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
567 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
568 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
569 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
570 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
571 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
572 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
573 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
574 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
575 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
576 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
577 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
578 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
579 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
580 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
581 /* SSC settings */
582 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
583 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
584 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
585 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
586 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
587 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
588 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
589};
590
591static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
592 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
593 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
594 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
595};
596
597static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
598 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
599 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
600 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
601 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
602 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
603 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
604 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
605 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
606 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
607 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
608};
609
610static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
611 /* FLL settings */
612 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
613 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
614 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
615 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
616 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
617
618 /* Lock Det settings */
619 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
620 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
621 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
622 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
623};
624
625static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
626 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
627 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
628 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
629 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
630 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
631 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
632 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
633 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
634 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
635 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
636 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
637 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
638 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
639 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
640 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
641 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
642 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
643 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
644 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
645 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
646 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
647 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
648 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
649 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
650 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
651 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
652 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
653 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
654 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
655 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
656 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
657 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
658 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
659 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
660 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
661 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
662 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
663 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
664 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
665 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
666 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
667 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
668 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
669 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
670 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
671 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
672};
673
674static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
675 QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
676 QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
677 QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
678};
679
680static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
681 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
682 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
683 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
684 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
685 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
686 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
687 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
688 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
689 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
690 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
691 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
692 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
693 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
694 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
695 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
696 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
697 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
698 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
699 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
700 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
701 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
702 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
703 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
704 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
705 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
706 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
707 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
708 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
709 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
710 QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
711};
712
713static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
714 QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
715 QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
716 QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
717 QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
718 QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
719 QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
720 QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
721 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
722 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
723 QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
724 QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
725 QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
726 QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
727 QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
728 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
729 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
730};
731
732static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
733 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
734 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
735 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
736 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
737 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
738 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
739 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
740 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
741 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
742 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
743 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
744 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
745 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
746 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
747 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
748 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
749 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
750 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
751 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
752 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
753 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
754 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
755 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
756 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
757 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
758 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
759 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
760 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
761 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
762 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
763 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
764 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
765 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
766 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
767 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
768 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
769 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
770 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
771 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
772 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
773};
774
775static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
776 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
777 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
778 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
779 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
780 QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
781 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
782};
783
784static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
785 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
786 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
787 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
788 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
789 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
790 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
791 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
792};
793
794static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
795 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
796 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
797 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
798 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
799 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
800 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
801 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
802 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
803 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
804 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
805 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
806 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
807 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
808};
809
810static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
811 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
812 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
813 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
814 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
815 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
816 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
817 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
818 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
819 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
820 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
821 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
822 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
823 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
824 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
825 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
826 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
827 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
828 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
829 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
830 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
831 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
832 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
833 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
834 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
835 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
836 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
837 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
838 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
839 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
840 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
841 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
842 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
843 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
844 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
845 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
846 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
847 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
848 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
849 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
850 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
851 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
852 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
853};
854
855static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
856 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
857 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
858 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
859 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
860};
861
862static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
863 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
864 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
865 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
866 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
867 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
868 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
869 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
870 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
871 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
872 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
873 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
874 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
875 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
876 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
877 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
878 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
879};
880
881static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
882 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
883
884 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
885 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
886 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
887 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
888 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
889
890 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
891 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
892 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
893 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
894 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
895 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
896 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
897
898 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
899 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
900 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
901
902 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
903};
904
905static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
906 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
907 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
908 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
909 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
910 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
911};
912
913static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
914 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
915 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
916 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
917 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
918 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
919 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
920 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
921 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
922 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
923 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
924 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
925 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
926 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
927 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
928 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
929 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
930 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
931 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
932 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
933 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
934 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
935 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
936 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
937 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
938 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
939 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
940 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
941 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
942 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
943 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
944 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
945 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
946 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
947 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
948 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
949 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
950 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
951 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
952 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
953 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
954 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
955 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
956 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
957 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
958 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
959};
960
961static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
962 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
963 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
964 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
965 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
966 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
967 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
968 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
969 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
970 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
971 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
972 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
973 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
974 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
975 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
976 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
977 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
978 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
979 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
980 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
981 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
982 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
983 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
984 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
985 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
986 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
987 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
988 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
989 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
990 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
991 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
992 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
993 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
994 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
995 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
996 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
997 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
998 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
999 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1000 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1001 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1002 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1003 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1004 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1005 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1006 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1007 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1008 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1009 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1010 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1011 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1012 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1013 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1014 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1015 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1016 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1017 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1018};
1019
1020static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
1021};
1022
1023static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1024 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1025 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1026 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1027 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1028 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1029 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1030 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1031};
1032
1033static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
1034 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1035 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1036 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1037 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1038 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1039 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1040 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
1041 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1042 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1043 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1044 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1045 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1046 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1047 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1048 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1049 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1050 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1051 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1052 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1053 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1054 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1055 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1056 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1057 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1058 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1059 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1060 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1061 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1062 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1063 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1064 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1065 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1066 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1067 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1068 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1069 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1070};
1071
1072static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
1073 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1074 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1075 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1076 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1077 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1078};
1079
1080static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
1081 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1082 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
1083 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1084 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
1085 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
1086 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1087 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
1088 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
1089 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1090 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1091 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1092 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1093 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1094 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1095 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1096 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
1097 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
1098 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1099 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1102};
1103
1104static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
1105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
1106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
1110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
1111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1112};
1113
1114static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
1115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
1116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
1120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
1121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1122};
1123
1124static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
1125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1132};
1133
1134static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1142};
1143
1144static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1145 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1146 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1147 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1148 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1149 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1150 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1151 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1152 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1153 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1154 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1155 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1156 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1157 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1158 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1159 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1160};
1161
1162static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1163 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1164 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1165 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1166 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1172};
1173
1174static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1175 /* FLL settings */
1176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1181
1182 /* Lock Det settings */
1183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1187
1188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1207
1208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1219};
1220
1221static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1258};
1259
1260static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1264 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1265 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1266};
1267
1268static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1269 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1270 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1271 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1272 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1273 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1278 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1279 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1280};
1281
1282static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1283 /* FLL settings */
1284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1289
1290 /* Lock Det settings */
1291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1295
1296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1315
1316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1327
1328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1330};
1331
1332static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1333 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1334 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1335 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1336 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1337 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1338 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1339 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1340 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1341 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1342 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1343 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1344 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1345 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1346 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1347 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1348 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1349 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1350 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1351 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1352 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1353 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1354 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1355 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1356 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1357 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1358 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1359 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1360 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1361 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1362 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1363 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1364 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1365 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1366 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1367 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1368 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1369
1370 /* Rate B */
1371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1372};
1373
1374static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1375 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1376 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1377 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1378};
1379
1380static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1381 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1382 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1383 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1384 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1385 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1386 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1387 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1388 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1389 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1390 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1391 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1392 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1393 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1394 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1395 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1396 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1397};
1398
1399static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1408};
1409
1410static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1449};
1450
1451static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1452 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1453 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1454 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1455 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1456};
1457
1458static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1459 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1460 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1462 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1463 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1465 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1466 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1467 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1468 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1469 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1470 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1471 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1472 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1473 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1474 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1475 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1476};
1477
1478static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1500 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1507 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1512 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1516 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1517};
1518
1519static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1520 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1544
1545 /* Rate B */
1546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1547};
1548
1549static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1550 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1551 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1552 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1553 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1554 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1555 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1556};
1557
1558static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1561 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1562 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1563 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1564 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1565 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1566 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1567 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1593
1594};
1595
1596static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1597 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1598 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1599 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1600 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1601 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1602 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1603 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1604};
1605
1606static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1607 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1608 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1647};
1648
1649static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1650 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1651 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1652 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1653 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1654 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1655};
1656
1657static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1694};
1695
1696static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1697 /* Lock Det settings */
1698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1701
1702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1705 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1707 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1709 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1712};
1713
1714static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1717 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1718 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1719 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1720 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1721 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1722 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1723 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1724 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1725 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1755};
1756
1757static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1758 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1759 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1760 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1761 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1762};
1763
1764static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1765 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1801};
1802
1803static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1804 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1805 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1806 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1807 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1808 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1809 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1810 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1811 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1812 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1813 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1814 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1815 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1816 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1817 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1818 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1819 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1820};
1821
1822static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1823 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1824 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1825 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1826 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1827 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1828 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1829 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1830 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1831};
1832
1833static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1834 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1835 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1836 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1837 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1838 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1839 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1840 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1841 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1842 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1843 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1844 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1845 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1846 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1847 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1852 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1853 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1854 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1855 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1856 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1857 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1872};
1873
1874static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1875 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1876 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1877 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1878 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1879 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1880 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1881 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1882 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1883 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1884 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1885 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1886 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1887 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1888 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1889};
1890
1891static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
1892 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1893 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1894 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
1895 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1896 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1897 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1898};
1899
1900static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
1901 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1902 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
1903 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1905 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1906 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1909 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
1921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1937};
1938
1939static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
1940 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1941 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1942 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1943 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1944 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1945 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1946 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1947 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1948 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1949 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1950 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1951 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1952 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1953 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1954 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1956};
1957
1958static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
1959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
1960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
1961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
1962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
1963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
1964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
1965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
1970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
1973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
1974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
1975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
1976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
1977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
1978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
1979};
1980
1981static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
1982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
1983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
1984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
1985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
1986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
1987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
1988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1989};
1990
1991static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
1992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
1993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
1994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
1995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
1996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
1997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
1998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
1999};
2000
2001static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
2002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
2004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
2005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
2006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
2007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
2008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2009};
2010
2011static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
2012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
2013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
2017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
2018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2019};
2020
2021static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
2022 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
2023 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
2024 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
2025 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
2026 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
2027 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
2028 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
2029 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
2030 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2031 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
2032 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
2033 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
2034 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
2035 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
2036};
2037
2038static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
2039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2040 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2041 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2042 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2043 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2044 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2045 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2046 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2047 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2048 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2049 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2050 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2051 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2052 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2053 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2054 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2055 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2056 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2057 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2058 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2059 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2060 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2061 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2062 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2063 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2064 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2065 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2066 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2067 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2068 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2069 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2070 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2071 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2072 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2073 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2074 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2075 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2076 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2077 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2078 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2079 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2080};
2081
2082static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
2083 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2084};
2085
2086static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
2087 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2088 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
2089 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2090};
2091
2092static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
2093 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2094 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2095 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
2096 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2097 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2098 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
2099 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
2100 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
2101 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2102 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2103 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
2104 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2105 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
2106 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2107 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2108 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2109 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2110 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2111 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2112 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2113 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
2114 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2115 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2116 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2117 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2118 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2119 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2120 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2121 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
2122 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2123};
2124
2125static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
2126 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
2127 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
2128 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2129 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
2130 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
2131 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2132};
2133
2134static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
2135 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2136 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
2137 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2138};
2139
2140static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
2141 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2142 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
2143};
2144
2145static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
2146 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2147 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2148 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2149 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
2150 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2151 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2152 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2153};
2154
2155static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2156 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2157 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
2158};
2159
2160static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
2161 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2162};
2163
2164static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
2165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
2167 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
2168 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2169};
2170
2171static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
2172 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
2173 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
2174};
2175
2176static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2177 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
2178 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2179};
2180
2181static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
2182 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2183 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2184 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
2185 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2186 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
2187};
2188
2189static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
2190 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
2191 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2192 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2193 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2194 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2195 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2196 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2197 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2198 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2199 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2200 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2201 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
2202 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2203 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
2204 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
2205 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2206 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2207 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2208 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2209 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
2210 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2211 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2212 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2213 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2214 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2215 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2216 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2217 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2218 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2219 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2220 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2221 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2222 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2223 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
2224 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2225 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2226};
2227
2228static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
2229 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
2230 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
2231 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
2232 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2233 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
2234 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
2235 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
2236 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
2237 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
2238 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
2239 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
2240 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
2241 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
2242 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
2243 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
2244 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
2245 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
2246 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
2247 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
2248 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
2249 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2250 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2251 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2252 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2253 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2254 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
2255 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2256 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
2257 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
2258 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
2259 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
2260 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
2261 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
2262 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
2263 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
2264 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
2265 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
2266 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
2267 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
2268};
2269
2270static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
2271 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
2272 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
2273 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
2274 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
2275 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
2276};
2277
2278static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
2279 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
2280 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
2281 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
2282 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
2283 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
2284 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
2285 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
2286 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
2287 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
2288 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
2289 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
2290 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
2291 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
2292 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
2293 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
2294 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
2295 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
2296 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
2297 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
2298 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
2299 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
2300 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
2301 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
2302 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2303 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
2304};
2305
2306static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
2307 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
2308 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
2309 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
2310 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
2311};
2312
2313static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
2314 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
2315 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
2316 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
2317 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
2318 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2319 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2320 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2321};
2322
2323static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
2324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
2325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
2326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
2331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
2334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
2335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
2336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
2338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
2339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
2341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
2342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
2343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
2344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
2345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
2346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
2347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
2348
2349 /* Rate B */
2350 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
2351};
2352
2353static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
2354 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
2355 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
2356 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
2357 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
2358 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
2359 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2360 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
2361 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
2362 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
2363};
2364
2365static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
2366 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
2367 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
2368 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2369 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
2370 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
2371 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
2372 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
2373 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
2374 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
2375 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
2376 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
2377 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
2378 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2379 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
2380 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
2381 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
2382 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2383 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
2384 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
2385 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2386 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2387 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
2388 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
2389 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
2390 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
2391 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
2392 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
2393 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
2394 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
2395 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
2396 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
2397 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
2398 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
2399 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
2400 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
2401 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
2402 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2403};
2404
2405static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
2406 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
2407 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
2408 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
2409 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
2410 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
2411 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
2412 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
2413 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
2414 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
2415 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
2416 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
2417 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
2418 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
2419 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
2420 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
2421};
2422
2423static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
2424 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
2425 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
2426 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2427 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2428 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
2429 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2430 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
2431 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
2432 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
2433 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2434};
2435
2436static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
2437 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2438 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2439 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2440 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2441 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2442 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2443 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2444 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2445 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2446 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2447 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2448 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2449 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2450 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2451 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2452 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2453 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2454 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2455 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2456 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2457 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2458 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
2459 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
2460 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
2461 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
2462 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
2463 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2464 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2465 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2466 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
2467 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
2468 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2469 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
2470 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2471 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2472 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2473 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2474 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
2475};
2476
2477static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
2478 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
2479 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
2480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2494 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2495 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
2496};
2497
2498static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
2499 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2500 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2501 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2502 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2503 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2504 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
2505 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2506};
2507
2508static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
2509 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
2510 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2511 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2512 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2513 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2514 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2515 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2516 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2517 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2518 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2519 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2520 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2521 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2522 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2523 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2524 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2525 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2526 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2527 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2528 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2529 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2530 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2531 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2532 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2533 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2534 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2535 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2536 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2537 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2538 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2539 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2540};
2541
2542static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
2543 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2544 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2545 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2546 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2547 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2548 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2549 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2550 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2551 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2552 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2553 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2554 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2555 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2556 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2557 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2558 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2559};
2560
2561struct qmp_phy;
2562
2563/* struct qmp_phy_cfg - per-PHY initialization config */
2564struct qmp_phy_cfg {
2565 /* phy-type - PCIE/UFS/USB */
2566 unsigned int type;
2567 /* number of lanes provided by phy */
2568 int nlanes;
2569
2570 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
2571 const struct qmp_phy_init_tbl *serdes_tbl;
2572 int serdes_tbl_num;
2573 const struct qmp_phy_init_tbl *serdes_tbl_sec;
2574 int serdes_tbl_num_sec;
2575 const struct qmp_phy_init_tbl *tx_tbl;
2576 int tx_tbl_num;
2577 const struct qmp_phy_init_tbl *tx_tbl_sec;
2578 int tx_tbl_num_sec;
2579 const struct qmp_phy_init_tbl *rx_tbl;
2580 int rx_tbl_num;
2581 const struct qmp_phy_init_tbl *rx_tbl_sec;
2582 int rx_tbl_num_sec;
2583 const struct qmp_phy_init_tbl *pcs_tbl;
2584 int pcs_tbl_num;
2585 const struct qmp_phy_init_tbl *pcs_tbl_sec;
2586 int pcs_tbl_num_sec;
2587 const struct qmp_phy_init_tbl *pcs_misc_tbl;
2588 int pcs_misc_tbl_num;
2589 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
2590 int pcs_misc_tbl_num_sec;
2591
2592 /* Init sequence for DP PHY block link rates */
2593 const struct qmp_phy_init_tbl *serdes_tbl_rbr;
2594 int serdes_tbl_rbr_num;
2595 const struct qmp_phy_init_tbl *serdes_tbl_hbr;
2596 int serdes_tbl_hbr_num;
2597 const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
2598 int serdes_tbl_hbr2_num;
2599 const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
2600 int serdes_tbl_hbr3_num;
2601
2602 /* DP PHY callbacks */
2603 int (*configure_dp_phy)(struct qmp_phy *qphy);
2604 void (*configure_dp_tx)(struct qmp_phy *qphy);
2605 int (*calibrate_dp_phy)(struct qmp_phy *qphy);
2606 void (*dp_aux_init)(struct qmp_phy *qphy);
2607
2608 /* clock ids to be requested */
2609 const char * const *clk_list;
2610 int num_clks;
2611 /* resets to be requested */
2612 const char * const *reset_list;
2613 int num_resets;
2614 /* regulators to be requested */
2615 const char * const *vreg_list;
2616 int num_vregs;
2617
2618 /* array of registers with different offsets */
2619 const unsigned int *regs;
2620
2621 unsigned int start_ctrl;
2622 unsigned int pwrdn_ctrl;
2623 unsigned int mask_com_pcs_ready;
2624 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
2625 unsigned int phy_status;
2626
2627 /* true, if PHY has a separate PHY_COM control block */
2628 bool has_phy_com_ctrl;
2629 /* true, if PHY has a reset for individual lanes */
2630 bool has_lane_rst;
2631 /* true, if PHY needs delay after POWER_DOWN */
2632 bool has_pwrdn_delay;
2633 /* power_down delay in usec */
2634 int pwrdn_delay_min;
2635 int pwrdn_delay_max;
2636
2637 /* true, if PHY has a separate DP_COM control block */
2638 bool has_phy_dp_com_ctrl;
2639 /* true, if PHY has secondary tx/rx lanes to be configured */
2640 bool is_dual_lane_phy;
2641
2642 /* true, if PCS block has no separate SW_RESET register */
2643 bool no_pcs_sw_reset;
2644};
2645
2646struct qmp_phy_combo_cfg {
2647 const struct qmp_phy_cfg *usb_cfg;
2648 const struct qmp_phy_cfg *dp_cfg;
2649};
2650
2651/**
2652 * struct qmp_phy - per-lane phy descriptor
2653 *
2654 * @phy: generic phy
2655 * @cfg: phy specific configuration
2656 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
2657 * @tx: iomapped memory space for lane's tx
2658 * @rx: iomapped memory space for lane's rx
2659 * @pcs: iomapped memory space for lane's pcs
2660 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
2661 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
2662 * @pcs_misc: iomapped memory space for lane's pcs_misc
2663 * @pipe_clk: pipe lock
2664 * @index: lane index
2665 * @qmp: QMP phy to which this lane belongs
2666 * @lane_rst: lane's reset controller
2667 * @mode: current PHY mode
2668 */
2669struct qmp_phy {
2670 struct phy *phy;
2671 const struct qmp_phy_cfg *cfg;
2672 void __iomem *serdes;
2673 void __iomem *tx;
2674 void __iomem *rx;
2675 void __iomem *pcs;
2676 void __iomem *tx2;
2677 void __iomem *rx2;
2678 void __iomem *pcs_misc;
2679 struct clk *pipe_clk;
2680 unsigned int index;
2681 struct qcom_qmp *qmp;
2682 struct reset_control *lane_rst;
2683 enum phy_mode mode;
2684 unsigned int dp_aux_cfg;
2685 struct phy_configure_opts_dp dp_opts;
2686 struct qmp_phy_dp_clks *dp_clks;
2687};
2688
2689struct qmp_phy_dp_clks {
2690 struct qmp_phy *qphy;
2691 struct clk_hw dp_link_hw;
2692 struct clk_hw dp_pixel_hw;
2693};
2694
2695/**
2696 * struct qcom_qmp - structure holding QMP phy block attributes
2697 *
2698 * @dev: device
2699 * @dp_com: iomapped memory space for phy's dp_com control block
2700 *
2701 * @clks: array of clocks required by phy
2702 * @resets: array of resets required by phy
2703 * @vregs: regulator supplies bulk data
2704 *
2705 * @phys: array of per-lane phy descriptors
2706 * @phy_mutex: mutex lock for PHY common block initialization
2707 * @init_count: phy common block initialization count
2708 * @ufs_reset: optional UFS PHY reset handle
2709 */
2710struct qcom_qmp {
2711 struct device *dev;
2712 void __iomem *dp_com;
2713
2714 struct clk_bulk_data *clks;
2715 struct reset_control **resets;
2716 struct regulator_bulk_data *vregs;
2717
2718 struct qmp_phy **phys;
2719
2720 struct mutex phy_mutex;
2721 int init_count;
2722
2723 struct reset_control *ufs_reset;
2724};
2725
2726static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
2727static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
2728static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
2729static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
2730
2731static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
2732static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
2733static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
2734static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
2735
2736static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
2737{
2738 u32 reg;
2739
2740 reg = readl(base + offset);
2741 reg |= val;
2742 writel(reg, base + offset);
2743
2744 /* ensure that above write is through */
2745 readl(base + offset);
2746}
2747
2748static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
2749{
2750 u32 reg;
2751
2752 reg = readl(base + offset);
2753 reg &= ~val;
2754 writel(reg, base + offset);
2755
2756 /* ensure that above write is through */
2757 readl(base + offset);
2758}
2759
2760/* list of clocks required by phy */
2761static const char * const msm8996_phy_clk_l[] = {
2762 "aux", "cfg_ahb", "ref",
2763};
2764
2765static const char * const msm8996_ufs_phy_clk_l[] = {
2766 "ref",
2767};
2768
2769static const char * const qmp_v3_phy_clk_l[] = {
2770 "aux", "cfg_ahb", "ref", "com_aux",
2771};
2772
2773static const char * const sdm845_pciephy_clk_l[] = {
2774 "aux", "cfg_ahb", "ref", "refgen",
2775};
2776
2777static const char * const qmp_v4_phy_clk_l[] = {
2778 "aux", "ref_clk_src", "ref", "com_aux",
2779};
2780
2781/* the primary usb3 phy on sm8250 doesn't have a ref clock */
2782static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
2783 "aux", "ref_clk_src", "com_aux"
2784};
2785
2786static const char * const sdm845_ufs_phy_clk_l[] = {
2787 "ref", "ref_aux",
2788};
2789
2790/* usb3 phy on sdx55 doesn't have com_aux clock */
2791static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
2792 "aux", "cfg_ahb", "ref"
2793};
2794
2795/* list of resets */
2796static const char * const msm8996_pciephy_reset_l[] = {
2797 "phy", "common", "cfg",
2798};
2799
2800static const char * const msm8996_usb3phy_reset_l[] = {
2801 "phy", "common",
2802};
2803
2804static const char * const sc7180_usb3phy_reset_l[] = {
2805 "phy",
2806};
2807
2808static const char * const sdm845_pciephy_reset_l[] = {
2809 "phy",
2810};
2811
2812/* list of regulators */
2813static const char * const qmp_phy_vreg_l[] = {
2814 "vdda-phy", "vdda-pll",
2815};
2816
2817static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
2818 .type = PHY_TYPE_USB3,
2819 .nlanes = 1,
2820
2821 .serdes_tbl = ipq8074_usb3_serdes_tbl,
2822 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
2823 .tx_tbl = msm8996_usb3_tx_tbl,
2824 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
2825 .rx_tbl = ipq8074_usb3_rx_tbl,
2826 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
2827 .pcs_tbl = ipq8074_usb3_pcs_tbl,
2828 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
2829 .clk_list = msm8996_phy_clk_l,
2830 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2831 .reset_list = msm8996_usb3phy_reset_l,
2832 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2833 .vreg_list = qmp_phy_vreg_l,
2834 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2835 .regs = usb3phy_regs_layout,
2836
2837 .start_ctrl = SERDES_START | PCS_START,
2838 .pwrdn_ctrl = SW_PWRDN,
2839 .phy_status = PHYSTATUS,
2840};
2841
2842static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
2843 .type = PHY_TYPE_PCIE,
2844 .nlanes = 3,
2845
2846 .serdes_tbl = msm8996_pcie_serdes_tbl,
2847 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
2848 .tx_tbl = msm8996_pcie_tx_tbl,
2849 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
2850 .rx_tbl = msm8996_pcie_rx_tbl,
2851 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
2852 .pcs_tbl = msm8996_pcie_pcs_tbl,
2853 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
2854 .clk_list = msm8996_phy_clk_l,
2855 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2856 .reset_list = msm8996_pciephy_reset_l,
2857 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
2858 .vreg_list = qmp_phy_vreg_l,
2859 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2860 .regs = pciephy_regs_layout,
2861
2862 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
2863 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2864 .mask_com_pcs_ready = PCS_READY,
2865 .phy_status = PHYSTATUS,
2866
2867 .has_phy_com_ctrl = true,
2868 .has_lane_rst = true,
2869 .has_pwrdn_delay = true,
2870 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
2871 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
2872};
2873
2874static const struct qmp_phy_cfg msm8996_ufs_cfg = {
2875 .type = PHY_TYPE_UFS,
2876 .nlanes = 1,
2877
2878 .serdes_tbl = msm8996_ufs_serdes_tbl,
2879 .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
2880 .tx_tbl = msm8996_ufs_tx_tbl,
2881 .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
2882 .rx_tbl = msm8996_ufs_rx_tbl,
2883 .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
2884
2885 .clk_list = msm8996_ufs_phy_clk_l,
2886 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
2887
2888 .vreg_list = qmp_phy_vreg_l,
2889 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2890
2891 .regs = msm8996_ufsphy_regs_layout,
2892
2893 .start_ctrl = SERDES_START,
2894 .pwrdn_ctrl = SW_PWRDN,
2895 .phy_status = PHYSTATUS,
2896
2897 .no_pcs_sw_reset = true,
2898};
2899
2900static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
2901 .type = PHY_TYPE_USB3,
2902 .nlanes = 1,
2903
2904 .serdes_tbl = msm8996_usb3_serdes_tbl,
2905 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
2906 .tx_tbl = msm8996_usb3_tx_tbl,
2907 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
2908 .rx_tbl = msm8996_usb3_rx_tbl,
2909 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
2910 .pcs_tbl = msm8996_usb3_pcs_tbl,
2911 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
2912 .clk_list = msm8996_phy_clk_l,
2913 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2914 .reset_list = msm8996_usb3phy_reset_l,
2915 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2916 .vreg_list = qmp_phy_vreg_l,
2917 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2918 .regs = usb3phy_regs_layout,
2919
2920 .start_ctrl = SERDES_START | PCS_START,
2921 .pwrdn_ctrl = SW_PWRDN,
2922 .phy_status = PHYSTATUS,
2923};
2924
2925static const char * const ipq8074_pciephy_clk_l[] = {
2926 "aux", "cfg_ahb",
2927};
2928/* list of resets */
2929static const char * const ipq8074_pciephy_reset_l[] = {
2930 "phy", "common",
2931};
2932
2933static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
2934 .type = PHY_TYPE_PCIE,
2935 .nlanes = 1,
2936
2937 .serdes_tbl = ipq8074_pcie_serdes_tbl,
2938 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
2939 .tx_tbl = ipq8074_pcie_tx_tbl,
2940 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
2941 .rx_tbl = ipq8074_pcie_rx_tbl,
2942 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
2943 .pcs_tbl = ipq8074_pcie_pcs_tbl,
2944 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
2945 .clk_list = ipq8074_pciephy_clk_l,
2946 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
2947 .reset_list = ipq8074_pciephy_reset_l,
2948 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2949 .vreg_list = NULL,
2950 .num_vregs = 0,
2951 .regs = pciephy_regs_layout,
2952
2953 .start_ctrl = SERDES_START | PCS_START,
2954 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2955 .phy_status = PHYSTATUS,
2956
2957 .has_phy_com_ctrl = false,
2958 .has_lane_rst = false,
2959 .has_pwrdn_delay = true,
2960 .pwrdn_delay_min = 995, /* us */
2961 .pwrdn_delay_max = 1005, /* us */
2962};
2963
2964static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
2965 .type = PHY_TYPE_PCIE,
2966 .nlanes = 1,
2967
2968 .serdes_tbl = ipq6018_pcie_serdes_tbl,
2969 .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
2970 .tx_tbl = ipq6018_pcie_tx_tbl,
2971 .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
2972 .rx_tbl = ipq6018_pcie_rx_tbl,
2973 .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
2974 .pcs_tbl = ipq6018_pcie_pcs_tbl,
2975 .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
2976 .clk_list = ipq8074_pciephy_clk_l,
2977 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
2978 .reset_list = ipq8074_pciephy_reset_l,
2979 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2980 .vreg_list = NULL,
2981 .num_vregs = 0,
2982 .regs = ipq_pciephy_gen3_regs_layout,
2983
2984 .start_ctrl = SERDES_START | PCS_START,
2985 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2986
2987 .has_phy_com_ctrl = false,
2988 .has_lane_rst = false,
2989 .has_pwrdn_delay = true,
2990 .pwrdn_delay_min = 995, /* us */
2991 .pwrdn_delay_max = 1005, /* us */
2992};
2993
2994static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2995 .type = PHY_TYPE_PCIE,
2996 .nlanes = 1,
2997
2998 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
2999 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3000 .tx_tbl = sdm845_qmp_pcie_tx_tbl,
3001 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3002 .rx_tbl = sdm845_qmp_pcie_rx_tbl,
3003 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3004 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
3005 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3006 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
3007 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3008 .clk_list = sdm845_pciephy_clk_l,
3009 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3010 .reset_list = sdm845_pciephy_reset_l,
3011 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3012 .vreg_list = qmp_phy_vreg_l,
3013 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3014 .regs = sdm845_qmp_pciephy_regs_layout,
3015
3016 .start_ctrl = PCS_START | SERDES_START,
3017 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3018 .phy_status = PHYSTATUS,
3019
3020 .has_pwrdn_delay = true,
3021 .pwrdn_delay_min = 995, /* us */
3022 .pwrdn_delay_max = 1005, /* us */
3023};
3024
3025static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3026 .type = PHY_TYPE_PCIE,
3027 .nlanes = 1,
3028
3029 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
3030 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3031 .tx_tbl = sdm845_qhp_pcie_tx_tbl,
3032 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3033 .rx_tbl = sdm845_qhp_pcie_rx_tbl,
3034 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
3035 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
3036 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3037 .clk_list = sdm845_pciephy_clk_l,
3038 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3039 .reset_list = sdm845_pciephy_reset_l,
3040 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3041 .vreg_list = qmp_phy_vreg_l,
3042 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3043 .regs = sdm845_qhp_pciephy_regs_layout,
3044
3045 .start_ctrl = PCS_START | SERDES_START,
3046 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3047 .phy_status = PHYSTATUS,
3048
3049 .has_pwrdn_delay = true,
3050 .pwrdn_delay_min = 995, /* us */
3051 .pwrdn_delay_max = 1005, /* us */
3052};
3053
3054static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3055 .type = PHY_TYPE_PCIE,
3056 .nlanes = 1,
3057
3058 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
3059 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3060 .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3061 .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3062 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
3063 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3064 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
3065 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3066 .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
3067 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3068 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
3069 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3070 .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3071 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3072 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
3073 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3074 .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3075 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3076 .clk_list = sdm845_pciephy_clk_l,
3077 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3078 .reset_list = sdm845_pciephy_reset_l,
3079 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3080 .vreg_list = qmp_phy_vreg_l,
3081 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3082 .regs = sm8250_pcie_regs_layout,
3083
3084 .start_ctrl = PCS_START | SERDES_START,
3085 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3086 .phy_status = PHYSTATUS,
3087
3088 .has_pwrdn_delay = true,
3089 .pwrdn_delay_min = 995, /* us */
3090 .pwrdn_delay_max = 1005, /* us */
3091};
3092
3093static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3094 .type = PHY_TYPE_PCIE,
3095 .nlanes = 2,
3096
3097 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
3098 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3099 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
3100 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3101 .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
3102 .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3103 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
3104 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3105 .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
3106 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3107 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
3108 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3109 .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3110 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3111 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
3112 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3113 .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3114 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3115 .clk_list = sdm845_pciephy_clk_l,
3116 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3117 .reset_list = sdm845_pciephy_reset_l,
3118 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3119 .vreg_list = qmp_phy_vreg_l,
3120 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3121 .regs = sm8250_pcie_regs_layout,
3122
3123 .start_ctrl = PCS_START | SERDES_START,
3124 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3125 .phy_status = PHYSTATUS,
3126
3127 .is_dual_lane_phy = true,
3128 .has_pwrdn_delay = true,
3129 .pwrdn_delay_min = 995, /* us */
3130 .pwrdn_delay_max = 1005, /* us */
3131};
3132
3133static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
3134 .type = PHY_TYPE_USB3,
3135 .nlanes = 1,
3136
3137 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
3138 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3139 .tx_tbl = qmp_v3_usb3_tx_tbl,
3140 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3141 .rx_tbl = qmp_v3_usb3_rx_tbl,
3142 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3143 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
3144 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3145 .clk_list = qmp_v3_phy_clk_l,
3146 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3147 .reset_list = msm8996_usb3phy_reset_l,
3148 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3149 .vreg_list = qmp_phy_vreg_l,
3150 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3151 .regs = qmp_v3_usb3phy_regs_layout,
3152
3153 .start_ctrl = SERDES_START | PCS_START,
3154 .pwrdn_ctrl = SW_PWRDN,
3155 .phy_status = PHYSTATUS,
3156
3157 .has_pwrdn_delay = true,
3158 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3159 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3160
3161 .has_phy_dp_com_ctrl = true,
3162 .is_dual_lane_phy = true,
3163};
3164
3165static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
3166 .type = PHY_TYPE_USB3,
3167 .nlanes = 1,
3168
3169 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
3170 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3171 .tx_tbl = qmp_v3_usb3_tx_tbl,
3172 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3173 .rx_tbl = qmp_v3_usb3_rx_tbl,
3174 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3175 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
3176 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3177 .clk_list = qmp_v3_phy_clk_l,
3178 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3179 .reset_list = sc7180_usb3phy_reset_l,
3180 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3181 .vreg_list = qmp_phy_vreg_l,
3182 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3183 .regs = qmp_v3_usb3phy_regs_layout,
3184
3185 .start_ctrl = SERDES_START | PCS_START,
3186 .pwrdn_ctrl = SW_PWRDN,
3187 .phy_status = PHYSTATUS,
3188
3189 .has_pwrdn_delay = true,
3190 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3191 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3192
3193 .has_phy_dp_com_ctrl = true,
3194 .is_dual_lane_phy = true,
3195};
3196
3197static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
3198 .type = PHY_TYPE_DP,
3199 .nlanes = 1,
3200
3201 .serdes_tbl = qmp_v3_dp_serdes_tbl,
3202 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
3203 .tx_tbl = qmp_v3_dp_tx_tbl,
3204 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
3205
3206 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
3207 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
3208 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
3209 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
3210 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
3211 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
3212 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
3213 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
3214
3215 .clk_list = qmp_v3_phy_clk_l,
3216 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3217 .reset_list = sc7180_usb3phy_reset_l,
3218 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3219 .vreg_list = qmp_phy_vreg_l,
3220 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3221 .regs = qmp_v3_usb3phy_regs_layout,
3222
3223 .has_phy_dp_com_ctrl = true,
3224 .is_dual_lane_phy = true,
3225
3226 .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
3227 .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
3228 .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
3229 .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
3230};
3231
3232static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
3233 .usb_cfg = &sc7180_usb3phy_cfg,
3234 .dp_cfg = &sc7180_dpphy_cfg,
3235};
3236
3237static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
3238 .type = PHY_TYPE_USB3,
3239 .nlanes = 1,
3240
3241 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
3242 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
3243 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
3244 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
3245 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
3246 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
3247 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
3248 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
3249 .clk_list = qmp_v3_phy_clk_l,
3250 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
3251 .reset_list = msm8996_usb3phy_reset_l,
3252 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3253 .vreg_list = qmp_phy_vreg_l,
3254 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3255 .regs = qmp_v3_usb3phy_regs_layout,
3256
3257 .start_ctrl = SERDES_START | PCS_START,
3258 .pwrdn_ctrl = SW_PWRDN,
3259 .phy_status = PHYSTATUS,
3260
3261 .has_pwrdn_delay = true,
3262 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3263 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3264};
3265
3266static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
3267 .type = PHY_TYPE_UFS,
3268 .nlanes = 2,
3269
3270 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
3271 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
3272 .tx_tbl = sdm845_ufsphy_tx_tbl,
3273 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
3274 .rx_tbl = sdm845_ufsphy_rx_tbl,
3275 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
3276 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
3277 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
3278 .clk_list = sdm845_ufs_phy_clk_l,
3279 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3280 .vreg_list = qmp_phy_vreg_l,
3281 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3282 .regs = sdm845_ufsphy_regs_layout,
3283
3284 .start_ctrl = SERDES_START,
3285 .pwrdn_ctrl = SW_PWRDN,
3286 .phy_status = PHYSTATUS,
3287
3288 .is_dual_lane_phy = true,
3289 .no_pcs_sw_reset = true,
3290};
3291
3292static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3293 .type = PHY_TYPE_PCIE,
3294 .nlanes = 1,
3295
3296 .serdes_tbl = msm8998_pcie_serdes_tbl,
3297 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3298 .tx_tbl = msm8998_pcie_tx_tbl,
3299 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3300 .rx_tbl = msm8998_pcie_rx_tbl,
3301 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3302 .pcs_tbl = msm8998_pcie_pcs_tbl,
3303 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3304 .clk_list = msm8996_phy_clk_l,
3305 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3306 .reset_list = ipq8074_pciephy_reset_l,
3307 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3308 .vreg_list = qmp_phy_vreg_l,
3309 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3310 .regs = pciephy_regs_layout,
3311
3312 .start_ctrl = SERDES_START | PCS_START,
3313 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3314 .phy_status = PHYSTATUS,
3315};
3316
3317static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
3318 .type = PHY_TYPE_USB3,
3319 .nlanes = 1,
3320
3321 .serdes_tbl = msm8998_usb3_serdes_tbl,
3322 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
3323 .tx_tbl = msm8998_usb3_tx_tbl,
3324 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
3325 .rx_tbl = msm8998_usb3_rx_tbl,
3326 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
3327 .pcs_tbl = msm8998_usb3_pcs_tbl,
3328 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
3329 .clk_list = msm8996_phy_clk_l,
3330 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
3331 .reset_list = msm8996_usb3phy_reset_l,
3332 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3333 .vreg_list = qmp_phy_vreg_l,
3334 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3335 .regs = qmp_v3_usb3phy_regs_layout,
3336
3337 .start_ctrl = SERDES_START | PCS_START,
3338 .pwrdn_ctrl = SW_PWRDN,
3339 .phy_status = PHYSTATUS,
3340
3341 .is_dual_lane_phy = true,
3342};
3343
3344static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
3345 .type = PHY_TYPE_UFS,
3346 .nlanes = 2,
3347
3348 .serdes_tbl = sm8150_ufsphy_serdes_tbl,
3349 .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
3350 .tx_tbl = sm8150_ufsphy_tx_tbl,
3351 .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
3352 .rx_tbl = sm8150_ufsphy_rx_tbl,
3353 .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
3354 .pcs_tbl = sm8150_ufsphy_pcs_tbl,
3355 .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
3356 .clk_list = sdm845_ufs_phy_clk_l,
3357 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3358 .vreg_list = qmp_phy_vreg_l,
3359 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3360 .regs = sm8150_ufsphy_regs_layout,
3361
3362 .start_ctrl = SERDES_START,
3363 .pwrdn_ctrl = SW_PWRDN,
3364 .phy_status = PHYSTATUS,
3365
3366 .is_dual_lane_phy = true,
3367};
3368
3369static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
3370 .type = PHY_TYPE_USB3,
3371 .nlanes = 1,
3372
3373 .serdes_tbl = sm8150_usb3_serdes_tbl,
3374 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3375 .tx_tbl = sm8150_usb3_tx_tbl,
3376 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
3377 .rx_tbl = sm8150_usb3_rx_tbl,
3378 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
3379 .pcs_tbl = sm8150_usb3_pcs_tbl,
3380 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
3381 .clk_list = qmp_v4_phy_clk_l,
3382 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3383 .reset_list = msm8996_usb3phy_reset_l,
3384 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3385 .vreg_list = qmp_phy_vreg_l,
3386 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3387 .regs = qmp_v4_usb3phy_regs_layout,
3388
3389 .start_ctrl = SERDES_START | PCS_START,
3390 .pwrdn_ctrl = SW_PWRDN,
3391 .phy_status = PHYSTATUS,
3392
3393
3394 .has_pwrdn_delay = true,
3395 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3396 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3397
3398 .has_phy_dp_com_ctrl = true,
3399 .is_dual_lane_phy = true,
3400};
3401
3402static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
3403 .type = PHY_TYPE_USB3,
3404 .nlanes = 1,
3405
3406 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3407 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3408 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
3409 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
3410 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
3411 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
3412 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
3413 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
3414 .clk_list = qmp_v4_phy_clk_l,
3415 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3416 .reset_list = msm8996_usb3phy_reset_l,
3417 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3418 .vreg_list = qmp_phy_vreg_l,
3419 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3420 .regs = qmp_v4_usb3_uniphy_regs_layout,
3421
3422 .start_ctrl = SERDES_START | PCS_START,
3423 .pwrdn_ctrl = SW_PWRDN,
3424 .phy_status = PHYSTATUS,
3425
3426 .has_pwrdn_delay = true,
3427 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3428 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3429};
3430
3431static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
3432 .type = PHY_TYPE_USB3,
3433 .nlanes = 1,
3434
3435 .serdes_tbl = sm8150_usb3_serdes_tbl,
3436 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3437 .tx_tbl = sm8250_usb3_tx_tbl,
3438 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
3439 .rx_tbl = sm8250_usb3_rx_tbl,
3440 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
3441 .pcs_tbl = sm8250_usb3_pcs_tbl,
3442 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
3443 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
3444 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3445 .reset_list = msm8996_usb3phy_reset_l,
3446 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3447 .vreg_list = qmp_phy_vreg_l,
3448 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3449 .regs = qmp_v4_usb3phy_regs_layout,
3450
3451 .start_ctrl = SERDES_START | PCS_START,
3452 .pwrdn_ctrl = SW_PWRDN,
3453 .phy_status = PHYSTATUS,
3454
3455 .has_pwrdn_delay = true,
3456 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3457 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3458
3459 .has_phy_dp_com_ctrl = true,
3460 .is_dual_lane_phy = true,
3461};
3462
3463static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
3464 .type = PHY_TYPE_USB3,
3465 .nlanes = 1,
3466
3467 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3468 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3469 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
3470 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
3471 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
3472 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
3473 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3474 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3475 .clk_list = qmp_v4_phy_clk_l,
3476 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3477 .reset_list = msm8996_usb3phy_reset_l,
3478 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3479 .vreg_list = qmp_phy_vreg_l,
3480 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3481 .regs = qmp_v4_usb3_uniphy_regs_layout,
3482
3483 .start_ctrl = SERDES_START | PCS_START,
3484 .pwrdn_ctrl = SW_PWRDN,
3485 .phy_status = PHYSTATUS,
3486
3487 .has_pwrdn_delay = true,
3488 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3489 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3490};
3491
3492static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
3493 .type = PHY_TYPE_DP,
3494 .nlanes = 1,
3495
3496 .serdes_tbl = qmp_v4_dp_serdes_tbl,
3497 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3498 .tx_tbl = qmp_v4_dp_tx_tbl,
3499 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3500
3501 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
3502 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
3503 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
3504 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
3505 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
3506 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
3507 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
3508 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
3509
3510 .clk_list = qmp_v4_phy_clk_l,
3511 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3512 .reset_list = msm8996_usb3phy_reset_l,
3513 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3514 .vreg_list = qmp_phy_vreg_l,
3515 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3516 .regs = qmp_v4_usb3phy_regs_layout,
3517
3518 .has_phy_dp_com_ctrl = true,
3519 .is_dual_lane_phy = true,
3520
3521 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
3522 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
3523 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
3524 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
3525};
3526
3527static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
3528 .usb_cfg = &sm8250_usb3phy_cfg,
3529 .dp_cfg = &sm8250_dpphy_cfg,
3530};
3531
3532static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
3533 .type = PHY_TYPE_USB3,
3534 .nlanes = 1,
3535
3536 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3537 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3538 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
3539 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
3540 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
3541 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
3542 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3543 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3544 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
3545 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
3546 .reset_list = msm8996_usb3phy_reset_l,
3547 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3548 .vreg_list = qmp_phy_vreg_l,
3549 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3550 .regs = qmp_v4_usb3_uniphy_regs_layout,
3551
3552 .start_ctrl = SERDES_START | PCS_START,
3553 .pwrdn_ctrl = SW_PWRDN,
3554 .phy_status = PHYSTATUS,
3555
3556 .has_pwrdn_delay = true,
3557 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3558 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3559};
3560
3561static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
3562 .type = PHY_TYPE_PCIE,
3563 .nlanes = 2,
3564
3565 .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
3566 .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
3567 .tx_tbl = sdx55_qmp_pcie_tx_tbl,
3568 .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
3569 .rx_tbl = sdx55_qmp_pcie_rx_tbl,
3570 .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
3571 .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
3572 .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
3573 .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
3574 .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
3575 .clk_list = sdm845_pciephy_clk_l,
3576 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
3577 .reset_list = sdm845_pciephy_reset_l,
3578 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3579 .vreg_list = qmp_phy_vreg_l,
3580 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3581 .regs = sm8250_pcie_regs_layout,
3582
3583 .start_ctrl = PCS_START | SERDES_START,
3584 .pwrdn_ctrl = SW_PWRDN,
3585 .phy_status = PHYSTATUS_4_20,
3586
3587 .is_dual_lane_phy = true,
3588 .has_pwrdn_delay = true,
3589 .pwrdn_delay_min = 995, /* us */
3590 .pwrdn_delay_max = 1005, /* us */
3591};
3592
3593static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
3594 .type = PHY_TYPE_UFS,
3595 .nlanes = 2,
3596
3597 .serdes_tbl = sm8350_ufsphy_serdes_tbl,
3598 .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
3599 .tx_tbl = sm8350_ufsphy_tx_tbl,
3600 .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
3601 .rx_tbl = sm8350_ufsphy_rx_tbl,
3602 .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
3603 .pcs_tbl = sm8350_ufsphy_pcs_tbl,
3604 .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
3605 .clk_list = sdm845_ufs_phy_clk_l,
3606 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3607 .vreg_list = qmp_phy_vreg_l,
3608 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3609 .regs = sm8150_ufsphy_regs_layout,
3610
3611 .start_ctrl = SERDES_START,
3612 .pwrdn_ctrl = SW_PWRDN,
3613 .phy_status = PHYSTATUS,
3614
3615 .is_dual_lane_phy = true,
3616};
3617
3618static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
3619 .type = PHY_TYPE_USB3,
3620 .nlanes = 1,
3621
3622 .serdes_tbl = sm8150_usb3_serdes_tbl,
3623 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3624 .tx_tbl = sm8350_usb3_tx_tbl,
3625 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
3626 .rx_tbl = sm8350_usb3_rx_tbl,
3627 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
3628 .pcs_tbl = sm8350_usb3_pcs_tbl,
3629 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
3630 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
3631 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3632 .reset_list = msm8996_usb3phy_reset_l,
3633 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3634 .vreg_list = qmp_phy_vreg_l,
3635 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3636 .regs = qmp_v4_usb3phy_regs_layout,
3637
3638 .start_ctrl = SERDES_START | PCS_START,
3639 .pwrdn_ctrl = SW_PWRDN,
3640 .phy_status = PHYSTATUS,
3641
3642 .has_pwrdn_delay = true,
3643 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3644 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3645
3646 .has_phy_dp_com_ctrl = true,
3647 .is_dual_lane_phy = true,
3648};
3649
3650static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
3651 .type = PHY_TYPE_USB3,
3652 .nlanes = 1,
3653
3654 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3655 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3656 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
3657 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
3658 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
3659 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
3660 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
3661 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
3662 .clk_list = qmp_v4_phy_clk_l,
3663 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3664 .reset_list = msm8996_usb3phy_reset_l,
3665 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3666 .vreg_list = qmp_phy_vreg_l,
3667 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3668 .regs = sm8350_usb3_uniphy_regs_layout,
3669
3670 .start_ctrl = SERDES_START | PCS_START,
3671 .pwrdn_ctrl = SW_PWRDN,
3672 .phy_status = PHYSTATUS,
3673
3674 .has_pwrdn_delay = true,
3675 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3676 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3677};
3678
3679static void qcom_qmp_phy_configure_lane(void __iomem *base,
3680 const unsigned int *regs,
3681 const struct qmp_phy_init_tbl tbl[],
3682 int num,
3683 u8 lane_mask)
3684{
3685 int i;
3686 const struct qmp_phy_init_tbl *t = tbl;
3687
3688 if (!t)
3689 return;
3690
3691 for (i = 0; i < num; i++, t++) {
3692 if (!(t->lane_mask & lane_mask))
3693 continue;
3694
3695 if (t->in_layout)
3696 writel(t->val, base + regs[t->offset]);
3697 else
3698 writel(t->val, base + t->offset);
3699 }
3700}
3701
3702static void qcom_qmp_phy_configure(void __iomem *base,
3703 const unsigned int *regs,
3704 const struct qmp_phy_init_tbl tbl[],
3705 int num)
3706{
3707 qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
3708}
3709
3710static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
3711{
3712 struct qcom_qmp *qmp = qphy->qmp;
3713 const struct qmp_phy_cfg *cfg = qphy->cfg;
3714 void __iomem *serdes = qphy->serdes;
3715 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3716 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
3717 int serdes_tbl_num = cfg->serdes_tbl_num;
3718 int ret;
3719
3720 qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
3721 if (cfg->serdes_tbl_sec)
3722 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
3723 cfg->serdes_tbl_num_sec);
3724
3725 if (cfg->type == PHY_TYPE_DP) {
3726 switch (dp_opts->link_rate) {
3727 case 1620:
3728 qcom_qmp_phy_configure(serdes, cfg->regs,
3729 cfg->serdes_tbl_rbr,
3730 cfg->serdes_tbl_rbr_num);
3731 break;
3732 case 2700:
3733 qcom_qmp_phy_configure(serdes, cfg->regs,
3734 cfg->serdes_tbl_hbr,
3735 cfg->serdes_tbl_hbr_num);
3736 break;
3737 case 5400:
3738 qcom_qmp_phy_configure(serdes, cfg->regs,
3739 cfg->serdes_tbl_hbr2,
3740 cfg->serdes_tbl_hbr2_num);
3741 break;
3742 case 8100:
3743 qcom_qmp_phy_configure(serdes, cfg->regs,
3744 cfg->serdes_tbl_hbr3,
3745 cfg->serdes_tbl_hbr3_num);
3746 break;
3747 default:
3748 /* Other link rates aren't supported */
3749 return -EINVAL;
3750 }
3751 }
3752
3753
3754 if (cfg->has_phy_com_ctrl) {
3755 void __iomem *status;
3756 unsigned int mask, val;
3757
3758 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
3759 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
3760 SERDES_START | PCS_START);
3761
3762 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
3763 mask = cfg->mask_com_pcs_ready;
3764
3765 ret = readl_poll_timeout(status, val, (val & mask), 10,
3766 PHY_INIT_COMPLETE_TIMEOUT);
3767 if (ret) {
3768 dev_err(qmp->dev,
3769 "phy common block init timed-out\n");
3770 return ret;
3771 }
3772 }
3773
3774 return 0;
3775}
3776
3777static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
3778{
3779 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
3780 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
3781 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
3782
3783 /* Turn on BIAS current for PHY/PLL */
3784 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
3785 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
3786 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
3787
3788 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
3789
3790 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
3791 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
3792 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
3793 DP_PHY_PD_CTL_DP_CLAMP_EN,
3794 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
3795
3796 writel(QSERDES_V3_COM_BIAS_EN |
3797 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
3798 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
3799 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
3800 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
3801
3802 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
3803 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
3804 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
3805 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
3806 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
3807 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
3808 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
3809 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
3810 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
3811 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
3812 qphy->dp_aux_cfg = 0;
3813
3814 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
3815 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
3816 PHY_AUX_REQ_ERR_MASK,
3817 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
3818}
3819
3820static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
3821 { 0x00, 0x0c, 0x15, 0x1a },
3822 { 0x02, 0x0e, 0x16, 0xff },
3823 { 0x02, 0x11, 0xff, 0xff },
3824 { 0x04, 0xff, 0xff, 0xff }
3825};
3826
3827static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
3828 { 0x02, 0x12, 0x16, 0x1a },
3829 { 0x09, 0x19, 0x1f, 0xff },
3830 { 0x10, 0x1f, 0xff, 0xff },
3831 { 0x1f, 0xff, 0xff, 0xff }
3832};
3833
3834static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
3835 { 0x00, 0x0c, 0x14, 0x19 },
3836 { 0x00, 0x0b, 0x12, 0xff },
3837 { 0x00, 0x0b, 0xff, 0xff },
3838 { 0x04, 0xff, 0xff, 0xff }
3839};
3840
3841static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
3842 { 0x08, 0x0f, 0x16, 0x1f },
3843 { 0x11, 0x1e, 0x1f, 0xff },
3844 { 0x19, 0x1f, 0xff, 0xff },
3845 { 0x1f, 0xff, 0xff, 0xff }
3846};
3847
3848static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
3849 unsigned int drv_lvl_reg, unsigned int emp_post_reg)
3850{
3851 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3852 unsigned int v_level = 0, p_level = 0;
3853 u8 voltage_swing_cfg, pre_emphasis_cfg;
3854 int i;
3855
3856 for (i = 0; i < dp_opts->lanes; i++) {
3857 v_level = max(v_level, dp_opts->voltage[i]);
3858 p_level = max(p_level, dp_opts->pre[i]);
3859 }
3860
3861 if (dp_opts->link_rate <= 2700) {
3862 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
3863 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
3864 } else {
3865 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
3866 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
3867 }
3868
3869 /* TODO: Move check to config check */
3870 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
3871 return -EINVAL;
3872
3873 /* Enable MUX to use Cursor values from these registers */
3874 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
3875 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
3876
3877 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
3878 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
3879 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
3880 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
3881
3882 return 0;
3883}
3884
3885static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
3886{
3887 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3888 u32 bias_en, drvr_en;
3889
3890 if (qcom_qmp_phy_configure_dp_swing(qphy,
3891 QSERDES_V3_TX_TX_DRV_LVL,
3892 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
3893 return;
3894
3895 if (dp_opts->lanes == 1) {
3896 bias_en = 0x3e;
3897 drvr_en = 0x13;
3898 } else {
3899 bias_en = 0x3f;
3900 drvr_en = 0x10;
3901 }
3902
3903 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
3904 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
3905 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
3906 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
3907}
3908
3909static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
3910{
3911 u32 val;
3912 bool reverse = false;
3913
3914 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
3915 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
3916
3917 /*
3918 * TODO: Assume orientation is CC1 for now and two lanes, need to
3919 * use type-c connector to understand orientation and lanes.
3920 *
3921 * Otherwise val changes to be like below if this code understood
3922 * the orientation of the type-c cable.
3923 *
3924 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
3925 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
3926 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
3927 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
3928 * if (orientation == ORIENTATION_CC2)
3929 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
3930 */
3931 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
3932 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
3933
3934 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
3935
3936 return reverse;
3937}
3938
3939static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
3940{
3941 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
3942 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3943 u32 phy_vco_div, status;
3944 unsigned long pixel_freq;
3945
3946 qcom_qmp_phy_configure_dp_mode(qphy);
3947
3948 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
3949 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
3950
3951 switch (dp_opts->link_rate) {
3952 case 1620:
3953 phy_vco_div = 0x1;
3954 pixel_freq = 1620000000UL / 2;
3955 break;
3956 case 2700:
3957 phy_vco_div = 0x1;
3958 pixel_freq = 2700000000UL / 2;
3959 break;
3960 case 5400:
3961 phy_vco_div = 0x2;
3962 pixel_freq = 5400000000UL / 4;
3963 break;
3964 case 8100:
3965 phy_vco_div = 0x0;
3966 pixel_freq = 8100000000UL / 6;
3967 break;
3968 default:
3969 /* Other link rates aren't supported */
3970 return -EINVAL;
3971 }
3972 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
3973
3974 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
3975 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
3976
3977 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
3978 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
3979 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
3980 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
3981 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
3982
3983 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
3984
3985 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
3986 status,
3987 ((status & BIT(0)) > 0),
3988 500,
3989 10000))
3990 return -ETIMEDOUT;
3991
3992 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
3993
3994 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
3995 status,
3996 ((status & BIT(1)) > 0),
3997 500,
3998 10000))
3999 return -ETIMEDOUT;
4000
4001 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4002 udelay(2000);
4003 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4004
4005 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4006 status,
4007 ((status & BIT(1)) > 0),
4008 500,
4009 10000);
4010}
4011
4012/*
4013 * We need to calibrate the aux setting here as many times
4014 * as the caller tries
4015 */
4016static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
4017{
4018 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
4019 u8 val;
4020
4021 qphy->dp_aux_cfg++;
4022 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4023 val = cfg1_settings[qphy->dp_aux_cfg];
4024
4025 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4026
4027 return 0;
4028}
4029
4030static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
4031{
4032 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4033 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4034 qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4035
4036 /* Turn on BIAS current for PHY/PLL */
4037 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
4038
4039 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4040 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4041 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4042 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4043 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4044 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4045 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4046 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4047 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4048 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4049 qphy->dp_aux_cfg = 0;
4050
4051 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4052 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4053 PHY_AUX_REQ_ERR_MASK,
4054 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
4055}
4056
4057static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
4058{
4059 /* Program default values before writing proper values */
4060 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4061 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4062
4063 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4064 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4065
4066 qcom_qmp_phy_configure_dp_swing(qphy,
4067 QSERDES_V4_TX_TX_DRV_LVL,
4068 QSERDES_V4_TX_TX_EMP_POST1_LVL);
4069}
4070
4071static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
4072{
4073 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4074 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4075 u32 phy_vco_div, status;
4076 unsigned long pixel_freq;
4077 u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
4078 bool reverse;
4079
4080 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
4081
4082 reverse = qcom_qmp_phy_configure_dp_mode(qphy);
4083
4084 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4085 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4086
4087 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
4088 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
4089
4090 switch (dp_opts->link_rate) {
4091 case 1620:
4092 phy_vco_div = 0x1;
4093 pixel_freq = 1620000000UL / 2;
4094 break;
4095 case 2700:
4096 phy_vco_div = 0x1;
4097 pixel_freq = 2700000000UL / 2;
4098 break;
4099 case 5400:
4100 phy_vco_div = 0x2;
4101 pixel_freq = 5400000000UL / 4;
4102 break;
4103 case 8100:
4104 phy_vco_div = 0x0;
4105 pixel_freq = 8100000000UL / 6;
4106 break;
4107 default:
4108 /* Other link rates aren't supported */
4109 return -EINVAL;
4110 }
4111 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
4112
4113 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4114 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4115
4116 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4117 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4118 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4119 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4120
4121 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
4122
4123 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
4124 status,
4125 ((status & BIT(0)) > 0),
4126 500,
4127 10000))
4128 return -ETIMEDOUT;
4129
4130 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4131 status,
4132 ((status & BIT(0)) > 0),
4133 500,
4134 10000))
4135 return -ETIMEDOUT;
4136
4137 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4138 status,
4139 ((status & BIT(1)) > 0),
4140 500,
4141 10000))
4142 return -ETIMEDOUT;
4143
4144 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4145
4146 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4147 status,
4148 ((status & BIT(0)) > 0),
4149 500,
4150 10000))
4151 return -ETIMEDOUT;
4152
4153 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4154 status,
4155 ((status & BIT(1)) > 0),
4156 500,
4157 10000))
4158 return -ETIMEDOUT;
4159
4160 /*
4161 * At least for 7nm DP PHY this has to be done after enabling link
4162 * clock.
4163 */
4164
4165 if (dp_opts->lanes == 1) {
4166 bias0_en = reverse ? 0x3e : 0x15;
4167 bias1_en = reverse ? 0x15 : 0x3e;
4168 drvr0_en = reverse ? 0x13 : 0x10;
4169 drvr1_en = reverse ? 0x10 : 0x13;
4170 } else if (dp_opts->lanes == 2) {
4171 bias0_en = reverse ? 0x3f : 0x15;
4172 bias1_en = reverse ? 0x15 : 0x3f;
4173 drvr0_en = 0x10;
4174 drvr1_en = 0x10;
4175 } else {
4176 bias0_en = 0x3f;
4177 bias1_en = 0x3f;
4178 drvr0_en = 0x10;
4179 drvr1_en = 0x10;
4180 }
4181
4182 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4183 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4184 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4185 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4186
4187 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4188 udelay(2000);
4189 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4190
4191 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4192 status,
4193 ((status & BIT(1)) > 0),
4194 500,
4195 10000))
4196 return -ETIMEDOUT;
4197
4198 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
4199 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
4200
4201 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4202 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4203
4204 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4205 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4206
4207 return 0;
4208}
4209
4210/*
4211 * We need to calibrate the aux setting here as many times
4212 * as the caller tries
4213 */
4214static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
4215{
4216 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
4217 u8 val;
4218
4219 qphy->dp_aux_cfg++;
4220 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4221 val = cfg1_settings[qphy->dp_aux_cfg];
4222
4223 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4224
4225 return 0;
4226}
4227
4228static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
4229{
4230 const struct phy_configure_opts_dp *dp_opts = &opts->dp;
4231 struct qmp_phy *qphy = phy_get_drvdata(phy);
4232 const struct qmp_phy_cfg *cfg = qphy->cfg;
4233
4234 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
4235 if (qphy->dp_opts.set_voltages) {
4236 cfg->configure_dp_tx(qphy);
4237 qphy->dp_opts.set_voltages = 0;
4238 }
4239
4240 return 0;
4241}
4242
4243static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
4244{
4245 struct qmp_phy *qphy = phy_get_drvdata(phy);
4246 const struct qmp_phy_cfg *cfg = qphy->cfg;
4247
4248 if (cfg->calibrate_dp_phy)
4249 return cfg->calibrate_dp_phy(qphy);
4250
4251 return 0;
4252}
4253
4254static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
4255{
4256 struct qcom_qmp *qmp = qphy->qmp;
4257 const struct qmp_phy_cfg *cfg = qphy->cfg;
4258 void __iomem *serdes = qphy->serdes;
4259 void __iomem *pcs = qphy->pcs;
4260 void __iomem *dp_com = qmp->dp_com;
4261 int ret, i;
4262
4263 mutex_lock(&qmp->phy_mutex);
4264 if (qmp->init_count++) {
4265 mutex_unlock(&qmp->phy_mutex);
4266 return 0;
4267 }
4268
4269 /* turn on regulator supplies */
4270 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
4271 if (ret) {
4272 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
4273 goto err_reg_enable;
4274 }
4275
4276 for (i = 0; i < cfg->num_resets; i++) {
4277 ret = reset_control_assert(qmp->resets[i]);
4278 if (ret) {
4279 dev_err(qmp->dev, "%s reset assert failed\n",
4280 cfg->reset_list[i]);
4281 goto err_rst_assert;
4282 }
4283 }
4284
4285 for (i = cfg->num_resets - 1; i >= 0; i--) {
4286 ret = reset_control_deassert(qmp->resets[i]);
4287 if (ret) {
4288 dev_err(qmp->dev, "%s reset deassert failed\n",
4289 qphy->cfg->reset_list[i]);
4290 goto err_rst;
4291 }
4292 }
4293
4294 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
4295 if (ret)
4296 goto err_rst;
4297
4298 if (cfg->has_phy_dp_com_ctrl) {
4299 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
4300 SW_PWRDN);
4301 /* override hardware control for reset of qmp phy */
4302 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4303 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4304 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
4305
4306 /* Default type-c orientation, i.e CC1 */
4307 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
4308
4309 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
4310 USB3_MODE | DP_MODE);
4311
4312 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
4313 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4314 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4315 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
4316
4317 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
4318 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
4319 }
4320
4321 if (cfg->has_phy_com_ctrl) {
4322 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4323 SW_PWRDN);
4324 } else {
4325 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
4326 qphy_setbits(pcs,
4327 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4328 cfg->pwrdn_ctrl);
4329 else
4330 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
4331 cfg->pwrdn_ctrl);
4332 }
4333
4334 mutex_unlock(&qmp->phy_mutex);
4335
4336 return 0;
4337
4338err_rst:
4339 while (++i < cfg->num_resets)
4340 reset_control_assert(qmp->resets[i]);
4341err_rst_assert:
4342 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4343err_reg_enable:
4344 mutex_unlock(&qmp->phy_mutex);
4345
4346 return ret;
4347}
4348
4349static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
4350{
4351 struct qcom_qmp *qmp = qphy->qmp;
4352 const struct qmp_phy_cfg *cfg = qphy->cfg;
4353 void __iomem *serdes = qphy->serdes;
4354 int i = cfg->num_resets;
4355
4356 mutex_lock(&qmp->phy_mutex);
4357 if (--qmp->init_count) {
4358 mutex_unlock(&qmp->phy_mutex);
4359 return 0;
4360 }
4361
4362 reset_control_assert(qmp->ufs_reset);
4363 if (cfg->has_phy_com_ctrl) {
4364 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4365 SERDES_START | PCS_START);
4366 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
4367 SW_RESET);
4368 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4369 SW_PWRDN);
4370 }
4371
4372 while (--i >= 0)
4373 reset_control_assert(qmp->resets[i]);
4374
4375 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4376
4377 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4378
4379 mutex_unlock(&qmp->phy_mutex);
4380
4381 return 0;
4382}
4383
4384static int qcom_qmp_phy_init(struct phy *phy)
4385{
4386 struct qmp_phy *qphy = phy_get_drvdata(phy);
4387 struct qcom_qmp *qmp = qphy->qmp;
4388 const struct qmp_phy_cfg *cfg = qphy->cfg;
4389 int ret;
4390 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
4391
4392 if (cfg->no_pcs_sw_reset) {
4393 /*
4394 * Get UFS reset, which is delayed until now to avoid a
4395 * circular dependency where UFS needs its PHY, but the PHY
4396 * needs this UFS reset.
4397 */
4398 if (!qmp->ufs_reset) {
4399 qmp->ufs_reset =
4400 devm_reset_control_get_exclusive(qmp->dev,
4401 "ufsphy");
4402
4403 if (IS_ERR(qmp->ufs_reset)) {
4404 ret = PTR_ERR(qmp->ufs_reset);
4405 dev_err(qmp->dev,
4406 "failed to get UFS reset: %d\n",
4407 ret);
4408
4409 qmp->ufs_reset = NULL;
4410 return ret;
4411 }
4412 }
4413
4414 ret = reset_control_assert(qmp->ufs_reset);
4415 if (ret)
4416 return ret;
4417 }
4418
4419 ret = qcom_qmp_phy_com_init(qphy);
4420 if (ret)
4421 return ret;
4422
4423 if (cfg->type == PHY_TYPE_DP)
4424 cfg->dp_aux_init(qphy);
4425
4426 return 0;
4427}
4428
4429static int qcom_qmp_phy_power_on(struct phy *phy)
4430{
4431 struct qmp_phy *qphy = phy_get_drvdata(phy);
4432 struct qcom_qmp *qmp = qphy->qmp;
4433 const struct qmp_phy_cfg *cfg = qphy->cfg;
4434 void __iomem *tx = qphy->tx;
4435 void __iomem *rx = qphy->rx;
4436 void __iomem *pcs = qphy->pcs;
4437 void __iomem *pcs_misc = qphy->pcs_misc;
4438 void __iomem *status;
4439 unsigned int mask, val, ready;
4440 int ret;
4441
4442 qcom_qmp_phy_serdes_init(qphy);
4443
4444 if (cfg->has_lane_rst) {
4445 ret = reset_control_deassert(qphy->lane_rst);
4446 if (ret) {
4447 dev_err(qmp->dev, "lane%d reset deassert failed\n",
4448 qphy->index);
4449 goto err_lane_rst;
4450 }
4451 }
4452
4453 ret = clk_prepare_enable(qphy->pipe_clk);
4454 if (ret) {
4455 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
4456 goto err_clk_enable;
4457 }
4458
4459 /* Tx, Rx, and PCS configurations */
4460 qcom_qmp_phy_configure_lane(tx, cfg->regs,
4461 cfg->tx_tbl, cfg->tx_tbl_num, 1);
4462 if (cfg->tx_tbl_sec)
4463 qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
4464 cfg->tx_tbl_num_sec, 1);
4465
4466 /* Configuration for other LANE for USB-DP combo PHY */
4467 if (cfg->is_dual_lane_phy) {
4468 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4469 cfg->tx_tbl, cfg->tx_tbl_num, 2);
4470 if (cfg->tx_tbl_sec)
4471 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4472 cfg->tx_tbl_sec,
4473 cfg->tx_tbl_num_sec, 2);
4474 }
4475
4476 /* Configure special DP tx tunings */
4477 if (cfg->type == PHY_TYPE_DP)
4478 cfg->configure_dp_tx(qphy);
4479
4480 qcom_qmp_phy_configure_lane(rx, cfg->regs,
4481 cfg->rx_tbl, cfg->rx_tbl_num, 1);
4482 if (cfg->rx_tbl_sec)
4483 qcom_qmp_phy_configure_lane(rx, cfg->regs,
4484 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
4485
4486 if (cfg->is_dual_lane_phy) {
4487 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4488 cfg->rx_tbl, cfg->rx_tbl_num, 2);
4489 if (cfg->rx_tbl_sec)
4490 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4491 cfg->rx_tbl_sec,
4492 cfg->rx_tbl_num_sec, 2);
4493 }
4494
4495 /* Configure link rate, swing, etc. */
4496 if (cfg->type == PHY_TYPE_DP) {
4497 cfg->configure_dp_phy(qphy);
4498 } else {
4499 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
4500 if (cfg->pcs_tbl_sec)
4501 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
4502 cfg->pcs_tbl_num_sec);
4503 }
4504
4505 ret = reset_control_deassert(qmp->ufs_reset);
4506 if (ret)
4507 goto err_lane_rst;
4508
4509 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
4510 cfg->pcs_misc_tbl_num);
4511 if (cfg->pcs_misc_tbl_sec)
4512 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
4513 cfg->pcs_misc_tbl_num_sec);
4514
4515 /*
4516 * Pull out PHY from POWER DOWN state.
4517 * This is active low enable signal to power-down PHY.
4518 */
4519 if(cfg->type == PHY_TYPE_PCIE)
4520 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
4521
4522 if (cfg->has_pwrdn_delay)
4523 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
4524
4525 if (cfg->type != PHY_TYPE_DP) {
4526 /* Pull PHY out of reset state */
4527 if (!cfg->no_pcs_sw_reset)
4528 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4529 /* start SerDes and Phy-Coding-Sublayer */
4530 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
4531
4532 if (cfg->type == PHY_TYPE_UFS) {
4533 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
4534 mask = PCS_READY;
4535 ready = PCS_READY;
4536 } else {
4537 status = pcs + cfg->regs[QPHY_PCS_STATUS];
4538 mask = cfg->phy_status;
4539 ready = 0;
4540 }
4541
4542 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
4543 PHY_INIT_COMPLETE_TIMEOUT);
4544 if (ret) {
4545 dev_err(qmp->dev, "phy initialization timed-out\n");
4546 goto err_pcs_ready;
4547 }
4548 }
4549 return 0;
4550
4551err_pcs_ready:
4552 clk_disable_unprepare(qphy->pipe_clk);
4553err_clk_enable:
4554 if (cfg->has_lane_rst)
4555 reset_control_assert(qphy->lane_rst);
4556err_lane_rst:
4557 return ret;
4558}
4559
4560static int qcom_qmp_phy_power_off(struct phy *phy)
4561{
4562 struct qmp_phy *qphy = phy_get_drvdata(phy);
4563 const struct qmp_phy_cfg *cfg = qphy->cfg;
4564
4565 clk_disable_unprepare(qphy->pipe_clk);
4566
4567 if (cfg->type == PHY_TYPE_DP) {
4568 /* Assert DP PHY power down */
4569 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4570 } else {
4571 /* PHY reset */
4572 if (!cfg->no_pcs_sw_reset)
4573 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4574
4575 /* stop SerDes and Phy-Coding-Sublayer */
4576 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
4577
4578 /* Put PHY into POWER DOWN state: active low */
4579 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
4580 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4581 cfg->pwrdn_ctrl);
4582 } else {
4583 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
4584 cfg->pwrdn_ctrl);
4585 }
4586 }
4587
4588 return 0;
4589}
4590
4591static int qcom_qmp_phy_exit(struct phy *phy)
4592{
4593 struct qmp_phy *qphy = phy_get_drvdata(phy);
4594 const struct qmp_phy_cfg *cfg = qphy->cfg;
4595
4596 if (cfg->has_lane_rst)
4597 reset_control_assert(qphy->lane_rst);
4598
4599 qcom_qmp_phy_com_exit(qphy);
4600
4601 return 0;
4602}
4603
4604static int qcom_qmp_phy_enable(struct phy *phy)
4605{
4606 int ret;
4607
4608 ret = qcom_qmp_phy_init(phy);
4609 if (ret)
4610 return ret;
4611
4612 ret = qcom_qmp_phy_power_on(phy);
4613 if (ret)
4614 qcom_qmp_phy_exit(phy);
4615
4616 return ret;
4617}
4618
4619static int qcom_qmp_phy_disable(struct phy *phy)
4620{
4621 int ret;
4622
4623 ret = qcom_qmp_phy_power_off(phy);
4624 if (ret)
4625 return ret;
4626 return qcom_qmp_phy_exit(phy);
4627}
4628
4629static int qcom_qmp_phy_set_mode(struct phy *phy,
4630 enum phy_mode mode, int submode)
4631{
4632 struct qmp_phy *qphy = phy_get_drvdata(phy);
4633
4634 qphy->mode = mode;
4635
4636 return 0;
4637}
4638
4639static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
4640{
4641 const struct qmp_phy_cfg *cfg = qphy->cfg;
4642 void __iomem *pcs = qphy->pcs;
4643 void __iomem *pcs_misc = qphy->pcs_misc;
4644 u32 intr_mask;
4645
4646 if (qphy->mode == PHY_MODE_USB_HOST_SS ||
4647 qphy->mode == PHY_MODE_USB_DEVICE_SS)
4648 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
4649 else
4650 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
4651
4652 /* Clear any pending interrupts status */
4653 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4654 /* Writing 1 followed by 0 clears the interrupt */
4655 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4656
4657 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
4658 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
4659
4660 /* Enable required PHY autonomous mode interrupts */
4661 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
4662
4663 /* Enable i/o clamp_n for autonomous mode */
4664 if (pcs_misc)
4665 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
4666}
4667
4668static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
4669{
4670 const struct qmp_phy_cfg *cfg = qphy->cfg;
4671 void __iomem *pcs = qphy->pcs;
4672 void __iomem *pcs_misc = qphy->pcs_misc;
4673
4674 /* Disable i/o clamp_n on resume for normal mode */
4675 if (pcs_misc)
4676 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
4677
4678 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
4679 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
4680
4681 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4682 /* Writing 1 followed by 0 clears the interrupt */
4683 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
4684}
4685
4686static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
4687{
4688 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4689 struct qmp_phy *qphy = qmp->phys[0];
4690 const struct qmp_phy_cfg *cfg = qphy->cfg;
4691
4692 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
4693
4694 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
4695 if (cfg->type != PHY_TYPE_USB3)
4696 return 0;
4697
4698 if (!qmp->init_count) {
4699 dev_vdbg(dev, "PHY not initialized, bailing out\n");
4700 return 0;
4701 }
4702
4703 qcom_qmp_phy_enable_autonomous_mode(qphy);
4704
4705 clk_disable_unprepare(qphy->pipe_clk);
4706 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4707
4708 return 0;
4709}
4710
4711static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
4712{
4713 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4714 struct qmp_phy *qphy = qmp->phys[0];
4715 const struct qmp_phy_cfg *cfg = qphy->cfg;
4716 int ret = 0;
4717
4718 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
4719
4720 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
4721 if (cfg->type != PHY_TYPE_USB3)
4722 return 0;
4723
4724 if (!qmp->init_count) {
4725 dev_vdbg(dev, "PHY not initialized, bailing out\n");
4726 return 0;
4727 }
4728
4729 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
4730 if (ret)
4731 return ret;
4732
4733 ret = clk_prepare_enable(qphy->pipe_clk);
4734 if (ret) {
4735 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
4736 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4737 return ret;
4738 }
4739
4740 qcom_qmp_phy_disable_autonomous_mode(qphy);
4741
4742 return 0;
4743}
4744
4745static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
4746{
4747 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4748 int num = cfg->num_vregs;
4749 int i;
4750
4751 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
4752 if (!qmp->vregs)
4753 return -ENOMEM;
4754
4755 for (i = 0; i < num; i++)
4756 qmp->vregs[i].supply = cfg->vreg_list[i];
4757
4758 return devm_regulator_bulk_get(dev, num, qmp->vregs);
4759}
4760
4761static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
4762{
4763 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4764 int i;
4765
4766 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
4767 sizeof(*qmp->resets), GFP_KERNEL);
4768 if (!qmp->resets)
4769 return -ENOMEM;
4770
4771 for (i = 0; i < cfg->num_resets; i++) {
4772 struct reset_control *rst;
4773 const char *name = cfg->reset_list[i];
4774
4775 rst = devm_reset_control_get(dev, name);
4776 if (IS_ERR(rst)) {
4777 dev_err(dev, "failed to get %s reset\n", name);
4778 return PTR_ERR(rst);
4779 }
4780 qmp->resets[i] = rst;
4781 }
4782
4783 return 0;
4784}
4785
4786static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
4787{
4788 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4789 int num = cfg->num_clks;
4790 int i;
4791
4792 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
4793 if (!qmp->clks)
4794 return -ENOMEM;
4795
4796 for (i = 0; i < num; i++)
4797 qmp->clks[i].id = cfg->clk_list[i];
4798
4799 return devm_clk_bulk_get(dev, num, qmp->clks);
4800}
4801
4802static void phy_clk_release_provider(void *res)
4803{
4804 of_clk_del_provider(res);
4805}
4806
4807/*
4808 * Register a fixed rate pipe clock.
4809 *
4810 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
4811 * controls it. The <s>_pipe_clk coming out of the GCC is requested
4812 * by the PHY driver for its operations.
4813 * We register the <s>_pipe_clksrc here. The gcc driver takes care
4814 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
4815 * Below picture shows this relationship.
4816 *
4817 * +---------------+
4818 * | PHY block |<<---------------------------------------+
4819 * | | |
4820 * | +-------+ | +-----+ |
4821 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4822 * clk | +-------+ | +-----+
4823 * +---------------+
4824 */
4825static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
4826{
4827 struct clk_fixed_rate *fixed;
4828 struct clk_init_data init = { };
4829 int ret;
4830
4831 ret = of_property_read_string(np, "clock-output-names", &init.name);
4832 if (ret) {
4833 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
4834 return ret;
4835 }
4836
4837 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
4838 if (!fixed)
4839 return -ENOMEM;
4840
4841 init.ops = &clk_fixed_rate_ops;
4842
4843 /* controllers using QMP phys use 125MHz pipe clock interface */
4844 fixed->fixed_rate = 125000000;
4845 fixed->hw.init = &init;
4846
4847 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
4848 if (ret)
4849 return ret;
4850
4851 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
4852 if (ret)
4853 return ret;
4854
4855 /*
4856 * Roll a devm action because the clock provider is the child node, but
4857 * the child node is not actually a device.
4858 */
4859 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
4860 if (ret)
4861 phy_clk_release_provider(np);
4862
4863 return ret;
4864}
4865
4866/*
4867 * Display Port PLL driver block diagram for branch clocks
4868 *
4869 * +------------------------------+
4870 * | DP_VCO_CLK |
4871 * | |
4872 * | +-------------------+ |
4873 * | | (DP PLL/VCO) | |
4874 * | +---------+---------+ |
4875 * | v |
4876 * | +----------+-----------+ |
4877 * | | hsclk_divsel_clk_src | |
4878 * | +----------+-----------+ |
4879 * +------------------------------+
4880 * |
4881 * +---------<---------v------------>----------+
4882 * | |
4883 * +--------v----------------+ |
4884 * | dp_phy_pll_link_clk | |
4885 * | link_clk | |
4886 * +--------+----------------+ |
4887 * | |
4888 * | |
4889 * v v
4890 * Input to DISPCC block |
4891 * for link clk, crypto clk |
4892 * and interface clock |
4893 * |
4894 * |
4895 * +--------<------------+-----------------+---<---+
4896 * | | |
4897 * +----v---------+ +--------v-----+ +--------v------+
4898 * | vco_divided | | vco_divided | | vco_divided |
4899 * | _clk_src | | _clk_src | | _clk_src |
4900 * | | | | | |
4901 * |divsel_six | | divsel_two | | divsel_four |
4902 * +-------+------+ +-----+--------+ +--------+------+
4903 * | | |
4904 * v---->----------v-------------<------v
4905 * |
4906 * +----------+-----------------+
4907 * | dp_phy_pll_vco_div_clk |
4908 * +---------+------------------+
4909 * |
4910 * v
4911 * Input to DISPCC block
4912 * for DP pixel clock
4913 *
4914 */
4915static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
4916 struct clk_rate_request *req)
4917{
4918 switch (req->rate) {
4919 case 1620000000UL / 2:
4920 case 2700000000UL / 2:
4921 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
4922 return 0;
4923 default:
4924 return -EINVAL;
4925 }
4926}
4927
4928static unsigned long
4929qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
4930{
4931 const struct qmp_phy_dp_clks *dp_clks;
4932 const struct qmp_phy *qphy;
4933 const struct phy_configure_opts_dp *dp_opts;
4934
4935 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
4936 qphy = dp_clks->qphy;
4937 dp_opts = &qphy->dp_opts;
4938
4939 switch (dp_opts->link_rate) {
4940 case 1620:
4941 return 1620000000UL / 2;
4942 case 2700:
4943 return 2700000000UL / 2;
4944 case 5400:
4945 return 5400000000UL / 4;
4946 case 8100:
4947 return 8100000000UL / 6;
4948 default:
4949 return 0;
4950 }
4951}
4952
4953static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
4954 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
4955 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
4956};
4957
4958static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
4959 struct clk_rate_request *req)
4960{
4961 switch (req->rate) {
4962 case 162000000:
4963 case 270000000:
4964 case 540000000:
4965 case 810000000:
4966 return 0;
4967 default:
4968 return -EINVAL;
4969 }
4970}
4971
4972static unsigned long
4973qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
4974{
4975 const struct qmp_phy_dp_clks *dp_clks;
4976 const struct qmp_phy *qphy;
4977 const struct phy_configure_opts_dp *dp_opts;
4978
4979 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
4980 qphy = dp_clks->qphy;
4981 dp_opts = &qphy->dp_opts;
4982
4983 switch (dp_opts->link_rate) {
4984 case 1620:
4985 case 2700:
4986 case 5400:
4987 case 8100:
4988 return dp_opts->link_rate * 100000;
4989 default:
4990 return 0;
4991 }
4992}
4993
4994static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
4995 .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
4996 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
4997};
4998
4999static struct clk_hw *
5000qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
5001{
5002 struct qmp_phy_dp_clks *dp_clks = data;
5003 unsigned int idx = clkspec->args[0];
5004
5005 if (idx >= 2) {
5006 pr_err("%s: invalid index %u\n", __func__, idx);
5007 return ERR_PTR(-EINVAL);
5008 }
5009
5010 if (idx == 0)
5011 return &dp_clks->dp_link_hw;
5012
5013 return &dp_clks->dp_pixel_hw;
5014}
5015
5016static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
5017 struct device_node *np)
5018{
5019 struct clk_init_data init = { };
5020 struct qmp_phy_dp_clks *dp_clks;
5021 int ret;
5022
5023 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
5024 if (!dp_clks)
5025 return -ENOMEM;
5026
5027 dp_clks->qphy = qphy;
5028 qphy->dp_clks = dp_clks;
5029
5030 init.ops = &qcom_qmp_dp_link_clk_ops;
5031 init.name = "qmp_dp_phy_pll_link_clk";
5032 dp_clks->dp_link_hw.init = &init;
5033 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
5034 if (ret)
5035 return ret;
5036
5037 init.ops = &qcom_qmp_dp_pixel_clk_ops;
5038 init.name = "qmp_dp_phy_pll_vco_div_clk";
5039 dp_clks->dp_pixel_hw.init = &init;
5040 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
5041 if (ret)
5042 return ret;
5043
5044 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
5045 if (ret)
5046 return ret;
5047
5048 /*
5049 * Roll a devm action because the clock provider is the child node, but
5050 * the child node is not actually a device.
5051 */
5052 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
5053 if (ret)
5054 phy_clk_release_provider(np);
5055
5056 return ret;
5057}
5058
5059static const struct phy_ops qcom_qmp_phy_gen_ops = {
5060 .init = qcom_qmp_phy_enable,
5061 .exit = qcom_qmp_phy_disable,
5062 .set_mode = qcom_qmp_phy_set_mode,
5063 .owner = THIS_MODULE,
5064};
5065
5066static const struct phy_ops qcom_qmp_phy_dp_ops = {
5067 .init = qcom_qmp_phy_init,
5068 .configure = qcom_qmp_dp_phy_configure,
5069 .power_on = qcom_qmp_phy_power_on,
5070 .calibrate = qcom_qmp_dp_phy_calibrate,
5071 .power_off = qcom_qmp_phy_power_off,
5072 .exit = qcom_qmp_phy_exit,
5073 .set_mode = qcom_qmp_phy_set_mode,
5074 .owner = THIS_MODULE,
5075};
5076
5077static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
5078 .power_on = qcom_qmp_phy_enable,
5079 .power_off = qcom_qmp_phy_disable,
5080 .set_mode = qcom_qmp_phy_set_mode,
5081 .owner = THIS_MODULE,
5082};
5083
5084static
5085int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
5086 void __iomem *serdes, const struct qmp_phy_cfg *cfg)
5087{
5088 struct qcom_qmp *qmp = dev_get_drvdata(dev);
5089 struct phy *generic_phy;
5090 struct qmp_phy *qphy;
5091 const struct phy_ops *ops;
5092 char prop_name[MAX_PROP_NAME];
5093 int ret;
5094
5095 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
5096 if (!qphy)
5097 return -ENOMEM;
5098
5099 qphy->cfg = cfg;
5100 qphy->serdes = serdes;
5101 /*
5102 * Get memory resources for each phy lane:
5103 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
5104 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
5105 * For single lane PHYs: pcs_misc (optional) -> 3.
5106 */
5107 qphy->tx = of_iomap(np, 0);
5108 if (!qphy->tx)
5109 return -ENOMEM;
5110
5111 qphy->rx = of_iomap(np, 1);
5112 if (!qphy->rx)
5113 return -ENOMEM;
5114
5115 qphy->pcs = of_iomap(np, 2);
5116 if (!qphy->pcs)
5117 return -ENOMEM;
5118
5119 /*
5120 * If this is a dual-lane PHY, then there should be registers for the
5121 * second lane. Some old device trees did not specify this, so fall
5122 * back to old legacy behavior of assuming they can be reached at an
5123 * offset from the first lane.
5124 */
5125 if (cfg->is_dual_lane_phy) {
5126 qphy->tx2 = of_iomap(np, 3);
5127 qphy->rx2 = of_iomap(np, 4);
5128 if (!qphy->tx2 || !qphy->rx2) {
5129 dev_warn(dev,
5130 "Underspecified device tree, falling back to legacy register regions\n");
5131
5132 /* In the old version, pcs_misc is at index 3. */
5133 qphy->pcs_misc = qphy->tx2;
5134 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
5135 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
5136
5137 } else {
5138 qphy->pcs_misc = of_iomap(np, 5);
5139 }
5140
5141 } else {
5142 qphy->pcs_misc = of_iomap(np, 3);
5143 }
5144
5145 if (!qphy->pcs_misc)
5146 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
5147
5148 /*
5149 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
5150 * based phys, so they essentially have pipe clock. So,
5151 * we return error in case phy is USB3 or PIPE type.
5152 * Otherwise, we initialize pipe clock to NULL for
5153 * all phys that don't need this.
5154 */
5155 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
5156 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
5157 if (IS_ERR(qphy->pipe_clk)) {
5158 if (cfg->type == PHY_TYPE_PCIE ||
5159 cfg->type == PHY_TYPE_USB3) {
5160 ret = PTR_ERR(qphy->pipe_clk);
5161 if (ret != -EPROBE_DEFER)
5162 dev_err(dev,
5163 "failed to get lane%d pipe_clk, %d\n",
5164 id, ret);
5165 return ret;
5166 }
5167 qphy->pipe_clk = NULL;
5168 }
5169
5170 /* Get lane reset, if any */
5171 if (cfg->has_lane_rst) {
5172 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
5173 qphy->lane_rst = of_reset_control_get(np, prop_name);
5174 if (IS_ERR(qphy->lane_rst)) {
5175 dev_err(dev, "failed to get lane%d reset\n", id);
5176 return PTR_ERR(qphy->lane_rst);
5177 }
5178 }
5179
5180 if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
5181 ops = &qcom_qmp_pcie_ufs_ops;
5182 else if (cfg->type == PHY_TYPE_DP)
5183 ops = &qcom_qmp_phy_dp_ops;
5184 else
5185 ops = &qcom_qmp_phy_gen_ops;
5186
5187 generic_phy = devm_phy_create(dev, np, ops);
5188 if (IS_ERR(generic_phy)) {
5189 ret = PTR_ERR(generic_phy);
5190 dev_err(dev, "failed to create qphy %d\n", ret);
5191 return ret;
5192 }
5193
5194 qphy->phy = generic_phy;
5195 qphy->index = id;
5196 qphy->qmp = qmp;
5197 qmp->phys[id] = qphy;
5198 phy_set_drvdata(generic_phy, qphy);
5199
5200 return 0;
5201}
5202
5203static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
5204 {
5205 .compatible = "qcom,ipq8074-qmp-usb3-phy",
5206 .data = &ipq8074_usb3phy_cfg,
5207 }, {
5208 .compatible = "qcom,msm8996-qmp-pcie-phy",
5209 .data = &msm8996_pciephy_cfg,
5210 }, {
5211 .compatible = "qcom,msm8996-qmp-ufs-phy",
5212 .data = &msm8996_ufs_cfg,
5213 }, {
5214 .compatible = "qcom,msm8996-qmp-usb3-phy",
5215 .data = &msm8996_usb3phy_cfg,
5216 }, {
5217 .compatible = "qcom,msm8998-qmp-pcie-phy",
5218 .data = &msm8998_pciephy_cfg,
5219 }, {
5220 .compatible = "qcom,msm8998-qmp-ufs-phy",
5221 .data = &sdm845_ufsphy_cfg,
5222 }, {
5223 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5224 .data = &ipq8074_pciephy_cfg,
5225 }, {
5226 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5227 .data = &ipq6018_pciephy_cfg,
5228 }, {
5229 .compatible = "qcom,sc7180-qmp-usb3-phy",
5230 .data = &sc7180_usb3phy_cfg,
5231 }, {
5232 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5233 /* It's a combo phy */
5234 }, {
5235 .compatible = "qcom,sc8180x-qmp-ufs-phy",
5236 .data = &sm8150_ufsphy_cfg,
5237 }, {
5238 .compatible = "qcom,sc8180x-qmp-usb3-phy",
5239 .data = &sm8150_usb3phy_cfg,
5240 }, {
5241 .compatible = "qcom,sdm845-qhp-pcie-phy",
5242 .data = &sdm845_qhp_pciephy_cfg,
5243 }, {
5244 .compatible = "qcom,sdm845-qmp-pcie-phy",
5245 .data = &sdm845_qmp_pciephy_cfg,
5246 }, {
5247 .compatible = "qcom,sdm845-qmp-usb3-phy",
5248 .data = &qmp_v3_usb3phy_cfg,
5249 }, {
5250 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
5251 .data = &qmp_v3_usb3_uniphy_cfg,
5252 }, {
5253 .compatible = "qcom,sdm845-qmp-ufs-phy",
5254 .data = &sdm845_ufsphy_cfg,
5255 }, {
5256 .compatible = "qcom,msm8998-qmp-usb3-phy",
5257 .data = &msm8998_usb3phy_cfg,
5258 }, {
5259 .compatible = "qcom,sm8150-qmp-ufs-phy",
5260 .data = &sm8150_ufsphy_cfg,
5261 }, {
5262 .compatible = "qcom,sm8250-qmp-ufs-phy",
5263 .data = &sm8150_ufsphy_cfg,
5264 }, {
5265 .compatible = "qcom,sm8150-qmp-usb3-phy",
5266 .data = &sm8150_usb3phy_cfg,
5267 }, {
5268 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
5269 .data = &sm8150_usb3_uniphy_cfg,
5270 }, {
5271 .compatible = "qcom,sm8250-qmp-usb3-phy",
5272 .data = &sm8250_usb3phy_cfg,
5273 }, {
5274 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5275 /* It's a combo phy */
5276 }, {
5277 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
5278 .data = &sm8250_usb3_uniphy_cfg,
5279 }, {
5280 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5281 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5282 }, {
5283 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5284 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5285 }, {
5286 .compatible = "qcom,sm8350-qmp-ufs-phy",
5287 .data = &sm8350_ufsphy_cfg,
5288 }, {
5289 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5290 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5291 }, {
5292 .compatible = "qcom,sdx55-qmp-pcie-phy",
5293 .data = &sdx55_qmp_pciephy_cfg,
5294 }, {
5295 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
5296 .data = &sdx55_usb3_uniphy_cfg,
5297 }, {
5298 .compatible = "qcom,sm8350-qmp-usb3-phy",
5299 .data = &sm8350_usb3phy_cfg,
5300 }, {
5301 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
5302 .data = &sm8350_usb3_uniphy_cfg,
5303 },
5304 { },
5305};
5306MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
5307
5308static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
5309 {
5310 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5311 .data = &sc7180_usb3dpphy_cfg,
5312 },
5313 {
5314 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5315 .data = &sm8250_usb3dpphy_cfg,
5316 },
5317 { }
5318};
5319
5320static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
5321 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
5322 qcom_qmp_phy_runtime_resume, NULL)
5323};
5324
5325static int qcom_qmp_phy_probe(struct platform_device *pdev)
5326{
5327 struct qcom_qmp *qmp;
5328 struct device *dev = &pdev->dev;
5329 struct device_node *child;
5330 struct phy_provider *phy_provider;
5331 void __iomem *serdes;
5332 void __iomem *usb_serdes;
5333 void __iomem *dp_serdes = NULL;
5334 const struct qmp_phy_combo_cfg *combo_cfg = NULL;
5335 const struct qmp_phy_cfg *cfg = NULL;
5336 const struct qmp_phy_cfg *usb_cfg = NULL;
5337 const struct qmp_phy_cfg *dp_cfg = NULL;
5338 int num, id, expected_phys;
5339 int ret;
5340
5341 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
5342 if (!qmp)
5343 return -ENOMEM;
5344
5345 qmp->dev = dev;
5346 dev_set_drvdata(dev, qmp);
5347
5348 /* Get the specific init parameters of QMP phy */
5349 cfg = of_device_get_match_data(dev);
5350 if (!cfg) {
5351 const struct of_device_id *match;
5352
5353 match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
5354 if (!match)
5355 return -EINVAL;
5356
5357 combo_cfg = match->data;
5358 if (!combo_cfg)
5359 return -EINVAL;
5360
5361 usb_cfg = combo_cfg->usb_cfg;
5362 cfg = usb_cfg; /* Setup clks and regulators */
5363 }
5364
5365 /* per PHY serdes; usually located at base address */
5366 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
5367 if (IS_ERR(serdes))
5368 return PTR_ERR(serdes);
5369
5370 /* per PHY dp_com; if PHY has dp_com control block */
5371 if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
5372 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
5373 if (IS_ERR(qmp->dp_com))
5374 return PTR_ERR(qmp->dp_com);
5375 }
5376
5377 if (combo_cfg) {
5378 /* Only two serdes for combo PHY */
5379 dp_serdes = devm_platform_ioremap_resource(pdev, 2);
5380 if (IS_ERR(dp_serdes))
5381 return PTR_ERR(dp_serdes);
5382
5383 dp_cfg = combo_cfg->dp_cfg;
5384 expected_phys = 2;
5385 } else {
5386 expected_phys = cfg->nlanes;
5387 }
5388
5389 mutex_init(&qmp->phy_mutex);
5390
5391 ret = qcom_qmp_phy_clk_init(dev, cfg);
5392 if (ret)
5393 return ret;
5394
5395 ret = qcom_qmp_phy_reset_init(dev, cfg);
5396 if (ret)
5397 return ret;
5398
5399 ret = qcom_qmp_phy_vreg_init(dev, cfg);
5400 if (ret) {
5401 if (ret != -EPROBE_DEFER)
5402 dev_err(dev, "failed to get regulator supplies: %d\n",
5403 ret);
5404 return ret;
5405 }
5406
5407 num = of_get_available_child_count(dev->of_node);
5408 /* do we have a rogue child node ? */
5409 if (num > expected_phys)
5410 return -EINVAL;
5411
5412 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
5413 if (!qmp->phys)
5414 return -ENOMEM;
5415
5416 pm_runtime_set_active(dev);
5417 pm_runtime_enable(dev);
5418 /*
5419 * Prevent runtime pm from being ON by default. Users can enable
5420 * it using power/control in sysfs.
5421 */
5422 pm_runtime_forbid(dev);
5423
5424 id = 0;
5425 for_each_available_child_of_node(dev->of_node, child) {
5426 if (of_node_name_eq(child, "dp-phy")) {
5427 cfg = dp_cfg;
5428 serdes = dp_serdes;
5429 } else if (of_node_name_eq(child, "usb3-phy")) {
5430 cfg = usb_cfg;
5431 serdes = usb_serdes;
5432 }
5433
5434 /* Create per-lane phy */
5435 ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
5436 if (ret) {
5437 dev_err(dev, "failed to create lane%d phy, %d\n",
5438 id, ret);
5439 goto err_node_put;
5440 }
5441
5442 /*
5443 * Register the pipe clock provided by phy.
5444 * See function description to see details of this pipe clock.
5445 */
5446 if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
5447 ret = phy_pipe_clk_register(qmp, child);
5448 if (ret) {
5449 dev_err(qmp->dev,
5450 "failed to register pipe clock source\n");
5451 goto err_node_put;
5452 }
5453 } else if (cfg->type == PHY_TYPE_DP) {
5454 ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
5455 if (ret) {
5456 dev_err(qmp->dev,
5457 "failed to register DP clock source\n");
5458 goto err_node_put;
5459 }
5460 }
5461 id++;
5462 }
5463
5464 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
5465 if (!IS_ERR(phy_provider))
5466 dev_info(dev, "Registered Qcom-QMP phy\n");
5467 else
5468 pm_runtime_disable(dev);
5469
5470 return PTR_ERR_OR_ZERO(phy_provider);
5471
5472err_node_put:
5473 pm_runtime_disable(dev);
5474 of_node_put(child);
5475 return ret;
5476}
5477
5478static struct platform_driver qcom_qmp_phy_driver = {
5479 .probe = qcom_qmp_phy_probe,
5480 .driver = {
5481 .name = "qcom-qmp-phy",
5482 .pm = &qcom_qmp_phy_pm_ops,
5483 .of_match_table = qcom_qmp_phy_of_match_table,
5484 },
5485};
5486
5487module_platform_driver(qcom_qmp_phy_driver);
5488
5489MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
5490MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
5491MODULE_LICENSE("GPL v2");