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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#ifndef __AMDGPU_SMU_H__
23#define __AMDGPU_SMU_H__
24
25#include "amdgpu.h"
26#include "kgd_pp_interface.h"
27#include "dm_pp_interface.h"
28#include "dm_pp_smu.h"
29#include "smu_types.h"
30
31#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
32#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
33#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
34#define SMU_FW_NAME_LEN 0x24
35
36#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
37
38// Power Throttlers
39#define SMU_THROTTLER_PPT0_BIT 0
40#define SMU_THROTTLER_PPT1_BIT 1
41#define SMU_THROTTLER_PPT2_BIT 2
42#define SMU_THROTTLER_PPT3_BIT 3
43#define SMU_THROTTLER_SPL_BIT 4
44#define SMU_THROTTLER_FPPT_BIT 5
45#define SMU_THROTTLER_SPPT_BIT 6
46#define SMU_THROTTLER_SPPT_APU_BIT 7
47
48// Current Throttlers
49#define SMU_THROTTLER_TDC_GFX_BIT 16
50#define SMU_THROTTLER_TDC_SOC_BIT 17
51#define SMU_THROTTLER_TDC_MEM_BIT 18
52#define SMU_THROTTLER_TDC_VDD_BIT 19
53#define SMU_THROTTLER_TDC_CVIP_BIT 20
54#define SMU_THROTTLER_EDC_CPU_BIT 21
55#define SMU_THROTTLER_EDC_GFX_BIT 22
56#define SMU_THROTTLER_APCC_BIT 23
57
58// Temperature
59#define SMU_THROTTLER_TEMP_GPU_BIT 32
60#define SMU_THROTTLER_TEMP_CORE_BIT 33
61#define SMU_THROTTLER_TEMP_MEM_BIT 34
62#define SMU_THROTTLER_TEMP_EDGE_BIT 35
63#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
64#define SMU_THROTTLER_TEMP_SOC_BIT 37
65#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38
66#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39
67#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40
68#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41
69#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42
70#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43
71#define SMU_THROTTLER_VRHOT0_BIT 44
72#define SMU_THROTTLER_VRHOT1_BIT 45
73#define SMU_THROTTLER_PROCHOT_CPU_BIT 46
74#define SMU_THROTTLER_PROCHOT_GFX_BIT 47
75
76// Other
77#define SMU_THROTTLER_PPM_BIT 56
78#define SMU_THROTTLER_FIT_BIT 57
79
80struct smu_hw_power_state {
81 unsigned int magic;
82};
83
84struct smu_power_state;
85
86enum smu_state_ui_label {
87 SMU_STATE_UI_LABEL_NONE,
88 SMU_STATE_UI_LABEL_BATTERY,
89 SMU_STATE_UI_TABEL_MIDDLE_LOW,
90 SMU_STATE_UI_LABEL_BALLANCED,
91 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
92 SMU_STATE_UI_LABEL_PERFORMANCE,
93 SMU_STATE_UI_LABEL_BACO,
94};
95
96enum smu_state_classification_flag {
97 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
98 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
99 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
100 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
101 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
102 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
103 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
104 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
105 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
106 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
107 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
108 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
109 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
110 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
111 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
112 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
113 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
114 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
115 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
116 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
117 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
118};
119
120struct smu_state_classification_block {
121 enum smu_state_ui_label ui_label;
122 enum smu_state_classification_flag flags;
123 int bios_index;
124 bool temporary_state;
125 bool to_be_deleted;
126};
127
128struct smu_state_pcie_block {
129 unsigned int lanes;
130};
131
132enum smu_refreshrate_source {
133 SMU_REFRESHRATE_SOURCE_EDID,
134 SMU_REFRESHRATE_SOURCE_EXPLICIT
135};
136
137struct smu_state_display_block {
138 bool disable_frame_modulation;
139 bool limit_refreshrate;
140 enum smu_refreshrate_source refreshrate_source;
141 int explicit_refreshrate;
142 int edid_refreshrate_index;
143 bool enable_vari_bright;
144};
145
146struct smu_state_memory_block {
147 bool dll_off;
148 uint8_t m3arb;
149 uint8_t unused[3];
150};
151
152struct smu_state_software_algorithm_block {
153 bool disable_load_balancing;
154 bool enable_sleep_for_timestamps;
155};
156
157struct smu_temperature_range {
158 int min;
159 int max;
160 int edge_emergency_max;
161 int hotspot_min;
162 int hotspot_crit_max;
163 int hotspot_emergency_max;
164 int mem_min;
165 int mem_crit_max;
166 int mem_emergency_max;
167 int software_shutdown_temp;
168};
169
170struct smu_state_validation_block {
171 bool single_display_only;
172 bool disallow_on_dc;
173 uint8_t supported_power_levels;
174};
175
176struct smu_uvd_clocks {
177 uint32_t vclk;
178 uint32_t dclk;
179};
180
181/**
182* Structure to hold a SMU Power State.
183*/
184struct smu_power_state {
185 uint32_t id;
186 struct list_head ordered_list;
187 struct list_head all_states_list;
188
189 struct smu_state_classification_block classification;
190 struct smu_state_validation_block validation;
191 struct smu_state_pcie_block pcie;
192 struct smu_state_display_block display;
193 struct smu_state_memory_block memory;
194 struct smu_state_software_algorithm_block software;
195 struct smu_uvd_clocks uvd_clocks;
196 struct smu_hw_power_state hardware;
197};
198
199enum smu_power_src_type
200{
201 SMU_POWER_SOURCE_AC,
202 SMU_POWER_SOURCE_DC,
203 SMU_POWER_SOURCE_COUNT,
204};
205
206enum smu_ppt_limit_type
207{
208 SMU_DEFAULT_PPT_LIMIT = 0,
209 SMU_FAST_PPT_LIMIT,
210};
211
212enum smu_ppt_limit_level
213{
214 SMU_PPT_LIMIT_MIN = -1,
215 SMU_PPT_LIMIT_CURRENT,
216 SMU_PPT_LIMIT_DEFAULT,
217 SMU_PPT_LIMIT_MAX,
218};
219
220enum smu_memory_pool_size
221{
222 SMU_MEMORY_POOL_SIZE_ZERO = 0,
223 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
224 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
225 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
226 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
227};
228
229struct smu_user_dpm_profile {
230 uint32_t fan_mode;
231 uint32_t power_limit;
232 uint32_t fan_speed_percent;
233 uint32_t flags;
234
235 /* user clock state information */
236 uint32_t clk_mask[SMU_CLK_COUNT];
237 uint32_t clk_dependency;
238};
239
240enum smu_event_type {
241
242 SMU_EVENT_RESET_COMPLETE = 0,
243};
244
245#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
246 do { \
247 tables[table_id].size = s; \
248 tables[table_id].align = a; \
249 tables[table_id].domain = d; \
250 } while (0)
251
252struct smu_table {
253 uint64_t size;
254 uint32_t align;
255 uint8_t domain;
256 uint64_t mc_address;
257 void *cpu_addr;
258 struct amdgpu_bo *bo;
259};
260
261enum smu_perf_level_designation {
262 PERF_LEVEL_ACTIVITY,
263 PERF_LEVEL_POWER_CONTAINMENT,
264};
265
266struct smu_performance_level {
267 uint32_t core_clock;
268 uint32_t memory_clock;
269 uint32_t vddc;
270 uint32_t vddci;
271 uint32_t non_local_mem_freq;
272 uint32_t non_local_mem_width;
273};
274
275struct smu_clock_info {
276 uint32_t min_mem_clk;
277 uint32_t max_mem_clk;
278 uint32_t min_eng_clk;
279 uint32_t max_eng_clk;
280 uint32_t min_bus_bandwidth;
281 uint32_t max_bus_bandwidth;
282};
283
284struct smu_bios_boot_up_values
285{
286 uint32_t revision;
287 uint32_t gfxclk;
288 uint32_t uclk;
289 uint32_t socclk;
290 uint32_t dcefclk;
291 uint32_t eclk;
292 uint32_t vclk;
293 uint32_t dclk;
294 uint16_t vddc;
295 uint16_t vddci;
296 uint16_t mvddc;
297 uint16_t vdd_gfx;
298 uint8_t cooling_id;
299 uint32_t pp_table_id;
300 uint32_t format_revision;
301 uint32_t content_revision;
302 uint32_t fclk;
303 uint32_t lclk;
304 uint32_t firmware_caps;
305};
306
307enum smu_table_id
308{
309 SMU_TABLE_PPTABLE = 0,
310 SMU_TABLE_WATERMARKS,
311 SMU_TABLE_CUSTOM_DPM,
312 SMU_TABLE_DPMCLOCKS,
313 SMU_TABLE_AVFS,
314 SMU_TABLE_AVFS_PSM_DEBUG,
315 SMU_TABLE_AVFS_FUSE_OVERRIDE,
316 SMU_TABLE_PMSTATUSLOG,
317 SMU_TABLE_SMU_METRICS,
318 SMU_TABLE_DRIVER_SMU_CONFIG,
319 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
320 SMU_TABLE_OVERDRIVE,
321 SMU_TABLE_I2C_COMMANDS,
322 SMU_TABLE_PACE,
323 SMU_TABLE_COUNT,
324};
325
326struct smu_table_context
327{
328 void *power_play_table;
329 uint32_t power_play_table_size;
330 void *hardcode_pptable;
331 unsigned long metrics_time;
332 void *metrics_table;
333 void *clocks_table;
334 void *watermarks_table;
335
336 void *max_sustainable_clocks;
337 struct smu_bios_boot_up_values boot_values;
338 void *driver_pptable;
339 struct smu_table tables[SMU_TABLE_COUNT];
340 /*
341 * The driver table is just a staging buffer for
342 * uploading/downloading content from the SMU.
343 *
344 * And the table_id for SMU_MSG_TransferTableSmu2Dram/
345 * SMU_MSG_TransferTableDram2Smu instructs SMU
346 * which content driver is interested.
347 */
348 struct smu_table driver_table;
349 struct smu_table memory_pool;
350 struct smu_table dummy_read_1_table;
351 uint8_t thermal_controller_type;
352
353 void *overdrive_table;
354 void *boot_overdrive_table;
355
356 uint32_t gpu_metrics_table_size;
357 void *gpu_metrics_table;
358};
359
360struct smu_dpm_context {
361 uint32_t dpm_context_size;
362 void *dpm_context;
363 void *golden_dpm_context;
364 bool enable_umd_pstate;
365 enum amd_dpm_forced_level dpm_level;
366 enum amd_dpm_forced_level saved_dpm_level;
367 enum amd_dpm_forced_level requested_dpm_level;
368 struct smu_power_state *dpm_request_power_state;
369 struct smu_power_state *dpm_current_power_state;
370 struct mclock_latency_table *mclk_latency_table;
371};
372
373struct smu_power_gate {
374 bool uvd_gated;
375 bool vce_gated;
376 atomic_t vcn_gated;
377 atomic_t jpeg_gated;
378 struct mutex vcn_gate_lock;
379 struct mutex jpeg_gate_lock;
380};
381
382struct smu_power_context {
383 void *power_context;
384 uint32_t power_context_size;
385 struct smu_power_gate power_gate;
386};
387
388#define SMU_FEATURE_MAX (64)
389struct smu_feature
390{
391 uint32_t feature_num;
392 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
393 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
394 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
395 struct mutex mutex;
396};
397
398struct smu_clocks {
399 uint32_t engine_clock;
400 uint32_t memory_clock;
401 uint32_t bus_bandwidth;
402 uint32_t engine_clock_in_sr;
403 uint32_t dcef_clock;
404 uint32_t dcef_clock_in_sr;
405};
406
407#define MAX_REGULAR_DPM_NUM 16
408struct mclk_latency_entries {
409 uint32_t frequency;
410 uint32_t latency;
411};
412struct mclock_latency_table {
413 uint32_t count;
414 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
415};
416
417enum smu_reset_mode
418{
419 SMU_RESET_MODE_0,
420 SMU_RESET_MODE_1,
421 SMU_RESET_MODE_2,
422};
423
424enum smu_baco_state
425{
426 SMU_BACO_STATE_ENTER = 0,
427 SMU_BACO_STATE_EXIT,
428};
429
430struct smu_baco_context
431{
432 struct mutex mutex;
433 uint32_t state;
434 bool platform_support;
435};
436
437struct smu_freq_info {
438 uint32_t min;
439 uint32_t max;
440 uint32_t freq_level;
441};
442
443struct pstates_clk_freq {
444 uint32_t min;
445 uint32_t standard;
446 uint32_t peak;
447 struct smu_freq_info custom;
448 struct smu_freq_info curr;
449};
450
451struct smu_umd_pstate_table {
452 struct pstates_clk_freq gfxclk_pstate;
453 struct pstates_clk_freq socclk_pstate;
454 struct pstates_clk_freq uclk_pstate;
455 struct pstates_clk_freq vclk_pstate;
456 struct pstates_clk_freq dclk_pstate;
457};
458
459struct cmn2asic_msg_mapping {
460 int valid_mapping;
461 int map_to;
462 int valid_in_vf;
463};
464
465struct cmn2asic_mapping {
466 int valid_mapping;
467 int map_to;
468};
469
470#define WORKLOAD_POLICY_MAX 7
471struct smu_context
472{
473 struct amdgpu_device *adev;
474 struct amdgpu_irq_src irq_source;
475
476 const struct pptable_funcs *ppt_funcs;
477 const struct cmn2asic_msg_mapping *message_map;
478 const struct cmn2asic_mapping *clock_map;
479 const struct cmn2asic_mapping *feature_map;
480 const struct cmn2asic_mapping *table_map;
481 const struct cmn2asic_mapping *pwr_src_map;
482 const struct cmn2asic_mapping *workload_map;
483 struct mutex mutex;
484 struct mutex sensor_lock;
485 struct mutex metrics_lock;
486 struct mutex message_lock;
487 uint64_t pool_size;
488
489 struct smu_table_context smu_table;
490 struct smu_dpm_context smu_dpm;
491 struct smu_power_context smu_power;
492 struct smu_feature smu_feature;
493 struct amd_pp_display_configuration *display_config;
494 struct smu_baco_context smu_baco;
495 struct smu_temperature_range thermal_range;
496 void *od_settings;
497
498 struct smu_umd_pstate_table pstate_table;
499 uint32_t pstate_sclk;
500 uint32_t pstate_mclk;
501
502 bool od_enabled;
503 uint32_t current_power_limit;
504 uint32_t default_power_limit;
505 uint32_t max_power_limit;
506
507 /* soft pptable */
508 uint32_t ppt_offset_bytes;
509 uint32_t ppt_size_bytes;
510 uint8_t *ppt_start_addr;
511
512 bool support_power_containment;
513 bool disable_watermark;
514
515#define WATERMARKS_EXIST (1 << 0)
516#define WATERMARKS_LOADED (1 << 1)
517 uint32_t watermarks_bitmap;
518 uint32_t hard_min_uclk_req_from_dal;
519 bool disable_uclk_switch;
520
521 uint32_t workload_mask;
522 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
523 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
524 uint32_t power_profile_mode;
525 uint32_t default_power_profile_mode;
526 bool pm_enabled;
527 bool is_apu;
528
529 uint32_t smc_driver_if_version;
530 uint32_t smc_fw_if_version;
531 uint32_t smc_fw_version;
532
533 bool uploading_custom_pp_table;
534 bool dc_controlled_by_gpio;
535
536 struct work_struct throttling_logging_work;
537 atomic64_t throttle_int_counter;
538 struct work_struct interrupt_work;
539
540 unsigned fan_max_rpm;
541 unsigned manual_fan_speed_percent;
542
543 uint32_t gfx_default_hard_min_freq;
544 uint32_t gfx_default_soft_max_freq;
545 uint32_t gfx_actual_hard_min_freq;
546 uint32_t gfx_actual_soft_max_freq;
547
548 /* APU only */
549 uint32_t cpu_default_soft_min_freq;
550 uint32_t cpu_default_soft_max_freq;
551 uint32_t cpu_actual_soft_min_freq;
552 uint32_t cpu_actual_soft_max_freq;
553 uint32_t cpu_core_id_select;
554 uint16_t cpu_core_num;
555
556 struct smu_user_dpm_profile user_dpm_profile;
557};
558
559struct i2c_adapter;
560
561/**
562 * struct pptable_funcs - Callbacks used to interact with the SMU.
563 */
564struct pptable_funcs {
565 /**
566 * @run_btc: Calibrate voltage/frequency curve to fit the system's
567 * power delivery and voltage margins. Required for adaptive
568 * voltage frequency scaling (AVFS).
569 */
570 int (*run_btc)(struct smu_context *smu);
571
572 /**
573 * @get_allowed_feature_mask: Get allowed feature mask.
574 * &feature_mask: Array to store feature mask.
575 * &num: Elements in &feature_mask.
576 */
577 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
578
579 /**
580 * @get_current_power_state: Get the current power state.
581 *
582 * Return: Current power state on success, negative errno on failure.
583 */
584 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
585
586 /**
587 * @set_default_dpm_table: Retrieve the default overdrive settings from
588 * the SMU.
589 */
590 int (*set_default_dpm_table)(struct smu_context *smu);
591
592 int (*set_power_state)(struct smu_context *smu);
593
594 /**
595 * @populate_umd_state_clk: Populate the UMD power state table with
596 * defaults.
597 */
598 int (*populate_umd_state_clk)(struct smu_context *smu);
599
600 /**
601 * @print_clk_levels: Print DPM clock levels for a clock domain
602 * to buffer. Star current level.
603 *
604 * Used for sysfs interfaces.
605 */
606 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
607
608 /**
609 * @force_clk_levels: Set a range of allowed DPM levels for a clock
610 * domain.
611 * &clk_type: Clock domain.
612 * &mask: Range of allowed DPM levels.
613 */
614 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
615
616 /**
617 * @od_edit_dpm_table: Edit the custom overdrive DPM table.
618 * &type: Type of edit.
619 * &input: Edit parameters.
620 * &size: Size of &input.
621 */
622 int (*od_edit_dpm_table)(struct smu_context *smu,
623 enum PP_OD_DPM_TABLE_COMMAND type,
624 long *input, uint32_t size);
625
626 /**
627 * @get_clock_by_type_with_latency: Get the speed and latency of a clock
628 * domain.
629 */
630 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
631 enum smu_clk_type clk_type,
632 struct
633 pp_clock_levels_with_latency
634 *clocks);
635 /**
636 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
637 * domain.
638 */
639 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
640 enum amd_pp_clock_type type,
641 struct
642 pp_clock_levels_with_voltage
643 *clocks);
644
645 /**
646 * @get_power_profile_mode: Print all power profile modes to
647 * buffer. Star current mode.
648 */
649 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
650
651 /**
652 * @set_power_profile_mode: Set a power profile mode. Also used to
653 * create/set custom power profile modes.
654 * &input: Power profile mode parameters.
655 * &size: Size of &input.
656 */
657 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
658
659 /**
660 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
661 * management.
662 */
663 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
664
665 /**
666 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
667 * management.
668 */
669 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
670
671 /**
672 * @read_sensor: Read data from a sensor.
673 * &sensor: Sensor to read data from.
674 * &data: Sensor reading.
675 * &size: Size of &data.
676 */
677 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
678 void *data, uint32_t *size);
679
680 /**
681 * @pre_display_config_changed: Prepare GPU for a display configuration
682 * change.
683 *
684 * Disable display tracking and pin memory clock speed to maximum. Used
685 * in display component synchronization.
686 */
687 int (*pre_display_config_changed)(struct smu_context *smu);
688
689 /**
690 * @display_config_changed: Notify the SMU of the current display
691 * configuration.
692 *
693 * Allows SMU to properly track blanking periods for memory clock
694 * adjustment. Used in display component synchronization.
695 */
696 int (*display_config_changed)(struct smu_context *smu);
697
698 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
699
700 /**
701 * @notify_smc_display_config: Applies display requirements to the
702 * current power state.
703 *
704 * Optimize deep sleep DCEFclk and mclk for the current display
705 * configuration. Used in display component synchronization.
706 */
707 int (*notify_smc_display_config)(struct smu_context *smu);
708
709 /**
710 * @is_dpm_running: Check if DPM is running.
711 *
712 * Return: True if DPM is running, false otherwise.
713 */
714 bool (*is_dpm_running)(struct smu_context *smu);
715
716 /**
717 * @get_fan_speed_percent: Get the current fan speed in percent.
718 */
719 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
720
721 /**
722 * @set_watermarks_table: Configure and upload the watermarks tables to
723 * the SMU.
724 */
725 int (*set_watermarks_table)(struct smu_context *smu,
726 struct pp_smu_wm_range_sets *clock_ranges);
727
728 /**
729 * @get_thermal_temperature_range: Get safe thermal limits in Celcius.
730 */
731 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
732
733 /**
734 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
735 * &clocks_in_khz: Array of DPM levels.
736 * &num_states: Elements in &clocks_in_khz.
737 */
738 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
739
740 /**
741 * @set_default_od_settings: Set the overdrive tables to defaults.
742 */
743 int (*set_default_od_settings)(struct smu_context *smu);
744
745 /**
746 * @set_performance_level: Set a performance level.
747 */
748 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
749
750 /**
751 * @display_disable_memory_clock_switch: Enable/disable dynamic memory
752 * clock switching.
753 *
754 * Disabling this feature forces memory clock speed to maximum.
755 * Enabling sets the minimum memory clock capable of driving the
756 * current display configuration.
757 */
758 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
759
760 /**
761 * @dump_pptable: Print the power play table to the system log.
762 */
763 void (*dump_pptable)(struct smu_context *smu);
764
765 /**
766 * @get_power_limit: Get the device's power limits.
767 */
768 int (*get_power_limit)(struct smu_context *smu,
769 uint32_t *current_power_limit,
770 uint32_t *default_power_limit,
771 uint32_t *max_power_limit);
772
773 /**
774 * @get_ppt_limit: Get the device's ppt limits.
775 */
776 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
777 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
778
779 /**
780 * @set_df_cstate: Set data fabric cstate.
781 */
782 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
783
784 /**
785 * @allow_xgmi_power_down: Enable/disable external global memory
786 * interconnect power down.
787 */
788 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
789
790 /**
791 * @update_pcie_parameters: Update and upload the system's PCIe
792 * capabilites to the SMU.
793 * &pcie_gen_cap: Maximum allowed PCIe generation.
794 * &pcie_width_cap: Maximum allowed PCIe width.
795 */
796 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
797
798 /**
799 * @i2c_init: Initialize i2c.
800 *
801 * The i2c bus is used internally by the SMU voltage regulators and
802 * other devices. The i2c's EEPROM also stores bad page tables on boards
803 * with ECC.
804 */
805 int (*i2c_init)(struct smu_context *smu, struct i2c_adapter *control);
806
807 /**
808 * @i2c_fini: Tear down i2c.
809 */
810 void (*i2c_fini)(struct smu_context *smu, struct i2c_adapter *control);
811
812 /**
813 * @get_unique_id: Get the GPU's unique id. Used for asset tracking.
814 */
815 void (*get_unique_id)(struct smu_context *smu);
816
817 /**
818 * @get_dpm_clock_table: Get a copy of the DPM clock table.
819 *
820 * Used by display component in bandwidth and watermark calculations.
821 */
822 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
823
824 /**
825 * @init_microcode: Request the SMU's firmware from the kernel.
826 */
827 int (*init_microcode)(struct smu_context *smu);
828
829 /**
830 * @load_microcode: Load firmware onto the SMU.
831 */
832 int (*load_microcode)(struct smu_context *smu);
833
834 /**
835 * @fini_microcode: Release the SMU's firmware.
836 */
837 void (*fini_microcode)(struct smu_context *smu);
838
839 /**
840 * @init_smc_tables: Initialize the SMU tables.
841 */
842 int (*init_smc_tables)(struct smu_context *smu);
843
844 /**
845 * @fini_smc_tables: Release the SMU tables.
846 */
847 int (*fini_smc_tables)(struct smu_context *smu);
848
849 /**
850 * @init_power: Initialize the power gate table context.
851 */
852 int (*init_power)(struct smu_context *smu);
853
854 /**
855 * @fini_power: Release the power gate table context.
856 */
857 int (*fini_power)(struct smu_context *smu);
858
859 /**
860 * @check_fw_status: Check the SMU's firmware status.
861 *
862 * Return: Zero if check passes, negative errno on failure.
863 */
864 int (*check_fw_status)(struct smu_context *smu);
865
866 /**
867 * @set_mp1_state: put SMU into a correct state for comming
868 * resume from runpm or gpu reset.
869 */
870 int (*set_mp1_state)(struct smu_context *smu,
871 enum pp_mp1_state mp1_state);
872
873 /**
874 * @setup_pptable: Initialize the power play table and populate it with
875 * default values.
876 */
877 int (*setup_pptable)(struct smu_context *smu);
878
879 /**
880 * @get_vbios_bootup_values: Get default boot values from the VBIOS.
881 */
882 int (*get_vbios_bootup_values)(struct smu_context *smu);
883
884 /**
885 * @check_fw_version: Print driver and SMU interface versions to the
886 * system log.
887 *
888 * Interface mismatch is not a critical failure.
889 */
890 int (*check_fw_version)(struct smu_context *smu);
891
892 /**
893 * @powergate_sdma: Power up/down system direct memory access.
894 */
895 int (*powergate_sdma)(struct smu_context *smu, bool gate);
896
897 /**
898 * @set_gfx_cgpg: Enable/disable graphics engine course grain power
899 * gating.
900 */
901 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
902
903 /**
904 * @write_pptable: Write the power play table to the SMU.
905 */
906 int (*write_pptable)(struct smu_context *smu);
907
908 /**
909 * @set_driver_table_location: Send the location of the driver table to
910 * the SMU.
911 */
912 int (*set_driver_table_location)(struct smu_context *smu);
913
914 /**
915 * @set_tool_table_location: Send the location of the tool table to the
916 * SMU.
917 */
918 int (*set_tool_table_location)(struct smu_context *smu);
919
920 /**
921 * @notify_memory_pool_location: Send the location of the memory pool to
922 * the SMU.
923 */
924 int (*notify_memory_pool_location)(struct smu_context *smu);
925
926 /**
927 * @system_features_control: Enable/disable all SMU features.
928 */
929 int (*system_features_control)(struct smu_context *smu, bool en);
930
931 /**
932 * @send_smc_msg_with_param: Send a message with a parameter to the SMU.
933 * &msg: Type of message.
934 * ¶m: Message parameter.
935 * &read_arg: SMU response (optional).
936 */
937 int (*send_smc_msg_with_param)(struct smu_context *smu,
938 enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
939
940 /**
941 * @send_smc_msg: Send a message to the SMU.
942 * &msg: Type of message.
943 * &read_arg: SMU response (optional).
944 */
945 int (*send_smc_msg)(struct smu_context *smu,
946 enum smu_message_type msg,
947 uint32_t *read_arg);
948
949 /**
950 * @init_display_count: Notify the SMU of the number of display
951 * components in current display configuration.
952 */
953 int (*init_display_count)(struct smu_context *smu, uint32_t count);
954
955 /**
956 * @set_allowed_mask: Notify the SMU of the features currently allowed
957 * by the driver.
958 */
959 int (*set_allowed_mask)(struct smu_context *smu);
960
961 /**
962 * @get_enabled_mask: Get a mask of features that are currently enabled
963 * on the SMU.
964 * &feature_mask: Array representing enabled feature mask.
965 * &num: Elements in &feature_mask.
966 */
967 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
968
969 /**
970 * @feature_is_enabled: Test if a feature is enabled.
971 *
972 * Return: One if enabled, zero if disabled.
973 */
974 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
975
976 /**
977 * @disable_all_features_with_exception: Disable all features with
978 * exception to those in &mask.
979 */
980 int (*disable_all_features_with_exception)(struct smu_context *smu,
981 bool no_hw_disablement,
982 enum smu_feature_mask mask);
983
984 /**
985 * @notify_display_change: Enable fast memory clock switching.
986 *
987 * Allows for fine grained memory clock switching but has more stringent
988 * timing requirements.
989 */
990 int (*notify_display_change)(struct smu_context *smu);
991
992 /**
993 * @set_power_limit: Set power limit in watts.
994 */
995 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
996
997 /**
998 * @init_max_sustainable_clocks: Populate max sustainable clock speed
999 * table with values from the SMU.
1000 */
1001 int (*init_max_sustainable_clocks)(struct smu_context *smu);
1002
1003 /**
1004 * @enable_thermal_alert: Enable thermal alert interrupts.
1005 */
1006 int (*enable_thermal_alert)(struct smu_context *smu);
1007
1008 /**
1009 * @disable_thermal_alert: Disable thermal alert interrupts.
1010 */
1011 int (*disable_thermal_alert)(struct smu_context *smu);
1012
1013 /**
1014 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
1015 * clock speed in MHz.
1016 */
1017 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
1018
1019 /**
1020 * @display_clock_voltage_request: Set a hard minimum frequency
1021 * for a clock domain.
1022 */
1023 int (*display_clock_voltage_request)(struct smu_context *smu, struct
1024 pp_display_clock_request
1025 *clock_req);
1026
1027 /**
1028 * @get_fan_control_mode: Get the current fan control mode.
1029 */
1030 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
1031
1032 /**
1033 * @set_fan_control_mode: Set the fan control mode.
1034 */
1035 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
1036
1037 /**
1038 * @set_fan_speed_percent: Set a static fan speed in percent.
1039 */
1040 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
1041
1042 /**
1043 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
1044 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
1045 */
1046 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
1047
1048 /**
1049 * @gfx_off_control: Enable/disable graphics engine poweroff.
1050 */
1051 int (*gfx_off_control)(struct smu_context *smu, bool enable);
1052
1053
1054 /**
1055 * @get_gfx_off_status: Get graphics engine poweroff status.
1056 *
1057 * Return:
1058 * 0 - GFXOFF(default).
1059 * 1 - Transition out of GFX State.
1060 * 2 - Not in GFXOFF.
1061 * 3 - Transition into GFXOFF.
1062 */
1063 uint32_t (*get_gfx_off_status)(struct smu_context *smu);
1064
1065 /**
1066 * @register_irq_handler: Register interupt request handlers.
1067 */
1068 int (*register_irq_handler)(struct smu_context *smu);
1069
1070 /**
1071 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
1072 */
1073 int (*set_azalia_d3_pme)(struct smu_context *smu);
1074
1075 /**
1076 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
1077 * clock speeds table.
1078 *
1079 * Provides a way for the display component (DC) to get the max
1080 * sustainable clocks from the SMU.
1081 */
1082 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
1083
1084 /**
1085 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off).
1086 */
1087 bool (*baco_is_support)(struct smu_context *smu);
1088
1089 /**
1090 * @baco_get_state: Get the current BACO state.
1091 *
1092 * Return: Current BACO state.
1093 */
1094 enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
1095
1096 /**
1097 * @baco_set_state: Enter/exit BACO.
1098 */
1099 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
1100
1101 /**
1102 * @baco_enter: Enter BACO.
1103 */
1104 int (*baco_enter)(struct smu_context *smu);
1105
1106 /**
1107 * @baco_exit: Exit Baco.
1108 */
1109 int (*baco_exit)(struct smu_context *smu);
1110
1111 /**
1112 * @mode1_reset_is_support: Check if GPU supports mode1 reset.
1113 */
1114 bool (*mode1_reset_is_support)(struct smu_context *smu);
1115 /**
1116 * @mode2_reset_is_support: Check if GPU supports mode2 reset.
1117 */
1118 bool (*mode2_reset_is_support)(struct smu_context *smu);
1119
1120 /**
1121 * @mode1_reset: Perform mode1 reset.
1122 *
1123 * Complete GPU reset.
1124 */
1125 int (*mode1_reset)(struct smu_context *smu);
1126
1127 /**
1128 * @mode2_reset: Perform mode2 reset.
1129 *
1130 * Mode2 reset generally does not reset as many IPs as mode1 reset. The
1131 * IPs reset varies by asic.
1132 */
1133 int (*mode2_reset)(struct smu_context *smu);
1134
1135 /**
1136 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock
1137 * domain in MHz.
1138 */
1139 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
1140
1141 /**
1142 * @set_soft_freq_limited_range: Set the soft frequency range of a clock
1143 * domain in MHz.
1144 */
1145 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
1146
1147 /**
1148 * @set_power_source: Notify the SMU of the current power source.
1149 */
1150 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
1151
1152 /**
1153 * @log_thermal_throttling_event: Print a thermal throttling warning to
1154 * the system's log.
1155 */
1156 void (*log_thermal_throttling_event)(struct smu_context *smu);
1157
1158 /**
1159 * @get_pp_feature_mask: Print a human readable table of enabled
1160 * features to buffer.
1161 */
1162 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
1163
1164 /**
1165 * @set_pp_feature_mask: Request the SMU enable/disable features to
1166 * match those enabled in &new_mask.
1167 */
1168 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
1169
1170 /**
1171 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
1172 *
1173 * Return: Size of &table
1174 */
1175 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
1176
1177 /**
1178 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
1179 */
1180 int (*enable_mgpu_fan_boost)(struct smu_context *smu);
1181
1182 /**
1183 * @gfx_ulv_control: Enable/disable ultra low voltage.
1184 */
1185 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
1186
1187 /**
1188 * @deep_sleep_control: Enable/disable deep sleep.
1189 */
1190 int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
1191
1192 /**
1193 * @get_fan_parameters: Get fan parameters.
1194 *
1195 * Get maximum fan speed from the power play table.
1196 */
1197 int (*get_fan_parameters)(struct smu_context *smu);
1198
1199 /**
1200 * @post_init: Helper function for asic specific workarounds.
1201 */
1202 int (*post_init)(struct smu_context *smu);
1203
1204 /**
1205 * @interrupt_work: Work task scheduled from SMU interrupt handler.
1206 */
1207 void (*interrupt_work)(struct smu_context *smu);
1208
1209 /**
1210 * @gpo_control: Enable/disable graphics power optimization if supported.
1211 */
1212 int (*gpo_control)(struct smu_context *smu, bool enablement);
1213
1214 /**
1215 * @gfx_state_change_set: Send the current graphics state to the SMU.
1216 */
1217 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
1218
1219 /**
1220 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
1221 * parameters to defaults.
1222 */
1223 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
1224
1225 /**
1226 * @set_light_sbr: Set light sbr mode for the SMU.
1227 */
1228 int (*set_light_sbr)(struct smu_context *smu, bool enable);
1229
1230 /**
1231 * @wait_for_event: Wait for events from SMU.
1232 */
1233 int (*wait_for_event)(struct smu_context *smu,
1234 enum smu_event_type event, uint64_t event_arg);
1235
1236 /**
1237 * @sned_hbm_bad_pages_num: message SMU to update bad page number
1238 * of SMUBUS table.
1239 */
1240 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
1241};
1242
1243typedef enum {
1244 METRICS_CURR_GFXCLK,
1245 METRICS_CURR_SOCCLK,
1246 METRICS_CURR_UCLK,
1247 METRICS_CURR_VCLK,
1248 METRICS_CURR_VCLK1,
1249 METRICS_CURR_DCLK,
1250 METRICS_CURR_DCLK1,
1251 METRICS_CURR_FCLK,
1252 METRICS_CURR_DCEFCLK,
1253 METRICS_AVERAGE_CPUCLK,
1254 METRICS_AVERAGE_GFXCLK,
1255 METRICS_AVERAGE_SOCCLK,
1256 METRICS_AVERAGE_FCLK,
1257 METRICS_AVERAGE_UCLK,
1258 METRICS_AVERAGE_VCLK,
1259 METRICS_AVERAGE_DCLK,
1260 METRICS_AVERAGE_GFXACTIVITY,
1261 METRICS_AVERAGE_MEMACTIVITY,
1262 METRICS_AVERAGE_VCNACTIVITY,
1263 METRICS_AVERAGE_SOCKETPOWER,
1264 METRICS_TEMPERATURE_EDGE,
1265 METRICS_TEMPERATURE_HOTSPOT,
1266 METRICS_TEMPERATURE_MEM,
1267 METRICS_TEMPERATURE_VRGFX,
1268 METRICS_TEMPERATURE_VRSOC,
1269 METRICS_TEMPERATURE_VRMEM,
1270 METRICS_THROTTLER_STATUS,
1271 METRICS_CURR_FANSPEED,
1272 METRICS_VOLTAGE_VDDSOC,
1273 METRICS_VOLTAGE_VDDGFX,
1274 METRICS_SS_APU_SHARE,
1275 METRICS_SS_DGPU_SHARE,
1276} MetricsMember_t;
1277
1278enum smu_cmn2asic_mapping_type {
1279 CMN2ASIC_MAPPING_MSG,
1280 CMN2ASIC_MAPPING_CLK,
1281 CMN2ASIC_MAPPING_FEATURE,
1282 CMN2ASIC_MAPPING_TABLE,
1283 CMN2ASIC_MAPPING_PWR,
1284 CMN2ASIC_MAPPING_WORKLOAD,
1285};
1286
1287#define MSG_MAP(msg, index, valid_in_vf) \
1288 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
1289
1290#define CLK_MAP(clk, index) \
1291 [SMU_##clk] = {1, (index)}
1292
1293#define FEA_MAP(fea) \
1294 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
1295
1296#define FEA_MAP_REVERSE(fea) \
1297 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1298
1299#define FEA_MAP_HALF_REVERSE(fea) \
1300 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1301
1302#define TAB_MAP(tab) \
1303 [SMU_TABLE_##tab] = {1, TABLE_##tab}
1304
1305#define TAB_MAP_VALID(tab) \
1306 [SMU_TABLE_##tab] = {1, TABLE_##tab}
1307
1308#define TAB_MAP_INVALID(tab) \
1309 [SMU_TABLE_##tab] = {0, TABLE_##tab}
1310
1311#define PWR_MAP(tab) \
1312 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
1313
1314#define WORKLOAD_MAP(profile, workload) \
1315 [profile] = {1, (workload)}
1316
1317#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
1318int smu_get_power_limit(void *handle,
1319 uint32_t *limit,
1320 enum pp_power_limit_level pp_limit_level,
1321 enum pp_power_type pp_power_type);
1322
1323bool smu_mode1_reset_is_support(struct smu_context *smu);
1324bool smu_mode2_reset_is_support(struct smu_context *smu);
1325int smu_mode1_reset(struct smu_context *smu);
1326
1327extern const struct amd_ip_funcs smu_ip_funcs;
1328
1329extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
1330extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
1331extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
1332
1333bool is_support_sw_smu(struct amdgpu_device *adev);
1334bool is_support_cclk_dpm(struct amdgpu_device *adev);
1335int smu_write_watermarks_table(struct smu_context *smu);
1336
1337int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1338 uint32_t *min, uint32_t *max);
1339
1340int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1341 uint32_t min, uint32_t max);
1342
1343int smu_set_ac_dc(struct smu_context *smu);
1344
1345int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
1346
1347int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
1348
1349int smu_set_light_sbr(struct smu_context *smu, bool enable);
1350
1351int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
1352 uint64_t event_arg);
1353
1354#endif
1355#endif