tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2//
3// rt1015.c -- RT1015 ALSA SoC audio amplifier driver
4//
5// Copyright 2019 Realtek Semiconductor Corp.
6//
7// Author: Jack Yu <jack.yu@realtek.com>
8//
9//
10
11#include <linux/acpi.h>
12#include <linux/delay.h>
13#include <linux/firmware.h>
14#include <linux/fs.h>
15#include <linux/gpio.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/platform_device.h>
21#include <linux/pm.h>
22#include <linux/regmap.h>
23#include <sound/core.h>
24#include <sound/initval.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/rt1015.h>
28#include <sound/soc-dapm.h>
29#include <sound/soc.h>
30#include <sound/tlv.h>
31
32#include "rl6231.h"
33#include "rt1015.h"
34
35static const struct rt1015_platform_data i2s_default_platform_data = {
36 .power_up_delay_ms = 50,
37};
38
39static const struct reg_default rt1015_reg[] = {
40 { 0x0000, 0x0000 },
41 { 0x0004, 0xa000 },
42 { 0x0006, 0x0003 },
43 { 0x000a, 0x081e },
44 { 0x000c, 0x0006 },
45 { 0x000e, 0x0000 },
46 { 0x0010, 0x0000 },
47 { 0x0012, 0x0000 },
48 { 0x0014, 0x0000 },
49 { 0x0016, 0x0000 },
50 { 0x0018, 0x0000 },
51 { 0x0020, 0x8000 },
52 { 0x0022, 0x8043 },
53 { 0x0076, 0x0000 },
54 { 0x0078, 0x0000 },
55 { 0x007a, 0x0002 },
56 { 0x007c, 0x10ec },
57 { 0x007d, 0x1015 },
58 { 0x00f0, 0x5000 },
59 { 0x00f2, 0x004c },
60 { 0x00f3, 0xecfe },
61 { 0x00f4, 0x0000 },
62 { 0x00f6, 0x0400 },
63 { 0x0100, 0x0028 },
64 { 0x0102, 0xff02 },
65 { 0x0104, 0xa213 },
66 { 0x0106, 0x200c },
67 { 0x010c, 0x0000 },
68 { 0x010e, 0x0058 },
69 { 0x0111, 0x0200 },
70 { 0x0112, 0x0400 },
71 { 0x0114, 0x0022 },
72 { 0x0116, 0x0000 },
73 { 0x0118, 0x0000 },
74 { 0x011a, 0x0123 },
75 { 0x011c, 0x4567 },
76 { 0x0300, 0x203d },
77 { 0x0302, 0x001e },
78 { 0x0311, 0x0000 },
79 { 0x0313, 0x6014 },
80 { 0x0314, 0x00a2 },
81 { 0x031a, 0x00a0 },
82 { 0x031c, 0x001f },
83 { 0x031d, 0xffff },
84 { 0x031e, 0x0000 },
85 { 0x031f, 0x0000 },
86 { 0x0320, 0x0000 },
87 { 0x0321, 0x0000 },
88 { 0x0322, 0xd7df },
89 { 0x0328, 0x10b2 },
90 { 0x0329, 0x0175 },
91 { 0x032a, 0x36ad },
92 { 0x032b, 0x7e55 },
93 { 0x032c, 0x0520 },
94 { 0x032d, 0xaa00 },
95 { 0x032e, 0x570e },
96 { 0x0330, 0xe180 },
97 { 0x0332, 0x0034 },
98 { 0x0334, 0x0001 },
99 { 0x0336, 0x0010 },
100 { 0x0338, 0x0000 },
101 { 0x04fa, 0x0030 },
102 { 0x04fc, 0x35c8 },
103 { 0x04fe, 0x0800 },
104 { 0x0500, 0x0400 },
105 { 0x0502, 0x1000 },
106 { 0x0504, 0x0000 },
107 { 0x0506, 0x04ff },
108 { 0x0508, 0x0010 },
109 { 0x050a, 0x001a },
110 { 0x0519, 0x1c68 },
111 { 0x051a, 0x0ccc },
112 { 0x051b, 0x0666 },
113 { 0x051d, 0x0000 },
114 { 0x051f, 0x0000 },
115 { 0x0536, 0x061c },
116 { 0x0538, 0x0000 },
117 { 0x053a, 0x0000 },
118 { 0x053c, 0x0000 },
119 { 0x053d, 0x0000 },
120 { 0x053e, 0x0000 },
121 { 0x053f, 0x0000 },
122 { 0x0540, 0x0000 },
123 { 0x0541, 0x0000 },
124 { 0x0542, 0x0000 },
125 { 0x0543, 0x0000 },
126 { 0x0544, 0x0000 },
127 { 0x0568, 0x0000 },
128 { 0x056a, 0x0000 },
129 { 0x1000, 0x0040 },
130 { 0x1002, 0x5405 },
131 { 0x1006, 0x5515 },
132 { 0x1007, 0x05f7 },
133 { 0x1009, 0x0b0a },
134 { 0x100a, 0x00ef },
135 { 0x100d, 0x0003 },
136 { 0x1010, 0xa433 },
137 { 0x1020, 0x0000 },
138 { 0x1200, 0x5a01 },
139 { 0x1202, 0x6524 },
140 { 0x1204, 0x1f00 },
141 { 0x1206, 0x0000 },
142 { 0x1208, 0x0000 },
143 { 0x120a, 0x0000 },
144 { 0x120c, 0x0000 },
145 { 0x120e, 0x0000 },
146 { 0x1210, 0x0000 },
147 { 0x1212, 0x0000 },
148 { 0x1300, 0x10a1 },
149 { 0x1302, 0x12ff },
150 { 0x1304, 0x0400 },
151 { 0x1305, 0x0844 },
152 { 0x1306, 0x4611 },
153 { 0x1308, 0x555e },
154 { 0x130a, 0x0000 },
155 { 0x130c, 0x2000 },
156 { 0x130e, 0x0100 },
157 { 0x130f, 0x0001 },
158 { 0x1310, 0x0000 },
159 { 0x1312, 0x0000 },
160 { 0x1314, 0x0000 },
161 { 0x1316, 0x0000 },
162 { 0x1318, 0x0000 },
163 { 0x131a, 0x0000 },
164 { 0x1322, 0x0029 },
165 { 0x1323, 0x4a52 },
166 { 0x1324, 0x002c },
167 { 0x1325, 0x0b02 },
168 { 0x1326, 0x002d },
169 { 0x1327, 0x6b5a },
170 { 0x1328, 0x002e },
171 { 0x1329, 0xcbb2 },
172 { 0x132a, 0x0030 },
173 { 0x132b, 0x2c0b },
174 { 0x1330, 0x0031 },
175 { 0x1331, 0x8c63 },
176 { 0x1332, 0x0032 },
177 { 0x1333, 0xecbb },
178 { 0x1334, 0x0034 },
179 { 0x1335, 0x4d13 },
180 { 0x1336, 0x0037 },
181 { 0x1337, 0x0dc3 },
182 { 0x1338, 0x003d },
183 { 0x1339, 0xef7b },
184 { 0x133a, 0x0044 },
185 { 0x133b, 0xd134 },
186 { 0x133c, 0x0047 },
187 { 0x133d, 0x91e4 },
188 { 0x133e, 0x004d },
189 { 0x133f, 0xc370 },
190 { 0x1340, 0x0053 },
191 { 0x1341, 0xf4fd },
192 { 0x1342, 0x0060 },
193 { 0x1343, 0x5816 },
194 { 0x1344, 0x006c },
195 { 0x1345, 0xbb2e },
196 { 0x1346, 0x0072 },
197 { 0x1347, 0xecbb },
198 { 0x1348, 0x0076 },
199 { 0x1349, 0x5d97 },
200};
201
202static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
203{
204 switch (reg) {
205 case RT1015_RESET:
206 case RT1015_CLK_DET:
207 case RT1015_SIL_DET:
208 case RT1015_VER_ID:
209 case RT1015_VENDOR_ID:
210 case RT1015_DEVICE_ID:
211 case RT1015_PRO_ALT:
212 case RT1015_MAN_I2C:
213 case RT1015_DAC3:
214 case RT1015_VBAT_TEST_OUT1:
215 case RT1015_VBAT_TEST_OUT2:
216 case RT1015_VBAT_PROT_ATT:
217 case RT1015_VBAT_DET_CODE:
218 case RT1015_SMART_BST_CTRL1:
219 case RT1015_SPK_DC_DETECT1:
220 case RT1015_SPK_DC_DETECT4:
221 case RT1015_SPK_DC_DETECT5:
222 case RT1015_DC_CALIB_CLSD1:
223 case RT1015_DC_CALIB_CLSD5:
224 case RT1015_DC_CALIB_CLSD6:
225 case RT1015_DC_CALIB_CLSD7:
226 case RT1015_DC_CALIB_CLSD8:
227 case RT1015_S_BST_TIMING_INTER1:
228 case RT1015_OSCK_STA:
229 case RT1015_MONO_DYNA_CTRL1:
230 case RT1015_MONO_DYNA_CTRL5:
231 return true;
232
233 default:
234 return false;
235 }
236}
237
238static bool rt1015_readable_register(struct device *dev, unsigned int reg)
239{
240 switch (reg) {
241 case RT1015_RESET:
242 case RT1015_CLK2:
243 case RT1015_CLK3:
244 case RT1015_PLL1:
245 case RT1015_PLL2:
246 case RT1015_DUM_RW1:
247 case RT1015_DUM_RW2:
248 case RT1015_DUM_RW3:
249 case RT1015_DUM_RW4:
250 case RT1015_DUM_RW5:
251 case RT1015_DUM_RW6:
252 case RT1015_CLK_DET:
253 case RT1015_SIL_DET:
254 case RT1015_CUSTOMER_ID:
255 case RT1015_PCODE_FWVER:
256 case RT1015_VER_ID:
257 case RT1015_VENDOR_ID:
258 case RT1015_DEVICE_ID:
259 case RT1015_PAD_DRV1:
260 case RT1015_PAD_DRV2:
261 case RT1015_GAT_BOOST:
262 case RT1015_PRO_ALT:
263 case RT1015_OSCK_STA:
264 case RT1015_MAN_I2C:
265 case RT1015_DAC1:
266 case RT1015_DAC2:
267 case RT1015_DAC3:
268 case RT1015_ADC1:
269 case RT1015_ADC2:
270 case RT1015_TDM_MASTER:
271 case RT1015_TDM_TCON:
272 case RT1015_TDM1_1:
273 case RT1015_TDM1_2:
274 case RT1015_TDM1_3:
275 case RT1015_TDM1_4:
276 case RT1015_TDM1_5:
277 case RT1015_MIXER1:
278 case RT1015_MIXER2:
279 case RT1015_ANA_PROTECT1:
280 case RT1015_ANA_CTRL_SEQ1:
281 case RT1015_ANA_CTRL_SEQ2:
282 case RT1015_VBAT_DET_DEB:
283 case RT1015_VBAT_VOLT_DET1:
284 case RT1015_VBAT_VOLT_DET2:
285 case RT1015_VBAT_TEST_OUT1:
286 case RT1015_VBAT_TEST_OUT2:
287 case RT1015_VBAT_PROT_ATT:
288 case RT1015_VBAT_DET_CODE:
289 case RT1015_PWR1:
290 case RT1015_PWR4:
291 case RT1015_PWR5:
292 case RT1015_PWR6:
293 case RT1015_PWR7:
294 case RT1015_PWR8:
295 case RT1015_PWR9:
296 case RT1015_CLASSD_SEQ:
297 case RT1015_SMART_BST_CTRL1:
298 case RT1015_SMART_BST_CTRL2:
299 case RT1015_ANA_CTRL1:
300 case RT1015_ANA_CTRL2:
301 case RT1015_PWR_STATE_CTRL:
302 case RT1015_MONO_DYNA_CTRL:
303 case RT1015_MONO_DYNA_CTRL1:
304 case RT1015_MONO_DYNA_CTRL2:
305 case RT1015_MONO_DYNA_CTRL3:
306 case RT1015_MONO_DYNA_CTRL4:
307 case RT1015_MONO_DYNA_CTRL5:
308 case RT1015_SPK_VOL:
309 case RT1015_SHORT_DETTOP1:
310 case RT1015_SHORT_DETTOP2:
311 case RT1015_SPK_DC_DETECT1:
312 case RT1015_SPK_DC_DETECT2:
313 case RT1015_SPK_DC_DETECT3:
314 case RT1015_SPK_DC_DETECT4:
315 case RT1015_SPK_DC_DETECT5:
316 case RT1015_BAT_RPO_STEP1:
317 case RT1015_BAT_RPO_STEP2:
318 case RT1015_BAT_RPO_STEP3:
319 case RT1015_BAT_RPO_STEP4:
320 case RT1015_BAT_RPO_STEP5:
321 case RT1015_BAT_RPO_STEP6:
322 case RT1015_BAT_RPO_STEP7:
323 case RT1015_BAT_RPO_STEP8:
324 case RT1015_BAT_RPO_STEP9:
325 case RT1015_BAT_RPO_STEP10:
326 case RT1015_BAT_RPO_STEP11:
327 case RT1015_BAT_RPO_STEP12:
328 case RT1015_SPREAD_SPEC1:
329 case RT1015_SPREAD_SPEC2:
330 case RT1015_PAD_STATUS:
331 case RT1015_PADS_PULLING_CTRL1:
332 case RT1015_PADS_DRIVING:
333 case RT1015_SYS_RST1:
334 case RT1015_SYS_RST2:
335 case RT1015_SYS_GATING1:
336 case RT1015_TEST_MODE1:
337 case RT1015_TEST_MODE2:
338 case RT1015_TIMING_CTRL1:
339 case RT1015_PLL_INT:
340 case RT1015_TEST_OUT1:
341 case RT1015_DC_CALIB_CLSD1:
342 case RT1015_DC_CALIB_CLSD2:
343 case RT1015_DC_CALIB_CLSD3:
344 case RT1015_DC_CALIB_CLSD4:
345 case RT1015_DC_CALIB_CLSD5:
346 case RT1015_DC_CALIB_CLSD6:
347 case RT1015_DC_CALIB_CLSD7:
348 case RT1015_DC_CALIB_CLSD8:
349 case RT1015_DC_CALIB_CLSD9:
350 case RT1015_DC_CALIB_CLSD10:
351 case RT1015_CLSD_INTERNAL1:
352 case RT1015_CLSD_INTERNAL2:
353 case RT1015_CLSD_INTERNAL3:
354 case RT1015_CLSD_INTERNAL4:
355 case RT1015_CLSD_INTERNAL5:
356 case RT1015_CLSD_INTERNAL6:
357 case RT1015_CLSD_INTERNAL7:
358 case RT1015_CLSD_INTERNAL8:
359 case RT1015_CLSD_INTERNAL9:
360 case RT1015_CLSD_OCP_CTRL:
361 case RT1015_VREF_LV:
362 case RT1015_MBIAS1:
363 case RT1015_MBIAS2:
364 case RT1015_MBIAS3:
365 case RT1015_MBIAS4:
366 case RT1015_VREF_LV1:
367 case RT1015_S_BST_TIMING_INTER1:
368 case RT1015_S_BST_TIMING_INTER2:
369 case RT1015_S_BST_TIMING_INTER3:
370 case RT1015_S_BST_TIMING_INTER4:
371 case RT1015_S_BST_TIMING_INTER5:
372 case RT1015_S_BST_TIMING_INTER6:
373 case RT1015_S_BST_TIMING_INTER7:
374 case RT1015_S_BST_TIMING_INTER8:
375 case RT1015_S_BST_TIMING_INTER9:
376 case RT1015_S_BST_TIMING_INTER10:
377 case RT1015_S_BST_TIMING_INTER11:
378 case RT1015_S_BST_TIMING_INTER12:
379 case RT1015_S_BST_TIMING_INTER13:
380 case RT1015_S_BST_TIMING_INTER14:
381 case RT1015_S_BST_TIMING_INTER15:
382 case RT1015_S_BST_TIMING_INTER16:
383 case RT1015_S_BST_TIMING_INTER17:
384 case RT1015_S_BST_TIMING_INTER18:
385 case RT1015_S_BST_TIMING_INTER19:
386 case RT1015_S_BST_TIMING_INTER20:
387 case RT1015_S_BST_TIMING_INTER21:
388 case RT1015_S_BST_TIMING_INTER22:
389 case RT1015_S_BST_TIMING_INTER23:
390 case RT1015_S_BST_TIMING_INTER24:
391 case RT1015_S_BST_TIMING_INTER25:
392 case RT1015_S_BST_TIMING_INTER26:
393 case RT1015_S_BST_TIMING_INTER27:
394 case RT1015_S_BST_TIMING_INTER28:
395 case RT1015_S_BST_TIMING_INTER29:
396 case RT1015_S_BST_TIMING_INTER30:
397 case RT1015_S_BST_TIMING_INTER31:
398 case RT1015_S_BST_TIMING_INTER32:
399 case RT1015_S_BST_TIMING_INTER33:
400 case RT1015_S_BST_TIMING_INTER34:
401 case RT1015_S_BST_TIMING_INTER35:
402 case RT1015_S_BST_TIMING_INTER36:
403 return true;
404
405 default:
406 return false;
407 }
408}
409
410static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
411
412static const char * const rt1015_din_source_select[] = {
413 "Left",
414 "Right",
415 "Left + Right average",
416};
417
418static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
419 rt1015_din_source_select);
420
421static const char * const rt1015_boost_mode[] = {
422 "Bypass", "Adaptive", "Fixed Adaptive"
423};
424
425static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
426 rt1015_boost_mode);
427
428static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
429 struct snd_ctl_elem_value *ucontrol)
430{
431 struct snd_soc_component *component =
432 snd_soc_kcontrol_component(kcontrol);
433 struct rt1015_priv *rt1015 =
434 snd_soc_component_get_drvdata(component);
435
436 ucontrol->value.integer.value[0] = rt1015->boost_mode;
437
438 return 0;
439}
440
441static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
442 struct snd_ctl_elem_value *ucontrol)
443{
444 struct snd_soc_component *component =
445 snd_soc_kcontrol_component(kcontrol);
446 struct rt1015_priv *rt1015 =
447 snd_soc_component_get_drvdata(component);
448 int boost_mode = ucontrol->value.integer.value[0];
449
450 switch (boost_mode) {
451 case BYPASS:
452 snd_soc_component_update_bits(component,
453 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
454 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
455 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
456 RT1015_BYPASS_SWRREG_BYPASS);
457 break;
458 case ADAPTIVE:
459 snd_soc_component_update_bits(component,
460 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
461 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
462 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
463 RT1015_BYPASS_SWRREG_PASS);
464 break;
465 case FIXED_ADAPTIVE:
466 snd_soc_component_update_bits(component,
467 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
468 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
469 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
470 RT1015_BYPASS_SWRREG_PASS);
471 break;
472 default:
473 dev_err(component->dev, "Unknown boost control.\n");
474 return -EINVAL;
475 }
476
477 rt1015->boost_mode = boost_mode;
478
479 return 0;
480}
481
482static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
483 struct snd_ctl_elem_value *ucontrol)
484{
485 struct snd_soc_component *component =
486 snd_soc_kcontrol_component(kcontrol);
487 struct rt1015_priv *rt1015 =
488 snd_soc_component_get_drvdata(component);
489
490 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
491
492 return 0;
493}
494
495static void rt1015_calibrate(struct rt1015_priv *rt1015)
496{
497 struct snd_soc_component *component = rt1015->component;
498 struct regmap *regmap = rt1015->regmap;
499
500 snd_soc_dapm_mutex_lock(&component->dapm);
501 regcache_cache_bypass(regmap, true);
502
503 regmap_write(regmap, RT1015_CLK_DET, 0x0000);
504 regmap_write(regmap, RT1015_PWR4, 0x00B2);
505 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0009);
506 msleep(100);
507 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000A);
508 msleep(100);
509 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000C);
510 msleep(100);
511 regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2028);
512 regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
513 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000D);
514 msleep(300);
515 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0008);
516 regmap_write(regmap, RT1015_SYS_RST1, 0x05F5);
517 regmap_write(regmap, RT1015_CLK_DET, 0x8000);
518
519 regcache_cache_bypass(regmap, false);
520 regcache_mark_dirty(regmap);
521 regcache_sync(regmap);
522 snd_soc_dapm_mutex_unlock(&component->dapm);
523}
524
525static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
526 struct snd_ctl_elem_value *ucontrol)
527{
528 struct snd_soc_component *component =
529 snd_soc_kcontrol_component(kcontrol);
530 struct rt1015_priv *rt1015 =
531 snd_soc_component_get_drvdata(component);
532
533 if (rt1015->dac_is_used) {
534 dev_err(component->dev, "DAC is being used!\n");
535 return -EBUSY;
536 }
537
538 rt1015->bypass_boost = ucontrol->value.integer.value[0];
539 if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
540 !rt1015->cali_done) {
541 rt1015_calibrate(rt1015);
542 rt1015->cali_done = 1;
543
544 regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
545 }
546
547 return 0;
548}
549
550static void rt1015_flush_work(struct work_struct *work)
551{
552 struct rt1015_priv *rt1015 = container_of(work, struct rt1015_priv,
553 flush_work.work);
554 struct snd_soc_component *component = rt1015->component;
555 unsigned int val, i;
556
557 for (i = 0; i < 200; ++i) {
558 usleep_range(1000, 1500);
559 dev_dbg(component->dev, "Flush DAC (retry:%u)\n", i);
560 regmap_read(rt1015->regmap, RT1015_CLK_DET, &val);
561 if (val & 0x800)
562 break;
563 }
564
565 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597);
566 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7);
567 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028);
568
569 if (val & 0x800)
570 dev_dbg(component->dev, "Flush DAC completed.\n");
571 else
572 dev_warn(component->dev, "Fail to flush DAC data.\n");
573}
574
575static const struct snd_kcontrol_new rt1015_snd_controls[] = {
576 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
577 127, 0, dac_vol_tlv),
578 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
579 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
580 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
581 rt1015_boost_mode_get, rt1015_boost_mode_put),
582 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
583 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
584 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
585};
586
587static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
588 struct snd_soc_dapm_widget *sink)
589{
590 struct snd_soc_component *component =
591 snd_soc_dapm_to_component(source->dapm);
592 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
593
594 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
595 return 1;
596 else
597 return 0;
598}
599
600static int r1015_dac_event(struct snd_soc_dapm_widget *w,
601 struct snd_kcontrol *kcontrol, int event)
602{
603 struct snd_soc_component *component =
604 snd_soc_dapm_to_component(w->dapm);
605 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
606
607 switch (event) {
608 case SND_SOC_DAPM_PRE_PMU:
609 rt1015->dac_is_used = 1;
610 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
611 snd_soc_component_write(component,
612 RT1015_SYS_RST1, 0x05f7);
613 snd_soc_component_write(component,
614 RT1015_SYS_RST2, 0x0b0a);
615 snd_soc_component_write(component,
616 RT1015_GAT_BOOST, 0xacfe);
617 snd_soc_component_write(component,
618 RT1015_PWR9, 0xaa00);
619 snd_soc_component_write(component,
620 RT1015_GAT_BOOST, 0xecfe);
621 } else {
622 snd_soc_component_write(component,
623 0x032d, 0xaa60);
624 snd_soc_component_write(component,
625 RT1015_SYS_RST1, 0x05f7);
626 snd_soc_component_write(component,
627 RT1015_SYS_RST2, 0x0b0a);
628 snd_soc_component_write(component,
629 RT1015_PWR_STATE_CTRL, 0x008e);
630 }
631 break;
632
633 case SND_SOC_DAPM_POST_PMU:
634 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8);
635 break;
636
637 case SND_SOC_DAPM_POST_PMD:
638 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
639 snd_soc_component_write(component,
640 RT1015_PWR9, 0xa800);
641 snd_soc_component_write(component,
642 RT1015_SYS_RST1, 0x05f5);
643 snd_soc_component_write(component,
644 RT1015_SYS_RST2, 0x0b9a);
645 } else {
646 snd_soc_component_write(component,
647 0x032d, 0xaa60);
648 snd_soc_component_write(component,
649 RT1015_PWR_STATE_CTRL, 0x0088);
650 snd_soc_component_write(component,
651 RT1015_SYS_RST1, 0x05f5);
652 snd_soc_component_write(component,
653 RT1015_SYS_RST2, 0x0b9a);
654 }
655 rt1015->dac_is_used = 0;
656
657 cancel_delayed_work_sync(&rt1015->flush_work);
658 break;
659
660 default:
661 break;
662 }
663 return 0;
664}
665
666static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
667 struct snd_kcontrol *kcontrol, int event)
668{
669 struct snd_soc_component *component =
670 snd_soc_dapm_to_component(w->dapm);
671 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
672 unsigned int ret, ret2;
673
674 switch (event) {
675 case SND_SOC_DAPM_PRE_PMU:
676 ret = snd_soc_component_read(component, RT1015_CLK_DET);
677 ret2 = snd_soc_component_read(component, RT1015_SPK_DC_DETECT1);
678 if (!((ret >> 15) & 0x1)) {
679 snd_soc_component_update_bits(component, RT1015_CLK_DET,
680 RT1015_EN_BCLK_DET_MASK, RT1015_EN_BCLK_DET);
681 dev_dbg(component->dev, "BCLK Detection Enabled.\n");
682 }
683 if (!((ret2 >> 12) & 0x1)) {
684 snd_soc_component_update_bits(component, RT1015_SPK_DC_DETECT1,
685 RT1015_EN_CLA_D_DC_DET_MASK, RT1015_EN_CLA_D_DC_DET);
686 dev_dbg(component->dev, "Class-D DC Detection Enabled.\n");
687 }
688 break;
689 case SND_SOC_DAPM_POST_PMU:
690 if (rt1015->hw_config == RT1015_HW_28)
691 schedule_delayed_work(&rt1015->flush_work, msecs_to_jiffies(10));
692 msleep(rt1015->pdata.power_up_delay_ms);
693 break;
694 default:
695 break;
696 }
697 return 0;
698}
699
700static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
701 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
702 NULL, 0),
703 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
704 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
705 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
706 SND_SOC_DAPM_POST_PMD),
707 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
708 rt1015_amp_drv_event, SND_SOC_DAPM_PRE_PMU |
709 SND_SOC_DAPM_POST_PMU),
710 SND_SOC_DAPM_OUTPUT("SPO"),
711};
712
713static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
714 { "DAC", NULL, "AIFRX" },
715 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
716 { "Amp Drv", NULL, "DAC" },
717 { "SPO", NULL, "Amp Drv" },
718};
719
720static int rt1015_hw_params(struct snd_pcm_substream *substream,
721 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
722{
723 struct snd_soc_component *component = dai->component;
724 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
725 int pre_div, bclk_ms, frame_size, lrck;
726 unsigned int val_len = 0;
727
728 lrck = params_rate(params);
729 pre_div = rl6231_get_clk_info(rt1015->sysclk, lrck);
730 if (pre_div < 0) {
731 dev_err(component->dev, "Unsupported clock rate\n");
732 return -EINVAL;
733 }
734
735 frame_size = snd_soc_params_to_frame_size(params);
736 if (frame_size < 0) {
737 dev_err(component->dev, "Unsupported frame size: %d\n",
738 frame_size);
739 return -EINVAL;
740 }
741
742 bclk_ms = frame_size > 32;
743
744 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
745 bclk_ms, pre_div, dai->id);
746
747 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
748 lrck, pre_div, dai->id);
749
750 switch (params_width(params)) {
751 case 16:
752 break;
753 case 20:
754 val_len = RT1015_I2S_DL_20;
755 break;
756 case 24:
757 val_len = RT1015_I2S_DL_24;
758 break;
759 case 8:
760 val_len = RT1015_I2S_DL_8;
761 break;
762 default:
763 return -EINVAL;
764 }
765
766 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
767 RT1015_I2S_DL_MASK, val_len);
768 snd_soc_component_update_bits(component, RT1015_CLK2,
769 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
770
771 return 0;
772}
773
774static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
775{
776 struct snd_soc_component *component = dai->component;
777 unsigned int reg_val = 0, reg_val2 = 0;
778
779 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
780 case SND_SOC_DAIFMT_CBM_CFM:
781 reg_val |= RT1015_TCON_TDM_MS_M;
782 break;
783 case SND_SOC_DAIFMT_CBS_CFS:
784 reg_val |= RT1015_TCON_TDM_MS_S;
785 break;
786 default:
787 return -EINVAL;
788 }
789
790 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
791 case SND_SOC_DAIFMT_NB_NF:
792 break;
793 case SND_SOC_DAIFMT_IB_NF:
794 reg_val2 |= RT1015_TDM_INV_BCLK;
795 break;
796 default:
797 return -EINVAL;
798 }
799
800 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
801 case SND_SOC_DAIFMT_I2S:
802 break;
803
804 case SND_SOC_DAIFMT_LEFT_J:
805 reg_val |= RT1015_I2S_M_DF_LEFT;
806 break;
807
808 case SND_SOC_DAIFMT_DSP_A:
809 reg_val |= RT1015_I2S_M_DF_PCM_A;
810 break;
811
812 case SND_SOC_DAIFMT_DSP_B:
813 reg_val |= RT1015_I2S_M_DF_PCM_B;
814 break;
815
816 default:
817 return -EINVAL;
818 }
819
820 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
821 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
822 reg_val);
823 snd_soc_component_update_bits(component, RT1015_TDM1_1,
824 RT1015_TDM_INV_BCLK_MASK, reg_val2);
825
826 return 0;
827}
828
829static int rt1015_set_component_sysclk(struct snd_soc_component *component,
830 int clk_id, int source, unsigned int freq, int dir)
831{
832 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
833 unsigned int reg_val = 0;
834
835 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
836 return 0;
837
838 switch (clk_id) {
839 case RT1015_SCLK_S_MCLK:
840 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
841 break;
842
843 case RT1015_SCLK_S_PLL:
844 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
845 break;
846
847 default:
848 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
849 return -EINVAL;
850 }
851
852 rt1015->sysclk = freq;
853 rt1015->sysclk_src = clk_id;
854
855 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
856 freq, clk_id);
857
858 snd_soc_component_update_bits(component, RT1015_CLK2,
859 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
860
861 return 0;
862}
863
864static int rt1015_set_component_pll(struct snd_soc_component *component,
865 int pll_id, int source, unsigned int freq_in,
866 unsigned int freq_out)
867{
868 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
869 struct rl6231_pll_code pll_code;
870 int ret;
871
872 if (!freq_in || !freq_out) {
873 dev_dbg(component->dev, "PLL disabled\n");
874
875 rt1015->pll_in = 0;
876 rt1015->pll_out = 0;
877
878 return 0;
879 }
880
881 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
882 freq_out == rt1015->pll_out)
883 return 0;
884
885 switch (source) {
886 case RT1015_PLL_S_MCLK:
887 snd_soc_component_update_bits(component, RT1015_CLK2,
888 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
889 break;
890
891 case RT1015_PLL_S_BCLK:
892 snd_soc_component_update_bits(component, RT1015_CLK2,
893 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
894 break;
895
896 default:
897 dev_err(component->dev, "Unknown PLL Source %d\n", source);
898 return -EINVAL;
899 }
900
901 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
902 if (ret < 0) {
903 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
904 return ret;
905 }
906
907 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
908 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
909 pll_code.n_code, pll_code.k_code);
910
911 snd_soc_component_write(component, RT1015_PLL1,
912 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT) |
913 (pll_code.m_bp << RT1015_PLL_M_BP_SFT) |
914 pll_code.n_code);
915 snd_soc_component_write(component, RT1015_PLL2,
916 pll_code.k_code);
917
918 rt1015->pll_in = freq_in;
919 rt1015->pll_out = freq_out;
920 rt1015->pll_src = source;
921
922 return 0;
923}
924
925static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
926 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
927{
928 struct snd_soc_component *component = dai->component;
929 unsigned int val = 0, rx_slotnum, tx_slotnum;
930 int ret = 0, first_bit;
931
932 switch (slots) {
933 case 2:
934 val |= RT1015_I2S_TX_2CH;
935 break;
936 case 4:
937 val |= RT1015_I2S_TX_4CH;
938 break;
939 case 6:
940 val |= RT1015_I2S_TX_6CH;
941 break;
942 case 8:
943 val |= RT1015_I2S_TX_8CH;
944 break;
945 default:
946 ret = -EINVAL;
947 goto _set_tdm_err_;
948 }
949
950 switch (slot_width) {
951 case 16:
952 val |= RT1015_I2S_CH_TX_LEN_16B;
953 break;
954 case 20:
955 val |= RT1015_I2S_CH_TX_LEN_20B;
956 break;
957 case 24:
958 val |= RT1015_I2S_CH_TX_LEN_24B;
959 break;
960 case 32:
961 val |= RT1015_I2S_CH_TX_LEN_32B;
962 break;
963 default:
964 ret = -EINVAL;
965 goto _set_tdm_err_;
966 }
967
968 /* Rx slot configuration */
969 rx_slotnum = hweight_long(rx_mask);
970 if (rx_slotnum != 1) {
971 ret = -EINVAL;
972 dev_err(component->dev, "too many rx slots or zero slot\n");
973 goto _set_tdm_err_;
974 }
975
976 /* This is an assumption that the system sends stereo audio to the amplifier typically.
977 * And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
978 * The users could select the channel from L/R/L+R by "Mono LR Select" control.
979 */
980 first_bit = __ffs(rx_mask);
981 switch (first_bit) {
982 case 0:
983 case 2:
984 case 4:
985 case 6:
986 snd_soc_component_update_bits(component,
987 RT1015_TDM1_4,
988 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
989 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
990 (first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
991 ((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
992 break;
993 case 1:
994 case 3:
995 case 5:
996 case 7:
997 snd_soc_component_update_bits(component,
998 RT1015_TDM1_4,
999 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
1000 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
1001 ((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
1002 (first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
1003 break;
1004 default:
1005 ret = -EINVAL;
1006 goto _set_tdm_err_;
1007 }
1008
1009 /* Tx slot configuration */
1010 tx_slotnum = hweight_long(tx_mask);
1011 if (tx_slotnum) {
1012 ret = -EINVAL;
1013 dev_err(component->dev, "doesn't need to support tx slots\n");
1014 goto _set_tdm_err_;
1015 }
1016
1017 snd_soc_component_update_bits(component, RT1015_TDM1_1,
1018 RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
1019 RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
1020
1021_set_tdm_err_:
1022 return ret;
1023}
1024
1025static int rt1015_probe(struct snd_soc_component *component)
1026{
1027 struct rt1015_priv *rt1015 =
1028 snd_soc_component_get_drvdata(component);
1029
1030 rt1015->component = component;
1031 INIT_DELAYED_WORK(&rt1015->flush_work, rt1015_flush_work);
1032
1033 return 0;
1034}
1035
1036static void rt1015_remove(struct snd_soc_component *component)
1037{
1038 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1039
1040 cancel_delayed_work_sync(&rt1015->flush_work);
1041 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1042}
1043
1044#define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1045#define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1046 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1047
1048static const struct snd_soc_dai_ops rt1015_aif_dai_ops = {
1049 .hw_params = rt1015_hw_params,
1050 .set_fmt = rt1015_set_dai_fmt,
1051 .set_tdm_slot = rt1015_set_tdm_slot,
1052};
1053
1054static struct snd_soc_dai_driver rt1015_dai[] = {
1055 {
1056 .name = "rt1015-aif",
1057 .id = 0,
1058 .playback = {
1059 .stream_name = "AIF Playback",
1060 .channels_min = 1,
1061 .channels_max = 4,
1062 .rates = RT1015_STEREO_RATES,
1063 .formats = RT1015_FORMATS,
1064 },
1065 .ops = &rt1015_aif_dai_ops,
1066 }
1067};
1068
1069#ifdef CONFIG_PM
1070static int rt1015_suspend(struct snd_soc_component *component)
1071{
1072 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1073
1074 regcache_cache_only(rt1015->regmap, true);
1075 regcache_mark_dirty(rt1015->regmap);
1076
1077 return 0;
1078}
1079
1080static int rt1015_resume(struct snd_soc_component *component)
1081{
1082 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1083
1084 regcache_cache_only(rt1015->regmap, false);
1085 regcache_sync(rt1015->regmap);
1086
1087 if (rt1015->cali_done)
1088 rt1015_calibrate(rt1015);
1089
1090 return 0;
1091}
1092#else
1093#define rt1015_suspend NULL
1094#define rt1015_resume NULL
1095#endif
1096
1097static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
1098 .probe = rt1015_probe,
1099 .remove = rt1015_remove,
1100 .suspend = rt1015_suspend,
1101 .resume = rt1015_resume,
1102 .controls = rt1015_snd_controls,
1103 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
1104 .dapm_widgets = rt1015_dapm_widgets,
1105 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
1106 .dapm_routes = rt1015_dapm_routes,
1107 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
1108 .set_sysclk = rt1015_set_component_sysclk,
1109 .set_pll = rt1015_set_component_pll,
1110 .use_pmdown_time = 1,
1111 .endianness = 1,
1112 .non_legacy_dai_naming = 1,
1113};
1114
1115static const struct regmap_config rt1015_regmap = {
1116 .reg_bits = 16,
1117 .val_bits = 16,
1118 .max_register = RT1015_S_BST_TIMING_INTER36,
1119 .volatile_reg = rt1015_volatile_register,
1120 .readable_reg = rt1015_readable_register,
1121 .cache_type = REGCACHE_RBTREE,
1122 .reg_defaults = rt1015_reg,
1123 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1124};
1125
1126static const struct i2c_device_id rt1015_i2c_id[] = {
1127 { "rt1015", 0 },
1128 { }
1129};
1130MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1131
1132#if defined(CONFIG_OF)
1133static const struct of_device_id rt1015_of_match[] = {
1134 { .compatible = "realtek,rt1015", },
1135 {},
1136};
1137MODULE_DEVICE_TABLE(of, rt1015_of_match);
1138#endif
1139
1140#ifdef CONFIG_ACPI
1141static const struct acpi_device_id rt1015_acpi_match[] = {
1142 {"10EC1015", 0,},
1143 {},
1144};
1145MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1146#endif
1147
1148static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
1149{
1150 device_property_read_u32(dev, "realtek,power-up-delay-ms",
1151 &rt1015->pdata.power_up_delay_ms);
1152}
1153
1154static int rt1015_i2c_probe(struct i2c_client *i2c,
1155 const struct i2c_device_id *id)
1156{
1157 struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev);
1158 struct rt1015_priv *rt1015;
1159 int ret;
1160 unsigned int val;
1161
1162 rt1015 = devm_kzalloc(&i2c->dev, sizeof(*rt1015), GFP_KERNEL);
1163 if (!rt1015)
1164 return -ENOMEM;
1165
1166 i2c_set_clientdata(i2c, rt1015);
1167
1168 rt1015->pdata = i2s_default_platform_data;
1169
1170 if (pdata)
1171 rt1015->pdata = *pdata;
1172 else
1173 rt1015_parse_dt(rt1015, &i2c->dev);
1174
1175 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1176 if (IS_ERR(rt1015->regmap)) {
1177 ret = PTR_ERR(rt1015->regmap);
1178 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1179 ret);
1180 return ret;
1181 }
1182
1183 rt1015->hw_config = (i2c->addr == 0x29) ? RT1015_HW_29 : RT1015_HW_28;
1184
1185 ret = regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1186 if (ret) {
1187 dev_err(&i2c->dev,
1188 "Failed to read device register: %d\n", ret);
1189 return ret;
1190 } else if ((val != RT1015_DEVICE_ID_VAL) &&
1191 (val != RT1015_DEVICE_ID_VAL2)) {
1192 dev_err(&i2c->dev,
1193 "Device with ID register %x is not rt1015\n", val);
1194 return -ENODEV;
1195 }
1196
1197 return devm_snd_soc_register_component(&i2c->dev,
1198 &soc_component_dev_rt1015,
1199 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1200}
1201
1202static void rt1015_i2c_shutdown(struct i2c_client *client)
1203{
1204 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1205
1206 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1207}
1208
1209static struct i2c_driver rt1015_i2c_driver = {
1210 .driver = {
1211 .name = "rt1015",
1212 .of_match_table = of_match_ptr(rt1015_of_match),
1213 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1214 },
1215 .probe = rt1015_i2c_probe,
1216 .shutdown = rt1015_i2c_shutdown,
1217 .id_table = rt1015_i2c_id,
1218};
1219module_i2c_driver(rt1015_i2c_driver);
1220
1221MODULE_DESCRIPTION("ASoC RT1015 driver");
1222MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1223MODULE_LICENSE("GPL v2");