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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3
4 Header file for stmmac platform data
5
6 Copyright (C) 2009 STMicroelectronics Ltd
7
8
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10*******************************************************************************/
11
12#ifndef __STMMAC_PLATFORM_DATA
13#define __STMMAC_PLATFORM_DATA
14
15#include <linux/platform_device.h>
16#include <linux/phy.h>
17
18#define MTL_MAX_RX_QUEUES 8
19#define MTL_MAX_TX_QUEUES 8
20#define STMMAC_CH_MAX 8
21
22#define STMMAC_RX_COE_NONE 0
23#define STMMAC_RX_COE_TYPE1 1
24#define STMMAC_RX_COE_TYPE2 2
25
26/* Define the macros for CSR clock range parameters to be passed by
27 * platform code.
28 * This could also be configured at run time using CPU freq framework. */
29
30/* MDC Clock Selection define*/
31#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
32#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
33#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
34#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
35#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
36#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
37
38/* MTL algorithms identifiers */
39#define MTL_TX_ALGORITHM_WRR 0x0
40#define MTL_TX_ALGORITHM_WFQ 0x1
41#define MTL_TX_ALGORITHM_DWRR 0x2
42#define MTL_TX_ALGORITHM_SP 0x3
43#define MTL_RX_ALGORITHM_SP 0x4
44#define MTL_RX_ALGORITHM_WSP 0x5
45
46/* RX/TX Queue Mode */
47#define MTL_QUEUE_AVB 0x0
48#define MTL_QUEUE_DCB 0x1
49
50/* The MDC clock could be set higher than the IEEE 802.3
51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
52 * of value different than the above defined values. The resultant MDIO
53 * clock frequency of 12.5 MHz is applicable for the interfacing chips
54 * supporting higher MDC clocks.
55 * The MDC clock selection macros need to be defined for MDC clock rate
56 * of 12.5 MHz, corresponding to the following selection.
57 */
58#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
59#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
60#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
61#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
62#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
63#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
64#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
65#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
66
67/* AXI DMA Burst length supported */
68#define DMA_AXI_BLEN_4 (1 << 1)
69#define DMA_AXI_BLEN_8 (1 << 2)
70#define DMA_AXI_BLEN_16 (1 << 3)
71#define DMA_AXI_BLEN_32 (1 << 4)
72#define DMA_AXI_BLEN_64 (1 << 5)
73#define DMA_AXI_BLEN_128 (1 << 6)
74#define DMA_AXI_BLEN_256 (1 << 7)
75#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
78
79/* Platfrom data for platform device structure's platform_data field */
80
81struct stmmac_mdio_bus_data {
82 unsigned int phy_mask;
83 unsigned int has_xpcs;
84 unsigned int xpcs_an_inband;
85 int *irqs;
86 int probed_phy_irq;
87 bool needs_reset;
88};
89
90struct stmmac_dma_cfg {
91 int pbl;
92 int txpbl;
93 int rxpbl;
94 bool pblx8;
95 int fixed_burst;
96 int mixed_burst;
97 bool aal;
98 bool eame;
99 bool multi_msi_en;
100 bool dche;
101};
102
103#define AXI_BLEN 7
104struct stmmac_axi {
105 bool axi_lpi_en;
106 bool axi_xit_frm;
107 u32 axi_wr_osr_lmt;
108 u32 axi_rd_osr_lmt;
109 bool axi_kbbe;
110 u32 axi_blen[AXI_BLEN];
111 bool axi_fb;
112 bool axi_mb;
113 bool axi_rb;
114};
115
116#define EST_GCL 1024
117struct stmmac_est {
118 int enable;
119 u32 btr_offset[2];
120 u32 btr[2];
121 u32 ctr[2];
122 u32 ter;
123 u32 gcl_unaligned[EST_GCL];
124 u32 gcl[EST_GCL];
125 u32 gcl_size;
126};
127
128struct stmmac_rxq_cfg {
129 u8 mode_to_use;
130 u32 chan;
131 u8 pkt_route;
132 bool use_prio;
133 u32 prio;
134};
135
136struct stmmac_txq_cfg {
137 u32 weight;
138 u8 mode_to_use;
139 /* Credit Base Shaper parameters */
140 u32 send_slope;
141 u32 idle_slope;
142 u32 high_credit;
143 u32 low_credit;
144 bool use_prio;
145 u32 prio;
146 int tbs_en;
147};
148
149/* FPE link state */
150enum stmmac_fpe_state {
151 FPE_STATE_OFF = 0,
152 FPE_STATE_CAPABLE = 1,
153 FPE_STATE_ENTERING_ON = 2,
154 FPE_STATE_ON = 3,
155};
156
157/* FPE link-partner hand-shaking mPacket type */
158enum stmmac_mpacket_type {
159 MPACKET_VERIFY = 0,
160 MPACKET_RESPONSE = 1,
161};
162
163enum stmmac_fpe_task_state_t {
164 __FPE_REMOVING,
165 __FPE_TASK_SCHED,
166};
167
168struct stmmac_fpe_cfg {
169 bool enable; /* FPE enable */
170 bool hs_enable; /* FPE handshake enable */
171 enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
172 enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
173};
174
175struct plat_stmmacenet_data {
176 int bus_id;
177 int phy_addr;
178 int interface;
179 phy_interface_t phy_interface;
180 struct stmmac_mdio_bus_data *mdio_bus_data;
181 struct device_node *phy_node;
182 struct device_node *phylink_node;
183 struct device_node *mdio_node;
184 struct stmmac_dma_cfg *dma_cfg;
185 struct stmmac_est *est;
186 struct stmmac_fpe_cfg *fpe_cfg;
187 int clk_csr;
188 int has_gmac;
189 int enh_desc;
190 int tx_coe;
191 int rx_coe;
192 int bugged_jumbo;
193 int pmt;
194 int force_sf_dma_mode;
195 int force_thresh_dma_mode;
196 int riwt_off;
197 int max_speed;
198 int maxmtu;
199 int multicast_filter_bins;
200 int unicast_filter_entries;
201 int tx_fifo_size;
202 int rx_fifo_size;
203 u32 addr64;
204 u32 rx_queues_to_use;
205 u32 tx_queues_to_use;
206 u8 rx_sched_algorithm;
207 u8 tx_sched_algorithm;
208 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
209 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
210 void (*fix_mac_speed)(void *priv, unsigned int speed);
211 int (*serdes_powerup)(struct net_device *ndev, void *priv);
212 void (*serdes_powerdown)(struct net_device *ndev, void *priv);
213 void (*ptp_clk_freq_config)(void *priv);
214 int (*init)(struct platform_device *pdev, void *priv);
215 void (*exit)(struct platform_device *pdev, void *priv);
216 struct mac_device_info *(*setup)(void *priv);
217 int (*clks_config)(void *priv, bool enabled);
218 int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
219 void *ctx);
220 void *bsp_priv;
221 struct clk *stmmac_clk;
222 struct clk *pclk;
223 struct clk *clk_ptp_ref;
224 unsigned int clk_ptp_rate;
225 unsigned int clk_ref_rate;
226 s32 ptp_max_adj;
227 struct reset_control *stmmac_rst;
228 struct stmmac_axi *axi;
229 int has_gmac4;
230 bool has_sun8i;
231 bool tso_en;
232 int rss_en;
233 int mac_port_sel_speed;
234 bool en_tx_lpi_clockgating;
235 int has_xgmac;
236 bool vlan_fail_q_en;
237 u8 vlan_fail_q;
238 unsigned int eee_usecs_rate;
239 struct pci_dev *pdev;
240 bool has_crossts;
241 int int_snapshot_num;
242 int ext_snapshot_num;
243 bool ext_snapshot_en;
244 bool multi_msi_en;
245 int msi_mac_vec;
246 int msi_wol_vec;
247 int msi_lpi_vec;
248 int msi_sfty_ce_vec;
249 int msi_sfty_ue_vec;
250 int msi_rx_base_vec;
251 int msi_tx_base_vec;
252};
253#endif