tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2017-2019, Linaro Ltd.
5 */
6
7#include <linux/debugfs.h>
8#include <linux/err.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/random.h>
12#include <linux/slab.h>
13#include <linux/soc/qcom/smem.h>
14#include <linux/string.h>
15#include <linux/sys_soc.h>
16#include <linux/types.h>
17
18#include <asm/unaligned.h>
19
20/*
21 * SoC version type with major number in the upper 16 bits and minor
22 * number in the lower 16 bits.
23 */
24#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
25#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
26#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
27
28#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
29#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
30
31/*
32 * SMEM item id, used to acquire handles to respective
33 * SMEM region.
34 */
35#define SMEM_HW_SW_BUILD_ID 137
36
37#ifdef CONFIG_DEBUG_FS
38#define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32
39#define SMEM_IMAGE_VERSION_SIZE 4096
40#define SMEM_IMAGE_VERSION_NAME_SIZE 75
41#define SMEM_IMAGE_VERSION_VARIANT_SIZE 20
42#define SMEM_IMAGE_VERSION_OEM_SIZE 32
43
44/*
45 * SMEM Image table indices
46 */
47#define SMEM_IMAGE_TABLE_BOOT_INDEX 0
48#define SMEM_IMAGE_TABLE_TZ_INDEX 1
49#define SMEM_IMAGE_TABLE_RPM_INDEX 3
50#define SMEM_IMAGE_TABLE_APPS_INDEX 10
51#define SMEM_IMAGE_TABLE_MPSS_INDEX 11
52#define SMEM_IMAGE_TABLE_ADSP_INDEX 12
53#define SMEM_IMAGE_TABLE_CNSS_INDEX 13
54#define SMEM_IMAGE_TABLE_VIDEO_INDEX 14
55#define SMEM_IMAGE_VERSION_TABLE 469
56
57/*
58 * SMEM Image table names
59 */
60static const char *const socinfo_image_names[] = {
61 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp",
62 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps",
63 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot",
64 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
65 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
66 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
67 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
68 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
69};
70
71static const char *const pmic_models[] = {
72 [0] = "Unknown PMIC model",
73 [9] = "PM8994",
74 [11] = "PM8916",
75 [13] = "PM8058",
76 [14] = "PM8028",
77 [15] = "PM8901",
78 [16] = "PM8027",
79 [17] = "ISL9519",
80 [18] = "PM8921",
81 [19] = "PM8018",
82 [20] = "PM8015",
83 [21] = "PM8014",
84 [22] = "PM8821",
85 [23] = "PM8038",
86 [24] = "PM8922",
87 [25] = "PM8917",
88 [30] = "PM8150",
89 [31] = "PM8150L",
90 [32] = "PM8150B",
91 [33] = "PMK8002",
92 [36] = "PM8009",
93};
94#endif /* CONFIG_DEBUG_FS */
95
96/* Socinfo SMEM item structure */
97struct socinfo {
98 __le32 fmt;
99 __le32 id;
100 __le32 ver;
101 char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
102 /* Version 2 */
103 __le32 raw_id;
104 __le32 raw_ver;
105 /* Version 3 */
106 __le32 hw_plat;
107 /* Version 4 */
108 __le32 plat_ver;
109 /* Version 5 */
110 __le32 accessory_chip;
111 /* Version 6 */
112 __le32 hw_plat_subtype;
113 /* Version 7 */
114 __le32 pmic_model;
115 __le32 pmic_die_rev;
116 /* Version 8 */
117 __le32 pmic_model_1;
118 __le32 pmic_die_rev_1;
119 __le32 pmic_model_2;
120 __le32 pmic_die_rev_2;
121 /* Version 9 */
122 __le32 foundry_id;
123 /* Version 10 */
124 __le32 serial_num;
125 /* Version 11 */
126 __le32 num_pmics;
127 __le32 pmic_array_offset;
128 /* Version 12 */
129 __le32 chip_family;
130 __le32 raw_device_family;
131 __le32 raw_device_num;
132 /* Version 13 */
133 __le32 nproduct_id;
134 char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
135 /* Version 14 */
136 __le32 num_clusters;
137 __le32 ncluster_array_offset;
138 __le32 num_defective_parts;
139 __le32 ndefective_parts_array_offset;
140 /* Version 15 */
141 __le32 nmodem_supported;
142};
143
144#ifdef CONFIG_DEBUG_FS
145struct socinfo_params {
146 u32 raw_device_family;
147 u32 hw_plat_subtype;
148 u32 accessory_chip;
149 u32 raw_device_num;
150 u32 chip_family;
151 u32 foundry_id;
152 u32 plat_ver;
153 u32 raw_ver;
154 u32 hw_plat;
155 u32 fmt;
156 u32 nproduct_id;
157 u32 num_clusters;
158 u32 ncluster_array_offset;
159 u32 num_defective_parts;
160 u32 ndefective_parts_array_offset;
161 u32 nmodem_supported;
162};
163
164struct smem_image_version {
165 char name[SMEM_IMAGE_VERSION_NAME_SIZE];
166 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE];
167 char pad;
168 char oem[SMEM_IMAGE_VERSION_OEM_SIZE];
169};
170#endif /* CONFIG_DEBUG_FS */
171
172struct qcom_socinfo {
173 struct soc_device *soc_dev;
174 struct soc_device_attribute attr;
175#ifdef CONFIG_DEBUG_FS
176 struct dentry *dbg_root;
177 struct socinfo_params info;
178#endif /* CONFIG_DEBUG_FS */
179};
180
181struct soc_id {
182 unsigned int id;
183 const char *name;
184};
185
186static const struct soc_id soc_id[] = {
187 { 87, "MSM8960" },
188 { 109, "APQ8064" },
189 { 122, "MSM8660A" },
190 { 123, "MSM8260A" },
191 { 124, "APQ8060A" },
192 { 126, "MSM8974" },
193 { 130, "MPQ8064" },
194 { 138, "MSM8960AB" },
195 { 139, "APQ8060AB" },
196 { 140, "MSM8260AB" },
197 { 141, "MSM8660AB" },
198 { 178, "APQ8084" },
199 { 184, "APQ8074" },
200 { 185, "MSM8274" },
201 { 186, "MSM8674" },
202 { 194, "MSM8974PRO" },
203 { 206, "MSM8916" },
204 { 207, "MSM8994" },
205 { 208, "APQ8074-AA" },
206 { 209, "APQ8074-AB" },
207 { 210, "APQ8074PRO" },
208 { 211, "MSM8274-AA" },
209 { 212, "MSM8274-AB" },
210 { 213, "MSM8274PRO" },
211 { 214, "MSM8674-AA" },
212 { 215, "MSM8674-AB" },
213 { 216, "MSM8674PRO" },
214 { 217, "MSM8974-AA" },
215 { 218, "MSM8974-AB" },
216 { 233, "MSM8936" },
217 { 239, "MSM8939" },
218 { 240, "APQ8036" },
219 { 241, "APQ8039" },
220 { 246, "MSM8996" },
221 { 247, "APQ8016" },
222 { 248, "MSM8216" },
223 { 249, "MSM8116" },
224 { 250, "MSM8616" },
225 { 251, "MSM8992" },
226 { 253, "APQ8094" },
227 { 290, "MDM9607" },
228 { 291, "APQ8096" },
229 { 292, "MSM8998" },
230 { 293, "MSM8953" },
231 { 296, "MDM8207" },
232 { 297, "MDM9207" },
233 { 298, "MDM9307" },
234 { 299, "MDM9628" },
235 { 304, "APQ8053" },
236 { 305, "MSM8996SG" },
237 { 310, "MSM8996AU" },
238 { 311, "APQ8096AU" },
239 { 312, "APQ8096SG" },
240 { 317, "SDM660" },
241 { 318, "SDM630" },
242 { 319, "APQ8098" },
243 { 321, "SDM845" },
244 { 322, "MDM9206" },
245 { 324, "SDA660" },
246 { 325, "SDM658" },
247 { 326, "SDA658" },
248 { 327, "SDA630" },
249 { 338, "SDM450" },
250 { 341, "SDA845" },
251 { 345, "SDM636" },
252 { 346, "SDA636" },
253 { 349, "SDM632" },
254 { 350, "SDA632" },
255 { 351, "SDA450" },
256 { 356, "SM8250" },
257 { 402, "IPQ6018" },
258 { 425, "SC7180" },
259 { 455, "QRB5165" },
260};
261
262static const char *socinfo_machine(struct device *dev, unsigned int id)
263{
264 int idx;
265
266 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) {
267 if (soc_id[idx].id == id)
268 return soc_id[idx].name;
269 }
270
271 return NULL;
272}
273
274#ifdef CONFIG_DEBUG_FS
275
276#define QCOM_OPEN(name, _func) \
277static int qcom_open_##name(struct inode *inode, struct file *file) \
278{ \
279 return single_open(file, _func, inode->i_private); \
280} \
281 \
282static const struct file_operations qcom_ ##name## _ops = { \
283 .open = qcom_open_##name, \
284 .read = seq_read, \
285 .llseek = seq_lseek, \
286 .release = single_release, \
287}
288
289#define DEBUGFS_ADD(info, name) \
290 debugfs_create_file(__stringify(name), 0444, \
291 qcom_socinfo->dbg_root, \
292 info, &qcom_ ##name## _ops)
293
294
295static int qcom_show_build_id(struct seq_file *seq, void *p)
296{
297 struct socinfo *socinfo = seq->private;
298
299 seq_printf(seq, "%s\n", socinfo->build_id);
300
301 return 0;
302}
303
304static int qcom_show_pmic_model(struct seq_file *seq, void *p)
305{
306 struct socinfo *socinfo = seq->private;
307 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model));
308
309 if (model < 0)
310 return -EINVAL;
311
312 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
313 seq_printf(seq, "%s\n", pmic_models[model]);
314 else
315 seq_printf(seq, "unknown (%d)\n", model);
316
317 return 0;
318}
319
320static int qcom_show_pmic_model_array(struct seq_file *seq, void *p)
321{
322 struct socinfo *socinfo = seq->private;
323 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics);
324 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset);
325 int i;
326 void *ptr = socinfo;
327
328 ptr += pmic_array_offset;
329
330 /* No need for bounds checking, it happened at socinfo_debugfs_init */
331 for (i = 0; i < num_pmics; i++) {
332 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32)));
333 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32));
334
335 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
336 seq_printf(seq, "%s %u.%u\n", pmic_models[model],
337 SOCINFO_MAJOR(die_rev),
338 SOCINFO_MINOR(die_rev));
339 else
340 seq_printf(seq, "unknown (%d)\n", model);
341 }
342
343 return 0;
344}
345
346static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p)
347{
348 struct socinfo *socinfo = seq->private;
349
350 seq_printf(seq, "%u.%u\n",
351 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)),
352 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev)));
353
354 return 0;
355}
356
357static int qcom_show_chip_id(struct seq_file *seq, void *p)
358{
359 struct socinfo *socinfo = seq->private;
360
361 seq_printf(seq, "%s\n", socinfo->chip_id);
362
363 return 0;
364}
365
366QCOM_OPEN(build_id, qcom_show_build_id);
367QCOM_OPEN(pmic_model, qcom_show_pmic_model);
368QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array);
369QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision);
370QCOM_OPEN(chip_id, qcom_show_chip_id);
371
372#define DEFINE_IMAGE_OPS(type) \
373static int show_image_##type(struct seq_file *seq, void *p) \
374{ \
375 struct smem_image_version *image_version = seq->private; \
376 seq_puts(seq, image_version->type); \
377 seq_putc(seq, '\n'); \
378 return 0; \
379} \
380static int open_image_##type(struct inode *inode, struct file *file) \
381{ \
382 return single_open(file, show_image_##type, inode->i_private); \
383} \
384 \
385static const struct file_operations qcom_image_##type##_ops = { \
386 .open = open_image_##type, \
387 .read = seq_read, \
388 .llseek = seq_lseek, \
389 .release = single_release, \
390}
391
392DEFINE_IMAGE_OPS(name);
393DEFINE_IMAGE_OPS(variant);
394DEFINE_IMAGE_OPS(oem);
395
396static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
397 struct socinfo *info, size_t info_size)
398{
399 struct smem_image_version *versions;
400 struct dentry *dentry;
401 size_t size;
402 int i;
403 unsigned int num_pmics;
404 unsigned int pmic_array_offset;
405
406 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL);
407
408 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt);
409
410 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root,
411 &qcom_socinfo->info.fmt);
412
413 switch (qcom_socinfo->info.fmt) {
414 case SOCINFO_VERSION(0, 15):
415 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported);
416
417 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root,
418 &qcom_socinfo->info.nmodem_supported);
419 fallthrough;
420 case SOCINFO_VERSION(0, 14):
421 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
422 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
423 qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
424 qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
425
426 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
427 &qcom_socinfo->info.num_clusters);
428 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
429 &qcom_socinfo->info.ncluster_array_offset);
430 debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
431 &qcom_socinfo->info.num_defective_parts);
432 debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
433 &qcom_socinfo->info.ndefective_parts_array_offset);
434 fallthrough;
435 case SOCINFO_VERSION(0, 13):
436 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);
437
438 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root,
439 &qcom_socinfo->info.nproduct_id);
440 DEBUGFS_ADD(info, chip_id);
441 fallthrough;
442 case SOCINFO_VERSION(0, 12):
443 qcom_socinfo->info.chip_family =
444 __le32_to_cpu(info->chip_family);
445 qcom_socinfo->info.raw_device_family =
446 __le32_to_cpu(info->raw_device_family);
447 qcom_socinfo->info.raw_device_num =
448 __le32_to_cpu(info->raw_device_num);
449
450 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root,
451 &qcom_socinfo->info.chip_family);
452 debugfs_create_x32("raw_device_family", 0444,
453 qcom_socinfo->dbg_root,
454 &qcom_socinfo->info.raw_device_family);
455 debugfs_create_x32("raw_device_number", 0444,
456 qcom_socinfo->dbg_root,
457 &qcom_socinfo->info.raw_device_num);
458 fallthrough;
459 case SOCINFO_VERSION(0, 11):
460 num_pmics = le32_to_cpu(info->num_pmics);
461 pmic_array_offset = le32_to_cpu(info->pmic_array_offset);
462 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size)
463 DEBUGFS_ADD(info, pmic_model_array);
464 fallthrough;
465 case SOCINFO_VERSION(0, 10):
466 case SOCINFO_VERSION(0, 9):
467 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id);
468
469 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root,
470 &qcom_socinfo->info.foundry_id);
471 fallthrough;
472 case SOCINFO_VERSION(0, 8):
473 case SOCINFO_VERSION(0, 7):
474 DEBUGFS_ADD(info, pmic_model);
475 DEBUGFS_ADD(info, pmic_die_rev);
476 fallthrough;
477 case SOCINFO_VERSION(0, 6):
478 qcom_socinfo->info.hw_plat_subtype =
479 __le32_to_cpu(info->hw_plat_subtype);
480
481 debugfs_create_u32("hardware_platform_subtype", 0444,
482 qcom_socinfo->dbg_root,
483 &qcom_socinfo->info.hw_plat_subtype);
484 fallthrough;
485 case SOCINFO_VERSION(0, 5):
486 qcom_socinfo->info.accessory_chip =
487 __le32_to_cpu(info->accessory_chip);
488
489 debugfs_create_u32("accessory_chip", 0444,
490 qcom_socinfo->dbg_root,
491 &qcom_socinfo->info.accessory_chip);
492 fallthrough;
493 case SOCINFO_VERSION(0, 4):
494 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver);
495
496 debugfs_create_u32("platform_version", 0444,
497 qcom_socinfo->dbg_root,
498 &qcom_socinfo->info.plat_ver);
499 fallthrough;
500 case SOCINFO_VERSION(0, 3):
501 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat);
502
503 debugfs_create_u32("hardware_platform", 0444,
504 qcom_socinfo->dbg_root,
505 &qcom_socinfo->info.hw_plat);
506 fallthrough;
507 case SOCINFO_VERSION(0, 2):
508 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
509
510 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
511 &qcom_socinfo->info.raw_ver);
512 fallthrough;
513 case SOCINFO_VERSION(0, 1):
514 DEBUGFS_ADD(info, build_id);
515 break;
516 }
517
518 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE,
519 &size);
520
521 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) {
522 if (!socinfo_image_names[i])
523 continue;
524
525 dentry = debugfs_create_dir(socinfo_image_names[i],
526 qcom_socinfo->dbg_root);
527 debugfs_create_file("name", 0444, dentry, &versions[i],
528 &qcom_image_name_ops);
529 debugfs_create_file("variant", 0444, dentry, &versions[i],
530 &qcom_image_variant_ops);
531 debugfs_create_file("oem", 0444, dentry, &versions[i],
532 &qcom_image_oem_ops);
533 }
534}
535
536static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo)
537{
538 debugfs_remove_recursive(qcom_socinfo->dbg_root);
539}
540#else
541static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
542 struct socinfo *info, size_t info_size)
543{
544}
545static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { }
546#endif /* CONFIG_DEBUG_FS */
547
548static int qcom_socinfo_probe(struct platform_device *pdev)
549{
550 struct qcom_socinfo *qs;
551 struct socinfo *info;
552 size_t item_size;
553
554 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID,
555 &item_size);
556 if (IS_ERR(info)) {
557 dev_err(&pdev->dev, "Couldn't find socinfo\n");
558 return PTR_ERR(info);
559 }
560
561 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL);
562 if (!qs)
563 return -ENOMEM;
564
565 qs->attr.family = "Snapdragon";
566 qs->attr.machine = socinfo_machine(&pdev->dev,
567 le32_to_cpu(info->id));
568 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u",
569 le32_to_cpu(info->id));
570 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u",
571 SOCINFO_MAJOR(le32_to_cpu(info->ver)),
572 SOCINFO_MINOR(le32_to_cpu(info->ver)));
573 if (offsetof(struct socinfo, serial_num) <= item_size)
574 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL,
575 "%u",
576 le32_to_cpu(info->serial_num));
577
578 qs->soc_dev = soc_device_register(&qs->attr);
579 if (IS_ERR(qs->soc_dev))
580 return PTR_ERR(qs->soc_dev);
581
582 socinfo_debugfs_init(qs, info, item_size);
583
584 /* Feed the soc specific unique data into entropy pool */
585 add_device_randomness(info, item_size);
586
587 platform_set_drvdata(pdev, qs->soc_dev);
588
589 return 0;
590}
591
592static int qcom_socinfo_remove(struct platform_device *pdev)
593{
594 struct qcom_socinfo *qs = platform_get_drvdata(pdev);
595
596 soc_device_unregister(qs->soc_dev);
597
598 socinfo_debugfs_exit(qs);
599
600 return 0;
601}
602
603static struct platform_driver qcom_socinfo_driver = {
604 .probe = qcom_socinfo_probe,
605 .remove = qcom_socinfo_remove,
606 .driver = {
607 .name = "qcom-socinfo",
608 },
609};
610
611module_platform_driver(qcom_socinfo_driver);
612
613MODULE_DESCRIPTION("Qualcomm SoCinfo driver");
614MODULE_LICENSE("GPL v2");
615MODULE_ALIAS("platform:qcom-socinfo");