Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1998-2000 Michel Aubry
4 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
7 * Portions copyright (c) 2001 Sun Microsystems
8 *
9 *
10 * RCC/ServerWorks IDE driver for Linux
11 *
12 * OSB4: `Open South Bridge' IDE Interface (fn 1)
13 * supports UDMA mode 2 (33 MB/s)
14 *
15 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
16 * all revisions support UDMA mode 4 (66 MB/s)
17 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
18 *
19 * *** The CSB5 does not provide ANY register ***
20 * *** to detect 80-conductor cable presence. ***
21 *
22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
23 *
24 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
25 * controller same as the CSB6. Single channel ATA100 only.
26 *
27 * Documentation:
28 * Available under NDA only. Errata info very hard to get.
29 *
30 */
31
32#include <linux/types.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/pci.h>
36#include <linux/ide.h>
37#include <linux/init.h>
38
39#include <asm/io.h>
40
41#define DRV_NAME "serverworks"
42
43#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
44#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
45
46/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
47 * can overrun their FIFOs when used with the CSB5 */
48static const char *svwks_bad_ata100[] = {
49 "ST320011A",
50 "ST340016A",
51 "ST360021A",
52 "ST380021A",
53 NULL
54};
55
56static int check_in_drive_lists (ide_drive_t *drive, const char **list)
57{
58 char *m = (char *)&drive->id[ATA_ID_PROD];
59
60 while (*list)
61 if (!strcmp(*list++, m))
62 return 1;
63 return 0;
64}
65
66static u8 svwks_udma_filter(ide_drive_t *drive)
67{
68 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
69
70 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
71 return 0x1f;
72 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
73 return 0x07;
74 } else {
75 u8 btr = 0, mode, mask;
76
77 pci_read_config_byte(dev, 0x5A, &btr);
78 mode = btr & 0x3;
79
80 /* If someone decides to do UDMA133 on CSB5 the same
81 issue will bite so be inclusive */
82 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
83 mode = 2;
84
85 switch(mode) {
86 case 3: mask = 0x3f; break;
87 case 2: mask = 0x1f; break;
88 case 1: mask = 0x07; break;
89 default: mask = 0x00; break;
90 }
91
92 return mask;
93 }
94}
95
96static u8 svwks_csb_check (struct pci_dev *dev)
97{
98 switch (dev->device) {
99 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
100 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
101 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
102 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
103 return 1;
104 default:
105 break;
106 }
107 return 0;
108}
109
110static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
111{
112 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
113 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
114
115 struct pci_dev *dev = to_pci_dev(hwif->dev);
116 const u8 pio = drive->pio_mode - XFER_PIO_0;
117
118 if (drive->dn >= ARRAY_SIZE(drive_pci))
119 return;
120
121 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
122
123 if (svwks_csb_check(dev)) {
124 u16 csb_pio = 0;
125
126 pci_read_config_word(dev, 0x4a, &csb_pio);
127
128 csb_pio &= ~(0x0f << (4 * drive->dn));
129 csb_pio |= (pio << (4 * drive->dn));
130
131 pci_write_config_word(dev, 0x4a, csb_pio);
132 }
133}
134
135static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
136{
137 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
138 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
139 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
140
141 struct pci_dev *dev = to_pci_dev(hwif->dev);
142 const u8 speed = drive->dma_mode;
143 u8 unit = drive->dn & 1;
144
145 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
146
147 if (drive->dn >= ARRAY_SIZE(drive_pci2))
148 return;
149
150 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
151 pci_read_config_byte(dev, 0x54, &ultra_enable);
152
153 ultra_timing &= ~(0x0F << (4*unit));
154 ultra_enable &= ~(0x01 << drive->dn);
155
156 if (speed >= XFER_UDMA_0) {
157 dma_timing |= dma_modes[2];
158 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
159 ultra_enable |= (0x01 << drive->dn);
160 } else if (speed >= XFER_MW_DMA_0)
161 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
162
163 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
164 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
165 pci_write_config_byte(dev, 0x54, ultra_enable);
166}
167
168static int init_chipset_svwks(struct pci_dev *dev)
169{
170 unsigned int reg;
171 u8 btr;
172
173 /* force Master Latency Timer value to 64 PCICLKs */
174 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
175
176 /* OSB4 : South Bridge and IDE */
177 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
178 struct pci_dev *isa_dev =
179 pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
180 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
181 if (isa_dev) {
182 pci_read_config_dword(isa_dev, 0x64, ®);
183 reg &= ~0x00002000; /* disable 600ns interrupt mask */
184 if(!(reg & 0x00004000))
185 printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
186 "enabled.\n", pci_name(dev));
187 reg |= 0x00004000; /* enable UDMA/33 support */
188 pci_write_config_dword(isa_dev, 0x64, reg);
189 pci_dev_put(isa_dev);
190 }
191 }
192
193 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
194 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
195 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
196 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
197
198 /* Third Channel Test */
199 if (!(PCI_FUNC(dev->devfn) & 1)) {
200 struct pci_dev * findev = NULL;
201 u32 reg4c = 0;
202 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
203 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
204 if (findev) {
205 pci_read_config_dword(findev, 0x4C, ®4c);
206 reg4c &= ~0x000007FF;
207 reg4c |= 0x00000040;
208 reg4c |= 0x00000020;
209 pci_write_config_dword(findev, 0x4C, reg4c);
210 pci_dev_put(findev);
211 }
212 outb_p(0x06, 0x0c00);
213 dev->irq = inb_p(0x0c01);
214 } else {
215 struct pci_dev * findev = NULL;
216 u8 reg41 = 0;
217
218 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
219 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
220 if (findev) {
221 pci_read_config_byte(findev, 0x41, ®41);
222 reg41 &= ~0x40;
223 pci_write_config_byte(findev, 0x41, reg41);
224 pci_dev_put(findev);
225 }
226 /*
227 * This is a device pin issue on CSB6.
228 * Since there will be a future raid mode,
229 * early versions of the chipset require the
230 * interrupt pin to be set, and it is a compatibility
231 * mode issue.
232 */
233 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
234 dev->irq = 0;
235 }
236// pci_read_config_dword(dev, 0x40, &pioreg)
237// pci_write_config_dword(dev, 0x40, 0x99999999);
238// pci_read_config_dword(dev, 0x44, &dmareg);
239// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
240 /* setup the UDMA Control register
241 *
242 * 1. clear bit 6 to enable DMA
243 * 2. enable DMA modes with bits 0-1
244 * 00 : legacy
245 * 01 : udma2
246 * 10 : udma2/udma4
247 * 11 : udma2/udma4/udma5
248 */
249 pci_read_config_byte(dev, 0x5A, &btr);
250 btr &= ~0x40;
251 if (!(PCI_FUNC(dev->devfn) & 1))
252 btr |= 0x2;
253 else
254 btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
255 pci_write_config_byte(dev, 0x5A, btr);
256 }
257 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
258 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
259 pci_read_config_byte(dev, 0x5A, &btr);
260 btr &= ~0x40;
261 btr |= 0x3;
262 pci_write_config_byte(dev, 0x5A, btr);
263 }
264
265 return 0;
266}
267
268static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
269{
270 return ATA_CBL_PATA80;
271}
272
273/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
274 * of the subsystem device ID indicate presence of an 80-pin cable.
275 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
276 * Bit 15 set = secondary IDE channel has 80-pin cable.
277 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
278 * Bit 14 set = primary IDE channel has 80-pin cable.
279 */
280static u8 ata66_svwks_dell(ide_hwif_t *hwif)
281{
282 struct pci_dev *dev = to_pci_dev(hwif->dev);
283
284 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
285 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
286 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
287 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
288 return ((1 << (hwif->channel + 14)) &
289 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
290 return ATA_CBL_PATA40;
291}
292
293/* Sun Cobalt Alpine hardware avoids the 80-pin cable
294 * detect issue by attaching the drives directly to the board.
295 * This check follows the Dell precedent (how scary is that?!)
296 *
297 * WARNING: this only works on Alpine hardware!
298 */
299static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
300{
301 struct pci_dev *dev = to_pci_dev(hwif->dev);
302
303 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
304 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
305 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
306 return ((1 << (hwif->channel + 14)) &
307 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
308 return ATA_CBL_PATA40;
309}
310
311static u8 svwks_cable_detect(ide_hwif_t *hwif)
312{
313 struct pci_dev *dev = to_pci_dev(hwif->dev);
314
315 /* Server Works */
316 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
317 return ata66_svwks_svwks (hwif);
318
319 /* Dell PowerEdge */
320 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
321 return ata66_svwks_dell (hwif);
322
323 /* Cobalt Alpine */
324 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
325 return ata66_svwks_cobalt (hwif);
326
327 /* Per Specified Design by OEM, and ASIC Architect */
328 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
329 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
330 return ATA_CBL_PATA80;
331
332 return ATA_CBL_PATA40;
333}
334
335static const struct ide_port_ops osb4_port_ops = {
336 .set_pio_mode = svwks_set_pio_mode,
337 .set_dma_mode = svwks_set_dma_mode,
338};
339
340static const struct ide_port_ops svwks_port_ops = {
341 .set_pio_mode = svwks_set_pio_mode,
342 .set_dma_mode = svwks_set_dma_mode,
343 .udma_filter = svwks_udma_filter,
344 .cable_detect = svwks_cable_detect,
345};
346
347static const struct ide_port_info serverworks_chipsets[] = {
348 { /* 0: OSB4 */
349 .name = DRV_NAME,
350 .init_chipset = init_chipset_svwks,
351 .port_ops = &osb4_port_ops,
352 .pio_mask = ATA_PIO4,
353 .mwdma_mask = ATA_MWDMA2,
354 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
355 },
356 { /* 1: CSB5 */
357 .name = DRV_NAME,
358 .init_chipset = init_chipset_svwks,
359 .port_ops = &svwks_port_ops,
360 .pio_mask = ATA_PIO4,
361 .mwdma_mask = ATA_MWDMA2,
362 .udma_mask = ATA_UDMA5,
363 },
364 { /* 2: CSB6 */
365 .name = DRV_NAME,
366 .init_chipset = init_chipset_svwks,
367 .port_ops = &svwks_port_ops,
368 .pio_mask = ATA_PIO4,
369 .mwdma_mask = ATA_MWDMA2,
370 .udma_mask = ATA_UDMA5,
371 },
372 { /* 3: CSB6-2 */
373 .name = DRV_NAME,
374 .init_chipset = init_chipset_svwks,
375 .port_ops = &svwks_port_ops,
376 .host_flags = IDE_HFLAG_SINGLE,
377 .pio_mask = ATA_PIO4,
378 .mwdma_mask = ATA_MWDMA2,
379 .udma_mask = ATA_UDMA5,
380 },
381 { /* 4: HT1000 */
382 .name = DRV_NAME,
383 .init_chipset = init_chipset_svwks,
384 .port_ops = &svwks_port_ops,
385 .host_flags = IDE_HFLAG_SINGLE,
386 .pio_mask = ATA_PIO4,
387 .mwdma_mask = ATA_MWDMA2,
388 .udma_mask = ATA_UDMA5,
389 }
390};
391
392/**
393 * svwks_init_one - called when a OSB/CSB is found
394 * @dev: the svwks device
395 * @id: the matching pci id
396 *
397 * Called when the PCI registration layer (or the IDE initialization)
398 * finds a device matching our IDE device tables.
399 */
400
401static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
402{
403 struct ide_port_info d;
404 u8 idx = id->driver_data;
405
406 d = serverworks_chipsets[idx];
407
408 if (idx == 1)
409 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
410 else if (idx == 2 || idx == 3) {
411 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
412 if (pci_resource_start(dev, 0) != 0x01f1)
413 d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
414 d.host_flags |= IDE_HFLAG_SINGLE;
415 } else
416 d.host_flags &= ~IDE_HFLAG_SINGLE;
417 }
418
419 return ide_pci_init_one(dev, &d, NULL);
420}
421
422static const struct pci_device_id svwks_pci_tbl[] = {
423 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
424 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
425 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
426 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
427 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
428 { 0, },
429};
430MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
431
432static struct pci_driver svwks_pci_driver = {
433 .name = "Serverworks_IDE",
434 .id_table = svwks_pci_tbl,
435 .probe = svwks_init_one,
436 .remove = ide_pci_remove,
437 .suspend = ide_pci_suspend,
438 .resume = ide_pci_resume,
439};
440
441static int __init svwks_ide_init(void)
442{
443 return ide_pci_register_driver(&svwks_pci_driver);
444}
445
446static void __exit svwks_ide_exit(void)
447{
448 pci_unregister_driver(&svwks_pci_driver);
449}
450
451module_init(svwks_ide_init);
452module_exit(svwks_ide_exit);
453
454MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
455MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
456MODULE_LICENSE("GPL");