tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip DWC HDMI TX Encoder
8
9maintainers:
10 - Mark Yao <markyao0591@gmail.com>
11
12description: |
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
14 with a companion PHY IP.
15
16allOf:
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18
19properties:
20 compatible:
21 enum:
22 - rockchip,rk3228-dw-hdmi
23 - rockchip,rk3288-dw-hdmi
24 - rockchip,rk3328-dw-hdmi
25 - rockchip,rk3399-dw-hdmi
26
27 reg-io-width:
28 const: 4
29
30 clocks:
31 minItems: 2
32 maxItems: 5
33 items:
34 - {}
35 - {}
36 # The next three clocks are all optional, but shall be specified in this
37 # order when present.
38 - description: The HDMI CEC controller main clock
39 - description: Power for GRF IO
40 - description: External clock for some HDMI PHY
41
42 clock-names:
43 minItems: 2
44 maxItems: 5
45 items:
46 - {}
47 - {}
48 - enum:
49 - cec
50 - grf
51 - vpll
52 - enum:
53 - grf
54 - vpll
55 - const: vpll
56
57 ddc-i2c-bus:
58 $ref: /schemas/types.yaml#/definitions/phandle
59 description:
60 The HDMI DDC bus can be connected to either a system I2C master or the
61 functionally-reduced I2C master contained in the DWC HDMI. When connected
62 to a system I2C master this property contains a phandle to that I2C
63 master controller.
64
65 phys:
66 maxItems: 1
67 description: The HDMI PHY
68
69 phy-names:
70 const: hdmi
71
72 pinctrl-names:
73 description:
74 The unwedge pinctrl entry shall drive the DDC SDA line low. This is
75 intended to work around a hardware errata that can cause the DDC I2C
76 bus to be wedged.
77 items:
78 - const: default
79 - const: unwedge
80
81 ports:
82 $ref: /schemas/graph.yaml#/properties/ports
83
84 properties:
85 port:
86 $ref: /schemas/graph.yaml#/$defs/port-base
87 unevaluatedProperties: false
88 description: Input of the DWC HDMI TX
89
90 properties:
91 endpoint@0:
92 $ref: /schemas/graph.yaml#/properties/endpoint
93 description: Connection to the VOPB
94
95 endpoint@1:
96 $ref: /schemas/graph.yaml#/properties/endpoint
97 description: Connection to the VOPL
98
99 required:
100 - endpoint@0
101 - endpoint@1
102
103 required:
104 - port
105
106 rockchip,grf:
107 $ref: /schemas/types.yaml#/definitions/phandle
108 description:
109 phandle to the GRF to mux vopl/vopb.
110
111required:
112 - compatible
113 - reg
114 - reg-io-width
115 - clocks
116 - clock-names
117 - interrupts
118 - ports
119 - rockchip,grf
120
121unevaluatedProperties: false
122
123examples:
124 - |
125 #include <dt-bindings/clock/rk3288-cru.h>
126 #include <dt-bindings/interrupt-controller/arm-gic.h>
127 #include <dt-bindings/interrupt-controller/irq.h>
128
129 hdmi: hdmi@ff980000 {
130 compatible = "rockchip,rk3288-dw-hdmi";
131 reg = <0xff980000 0x20000>;
132 reg-io-width = <4>;
133 ddc-i2c-bus = <&i2c5>;
134 rockchip,grf = <&grf>;
135 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
137 clock-names = "iahb", "isfr";
138
139 ports {
140 port {
141 #address-cells = <1>;
142 #size-cells = <0>;
143
144 hdmi_in_vopb: endpoint@0 {
145 reg = <0>;
146 remote-endpoint = <&vopb_out_hdmi>;
147 };
148 hdmi_in_vopl: endpoint@1 {
149 reg = <1>;
150 remote-endpoint = <&vopl_out_hdmi>;
151 };
152 };
153 };
154 };
155
156...