tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
3
4#ifndef __QCOM_CLK_ALPHA_PLL_H__
5#define __QCOM_CLK_ALPHA_PLL_H__
6
7#include <linux/clk-provider.h>
8#include "clk-regmap.h"
9
10/* Alpha PLL types */
11enum {
12 CLK_ALPHA_PLL_TYPE_DEFAULT,
13 CLK_ALPHA_PLL_TYPE_HUAYRA,
14 CLK_ALPHA_PLL_TYPE_BRAMMO,
15 CLK_ALPHA_PLL_TYPE_FABIA,
16 CLK_ALPHA_PLL_TYPE_TRION,
17 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
18 CLK_ALPHA_PLL_TYPE_AGERA,
19 CLK_ALPHA_PLL_TYPE_MAX,
20};
21
22enum {
23 PLL_OFF_L_VAL,
24 PLL_OFF_CAL_L_VAL,
25 PLL_OFF_ALPHA_VAL,
26 PLL_OFF_ALPHA_VAL_U,
27 PLL_OFF_USER_CTL,
28 PLL_OFF_USER_CTL_U,
29 PLL_OFF_USER_CTL_U1,
30 PLL_OFF_CONFIG_CTL,
31 PLL_OFF_CONFIG_CTL_U,
32 PLL_OFF_CONFIG_CTL_U1,
33 PLL_OFF_TEST_CTL,
34 PLL_OFF_TEST_CTL_U,
35 PLL_OFF_TEST_CTL_U1,
36 PLL_OFF_STATUS,
37 PLL_OFF_OPMODE,
38 PLL_OFF_FRAC,
39 PLL_OFF_CAL_VAL,
40 PLL_OFF_MAX_REGS
41};
42
43extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
44
45struct pll_vco {
46 unsigned long min_freq;
47 unsigned long max_freq;
48 u32 val;
49};
50
51#define VCO(a, b, c) { \
52 .val = a,\
53 .min_freq = b,\
54 .max_freq = c,\
55}
56
57/**
58 * struct clk_alpha_pll - phase locked loop (PLL)
59 * @offset: base address of registers
60 * @vco_table: array of VCO settings
61 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
62 * @clkr: regmap clock handle
63 */
64struct clk_alpha_pll {
65 u32 offset;
66 const u8 *regs;
67
68 const struct pll_vco *vco_table;
69 size_t num_vco;
70#define SUPPORTS_OFFLINE_REQ BIT(0)
71#define SUPPORTS_FSM_MODE BIT(2)
72#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
73 u8 flags;
74
75 struct clk_regmap clkr;
76};
77
78/**
79 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
80 * @offset: base address of registers
81 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
82 * @width: width of post-divider
83 * @post_div_shift: shift to differentiate between odd & even post-divider
84 * @post_div_table: table with PLL odd and even post-divider settings
85 * @num_post_div: Number of PLL post-divider settings
86 *
87 * @clkr: regmap clock handle
88 */
89struct clk_alpha_pll_postdiv {
90 u32 offset;
91 u8 width;
92 const u8 *regs;
93
94 struct clk_regmap clkr;
95 int post_div_shift;
96 const struct clk_div_table *post_div_table;
97 size_t num_post_div;
98};
99
100struct alpha_pll_config {
101 u32 l;
102 u32 alpha;
103 u32 alpha_hi;
104 u32 config_ctl_val;
105 u32 config_ctl_hi_val;
106 u32 config_ctl_hi1_val;
107 u32 user_ctl_val;
108 u32 user_ctl_hi_val;
109 u32 user_ctl_hi1_val;
110 u32 test_ctl_val;
111 u32 test_ctl_hi_val;
112 u32 test_ctl_hi1_val;
113 u32 main_output_mask;
114 u32 aux_output_mask;
115 u32 aux2_output_mask;
116 u32 early_output_mask;
117 u32 alpha_en_mask;
118 u32 alpha_mode_mask;
119 u32 pre_div_val;
120 u32 pre_div_mask;
121 u32 post_div_val;
122 u32 post_div_mask;
123 u32 vco_val;
124 u32 vco_mask;
125};
126
127extern const struct clk_ops clk_alpha_pll_ops;
128extern const struct clk_ops clk_alpha_pll_fixed_ops;
129extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
130extern const struct clk_ops clk_alpha_pll_postdiv_ops;
131extern const struct clk_ops clk_alpha_pll_huayra_ops;
132extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
133
134extern const struct clk_ops clk_alpha_pll_fabia_ops;
135extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
136extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
137
138extern const struct clk_ops clk_alpha_pll_trion_ops;
139extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
140extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
141
142extern const struct clk_ops clk_alpha_pll_lucid_ops;
143#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
144extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
145extern const struct clk_ops clk_alpha_pll_agera_ops;
146
147extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
148extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
149extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
150
151void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
152 const struct alpha_pll_config *config);
153void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
154 const struct alpha_pll_config *config);
155void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
156 const struct alpha_pll_config *config);
157void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
158 const struct alpha_pll_config *config);
159#define clk_lucid_pll_configure(pll, regmap, config) \
160 clk_trion_pll_configure(pll, regmap, config)
161
162
163
164#endif