tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier PCIe PHY
8
9description: |
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
12
13maintainers:
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15
16properties:
17 compatible:
18 enum:
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
21 - socionext,uniphier-pxs3-pcie-phy
22
23 reg:
24 maxItems: 1
25
26 "#phy-cells":
27 const: 0
28
29 clocks:
30 minItems: 1
31 maxItems: 2
32
33 clock-names:
34 oneOf:
35 - items: # for Pro5
36 - const: gio
37 - const: link
38 - const: link # for others
39
40 resets:
41 minItems: 1
42 maxItems: 2
43
44 reset-names:
45 oneOf:
46 - items: # for Pro5
47 - const: gio
48 - const: link
49 - const: link # for others
50
51 socionext,syscon:
52 $ref: /schemas/types.yaml#/definitions/phandle
53 description: A phandle to system control to set configurations for phy
54
55required:
56 - compatible
57 - reg
58 - "#phy-cells"
59 - clocks
60 - clock-names
61 - resets
62 - reset-names
63
64additionalProperties: false
65
66examples:
67 - |
68 pcie_phy: phy@66038000 {
69 compatible = "socionext,uniphier-ld20-pcie-phy";
70 reg = <0x66038000 0x4000>;
71 #phy-cells = <0>;
72 clock-names = "link";
73 clocks = <&sys_clk 24>;
74 reset-names = "link";
75 resets = <&sys_rst 24>;
76 socionext,syscon = <&soc_glue>;
77 };