tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2021 Linaro Ltd. */
4
5#include <linux/log2.h>
6
7#include "gsi.h"
8#include "ipa_data.h"
9#include "ipa_endpoint.h"
10#include "ipa_mem.h"
11
12/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.11 */
13enum ipa_resource_type {
14 /* Source resource types; first must have value 0 */
15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20
21 /* Destination resource types; first must have value 0 */
22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
23 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24};
25
26/* Resource groups used for an SoC having IPA v4.11 */
27enum ipa_rsrc_group_id {
28 /* Source resource group identifiers */
29 IPA_RSRC_GROUP_SRC_UL_DL = 0,
30 IPA_RSRC_GROUP_SRC_UC_RX_Q,
31 IPA_RSRC_GROUP_SRC_UNUSED_2,
32 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
33
34 /* Destination resource group identifiers */
35 IPA_RSRC_GROUP_DST_UL_DL_DPL = 0,
36 IPA_RSRC_GROUP_DST_UNUSED_1,
37 IPA_RSRC_GROUP_DST_DRB_IP,
38 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
39};
40
41/* QSB configuration data for an SoC having IPA v4.11 */
42static const struct ipa_qsb_data ipa_qsb_data[] = {
43 [IPA_QSB_MASTER_DDR] = {
44 .max_writes = 12,
45 .max_reads = 13,
46 .max_reads_beats = 120,
47 },
48};
49
50/* Endpoint configuration data for an SoC having IPA v4.11 */
51static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
52 [IPA_ENDPOINT_AP_COMMAND_TX] = {
53 .ee_id = GSI_EE_AP,
54 .channel_id = 5,
55 .endpoint_id = 7,
56 .toward_ipa = true,
57 .channel = {
58 .tre_count = 256,
59 .event_count = 256,
60 .tlv_count = 20,
61 },
62 .endpoint = {
63 .config = {
64 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
65 .dma_mode = true,
66 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
67 .tx = {
68 .seq_type = IPA_SEQ_DMA,
69 },
70 },
71 },
72 },
73 [IPA_ENDPOINT_AP_LAN_RX] = {
74 .ee_id = GSI_EE_AP,
75 .channel_id = 14,
76 .endpoint_id = 9,
77 .toward_ipa = false,
78 .channel = {
79 .tre_count = 256,
80 .event_count = 256,
81 .tlv_count = 9,
82 },
83 .endpoint = {
84 .config = {
85 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
86 .aggregation = true,
87 .status_enable = true,
88 .rx = {
89 .pad_align = ilog2(sizeof(u32)),
90 },
91 },
92 },
93 },
94 [IPA_ENDPOINT_AP_MODEM_TX] = {
95 .ee_id = GSI_EE_AP,
96 .channel_id = 2,
97 .endpoint_id = 2,
98 .toward_ipa = true,
99 .channel = {
100 .tre_count = 512,
101 .event_count = 512,
102 .tlv_count = 16,
103 },
104 .endpoint = {
105 .filter_support = true,
106 .config = {
107 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
108 .qmap = true,
109 .status_enable = true,
110 .tx = {
111 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
112 .status_endpoint =
113 IPA_ENDPOINT_MODEM_AP_RX,
114 },
115 },
116 },
117 },
118 [IPA_ENDPOINT_AP_MODEM_RX] = {
119 .ee_id = GSI_EE_AP,
120 .channel_id = 7,
121 .endpoint_id = 16,
122 .toward_ipa = false,
123 .channel = {
124 .tre_count = 256,
125 .event_count = 256,
126 .tlv_count = 9,
127 },
128 .endpoint = {
129 .config = {
130 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
131 .qmap = true,
132 .aggregation = true,
133 .rx = {
134 .aggr_close_eof = true,
135 },
136 },
137 },
138 },
139 [IPA_ENDPOINT_MODEM_AP_TX] = {
140 .ee_id = GSI_EE_MODEM,
141 .channel_id = 0,
142 .endpoint_id = 5,
143 .toward_ipa = true,
144 .endpoint = {
145 .filter_support = true,
146 },
147 },
148 [IPA_ENDPOINT_MODEM_AP_RX] = {
149 .ee_id = GSI_EE_MODEM,
150 .channel_id = 7,
151 .endpoint_id = 14,
152 .toward_ipa = false,
153 },
154 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
155 .ee_id = GSI_EE_MODEM,
156 .channel_id = 2,
157 .endpoint_id = 8,
158 .toward_ipa = true,
159 .endpoint = {
160 .filter_support = true,
161 },
162 },
163};
164
165/* Source resource configuration data for an SoC having IPA v4.11 */
166static const struct ipa_resource ipa_resource_src[] = {
167 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
168 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
169 .min = 6, .max = 6,
170 },
171 },
172 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
173 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
174 .min = 8, .max = 8,
175 },
176 },
177 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
178 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
179 .min = 18, .max = 18,
180 },
181 },
182 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
183 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
184 .min = 2, .max = 2,
185 },
186 },
187 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
188 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
189 .min = 15, .max = 15,
190 },
191 },
192};
193
194/* Destination resource configuration data for an SoC having IPA v4.11 */
195static const struct ipa_resource ipa_resource_dst[] = {
196 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
197 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
198 .min = 3, .max = 3,
199 },
200 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
201 .min = 25, .max = 25,
202 },
203 },
204 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
205 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
206 .min = 2, .max = 2,
207 },
208 },
209};
210
211/* Resource configuration data for an SoC having IPA v4.11 */
212static const struct ipa_resource_data ipa_resource_data = {
213 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
214 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
215 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
216 .resource_src = ipa_resource_src,
217 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
218 .resource_dst = ipa_resource_dst,
219};
220
221/* IPA-resident memory region data for an SoC having IPA v4.11 */
222static const struct ipa_mem ipa_mem_local_data[] = {
223 [IPA_MEM_UC_SHARED] = {
224 .offset = 0x0000,
225 .size = 0x0080,
226 .canary_count = 0,
227 },
228 [IPA_MEM_UC_INFO] = {
229 .offset = 0x0080,
230 .size = 0x0200,
231 .canary_count = 0,
232 },
233 [IPA_MEM_V4_FILTER_HASHED] = {
234 .offset = 0x0288,
235 .size = 0x0078,
236 .canary_count = 2,
237 },
238 [IPA_MEM_V4_FILTER] = {
239 .offset = 0x0308,
240 .size = 0x0078,
241 .canary_count = 2,
242 },
243 [IPA_MEM_V6_FILTER_HASHED] = {
244 .offset = 0x0388,
245 .size = 0x0078,
246 .canary_count = 2,
247 },
248 [IPA_MEM_V6_FILTER] = {
249 .offset = 0x0408,
250 .size = 0x0078,
251 .canary_count = 2,
252 },
253 [IPA_MEM_V4_ROUTE_HASHED] = {
254 .offset = 0x0488,
255 .size = 0x0078,
256 .canary_count = 2,
257 },
258 [IPA_MEM_V4_ROUTE] = {
259 .offset = 0x0508,
260 .size = 0x0078,
261 .canary_count = 2,
262 },
263 [IPA_MEM_V6_ROUTE_HASHED] = {
264 .offset = 0x0588,
265 .size = 0x0078,
266 .canary_count = 2,
267 },
268 [IPA_MEM_V6_ROUTE] = {
269 .offset = 0x0608,
270 .size = 0x0078,
271 .canary_count = 2,
272 },
273 [IPA_MEM_MODEM_HEADER] = {
274 .offset = 0x0688,
275 .size = 0x0240,
276 .canary_count = 2,
277 },
278 [IPA_MEM_AP_HEADER] = {
279 .offset = 0x08c8,
280 .size = 0x0200,
281 .canary_count = 0,
282 },
283 [IPA_MEM_MODEM_PROC_CTX] = {
284 .offset = 0x0ad0,
285 .size = 0x0200,
286 .canary_count = 2,
287 },
288 [IPA_MEM_AP_PROC_CTX] = {
289 .offset = 0x0cd0,
290 .size = 0x0200,
291 .canary_count = 0,
292 },
293 [IPA_MEM_NAT_TABLE] = {
294 .offset = 0x0ee0,
295 .size = 0x0d00,
296 .canary_count = 4,
297 },
298 [IPA_MEM_PDN_CONFIG] = {
299 .offset = 0x1be8,
300 .size = 0x0050,
301 .canary_count = 0,
302 },
303 [IPA_MEM_STATS_QUOTA_MODEM] = {
304 .offset = 0x1c40,
305 .size = 0x0030,
306 .canary_count = 4,
307 },
308 [IPA_MEM_STATS_QUOTA_AP] = {
309 .offset = 0x1c70,
310 .size = 0x0048,
311 .canary_count = 0,
312 },
313 [IPA_MEM_STATS_TETHERING] = {
314 .offset = 0x1cb8,
315 .size = 0x0238,
316 .canary_count = 0,
317 },
318 [IPA_MEM_STATS_DROP] = {
319 .offset = 0x1ef0,
320 .size = 0x0020,
321 .canary_count = 0,
322 },
323 [IPA_MEM_MODEM] = {
324 .offset = 0x1f18,
325 .size = 0x100c,
326 .canary_count = 2,
327 },
328 [IPA_MEM_UC_EVENT_RING] = {
329 .offset = 0x3000,
330 .size = 0x0000,
331 .canary_count = 1,
332 },
333};
334
335/* Memory configuration data for an SoC having IPA v4.11 */
336static const struct ipa_mem_data ipa_mem_data = {
337 .local_count = ARRAY_SIZE(ipa_mem_local_data),
338 .local = ipa_mem_local_data,
339 .imem_addr = 0x146a8000,
340 .imem_size = 0x00002000,
341 .smem_id = 497,
342 .smem_size = 0x00009000,
343};
344
345/* Interconnect rates are in 1000 byte/second units */
346static const struct ipa_interconnect_data ipa_interconnect_data[] = {
347 {
348 .name = "memory",
349 .peak_bandwidth = 465000, /* 465 MBps */
350 .average_bandwidth = 80000, /* 80 MBps */
351 },
352 /* Average rate is unused for the next two interconnects */
353 {
354 .name = "imem",
355 .peak_bandwidth = 68570, /* 68.57 MBps */
356 .average_bandwidth = 80000, /* 80 MBps (unused?) */
357 },
358 {
359 .name = "config",
360 .peak_bandwidth = 30000, /* 30 MBps */
361 .average_bandwidth = 0, /* unused */
362 },
363};
364
365/* Clock and interconnect configuration data for an SoC having IPA v4.11 */
366static const struct ipa_clock_data ipa_clock_data = {
367 .core_clock_rate = 60 * 1000 * 1000, /* Hz */
368 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
369 .interconnect_data = ipa_interconnect_data,
370};
371
372/* Configuration data for an SoC having IPA v4.11 */
373const struct ipa_data ipa_data_v4_11 = {
374 .version = IPA_VERSION_4_11,
375 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
376 .qsb_data = ipa_qsb_data,
377 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
378 .endpoint_data = ipa_gsi_endpoint_data,
379 .resource_data = &ipa_resource_data,
380 .mem_data = &ipa_mem_data,
381 .clock_data = &ipa_clock_data,
382};