tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/of.h>
7#include <linux/of_device.h>
8#include <linux/slab.h>
9
10#include <dt-bindings/memory/tegra124-mc.h>
11
12#include "mc.h"
13
14static const struct tegra_mc_client tegra124_mc_clients[] = {
15 {
16 .id = 0x00,
17 .name = "ptcr",
18 .swgroup = TEGRA_SWGROUP_PTC,
19 .la = {
20 .reg = 0x34c,
21 .shift = 0,
22 .mask = 0xff,
23 .def = 0x0,
24 },
25 }, {
26 .id = 0x01,
27 .name = "display0a",
28 .swgroup = TEGRA_SWGROUP_DC,
29 .smmu = {
30 .reg = 0x228,
31 .bit = 1,
32 },
33 .la = {
34 .reg = 0x2e8,
35 .shift = 0,
36 .mask = 0xff,
37 .def = 0xc2,
38 },
39 }, {
40 .id = 0x02,
41 .name = "display0ab",
42 .swgroup = TEGRA_SWGROUP_DCB,
43 .smmu = {
44 .reg = 0x228,
45 .bit = 2,
46 },
47 .la = {
48 .reg = 0x2f4,
49 .shift = 0,
50 .mask = 0xff,
51 .def = 0xc6,
52 },
53 }, {
54 .id = 0x03,
55 .name = "display0b",
56 .swgroup = TEGRA_SWGROUP_DC,
57 .smmu = {
58 .reg = 0x228,
59 .bit = 3,
60 },
61 .la = {
62 .reg = 0x2e8,
63 .shift = 16,
64 .mask = 0xff,
65 .def = 0x50,
66 },
67 }, {
68 .id = 0x04,
69 .name = "display0bb",
70 .swgroup = TEGRA_SWGROUP_DCB,
71 .smmu = {
72 .reg = 0x228,
73 .bit = 4,
74 },
75 .la = {
76 .reg = 0x2f4,
77 .shift = 16,
78 .mask = 0xff,
79 .def = 0x50,
80 },
81 }, {
82 .id = 0x05,
83 .name = "display0c",
84 .swgroup = TEGRA_SWGROUP_DC,
85 .smmu = {
86 .reg = 0x228,
87 .bit = 5,
88 },
89 .la = {
90 .reg = 0x2ec,
91 .shift = 0,
92 .mask = 0xff,
93 .def = 0x50,
94 },
95 }, {
96 .id = 0x06,
97 .name = "display0cb",
98 .swgroup = TEGRA_SWGROUP_DCB,
99 .smmu = {
100 .reg = 0x228,
101 .bit = 6,
102 },
103 .la = {
104 .reg = 0x2f8,
105 .shift = 0,
106 .mask = 0xff,
107 .def = 0x50,
108 },
109 }, {
110 .id = 0x0e,
111 .name = "afir",
112 .swgroup = TEGRA_SWGROUP_AFI,
113 .smmu = {
114 .reg = 0x228,
115 .bit = 14,
116 },
117 .la = {
118 .reg = 0x2e0,
119 .shift = 0,
120 .mask = 0xff,
121 .def = 0x13,
122 },
123 }, {
124 .id = 0x0f,
125 .name = "avpcarm7r",
126 .swgroup = TEGRA_SWGROUP_AVPC,
127 .smmu = {
128 .reg = 0x228,
129 .bit = 15,
130 },
131 .la = {
132 .reg = 0x2e4,
133 .shift = 0,
134 .mask = 0xff,
135 .def = 0x04,
136 },
137 }, {
138 .id = 0x10,
139 .name = "displayhc",
140 .swgroup = TEGRA_SWGROUP_DC,
141 .smmu = {
142 .reg = 0x228,
143 .bit = 16,
144 },
145 .la = {
146 .reg = 0x2f0,
147 .shift = 0,
148 .mask = 0xff,
149 .def = 0x50,
150 },
151 }, {
152 .id = 0x11,
153 .name = "displayhcb",
154 .swgroup = TEGRA_SWGROUP_DCB,
155 .smmu = {
156 .reg = 0x228,
157 .bit = 17,
158 },
159 .la = {
160 .reg = 0x2fc,
161 .shift = 0,
162 .mask = 0xff,
163 .def = 0x50,
164 },
165 }, {
166 .id = 0x15,
167 .name = "hdar",
168 .swgroup = TEGRA_SWGROUP_HDA,
169 .smmu = {
170 .reg = 0x228,
171 .bit = 21,
172 },
173 .la = {
174 .reg = 0x318,
175 .shift = 0,
176 .mask = 0xff,
177 .def = 0x24,
178 },
179 }, {
180 .id = 0x16,
181 .name = "host1xdmar",
182 .swgroup = TEGRA_SWGROUP_HC,
183 .smmu = {
184 .reg = 0x228,
185 .bit = 22,
186 },
187 .la = {
188 .reg = 0x310,
189 .shift = 0,
190 .mask = 0xff,
191 .def = 0x1e,
192 },
193 }, {
194 .id = 0x17,
195 .name = "host1xr",
196 .swgroup = TEGRA_SWGROUP_HC,
197 .smmu = {
198 .reg = 0x228,
199 .bit = 23,
200 },
201 .la = {
202 .reg = 0x310,
203 .shift = 16,
204 .mask = 0xff,
205 .def = 0x50,
206 },
207 }, {
208 .id = 0x1c,
209 .name = "msencsrd",
210 .swgroup = TEGRA_SWGROUP_MSENC,
211 .smmu = {
212 .reg = 0x228,
213 .bit = 28,
214 },
215 .la = {
216 .reg = 0x328,
217 .shift = 0,
218 .mask = 0xff,
219 .def = 0x23,
220 },
221 }, {
222 .id = 0x1d,
223 .name = "ppcsahbdmar",
224 .swgroup = TEGRA_SWGROUP_PPCS,
225 .smmu = {
226 .reg = 0x228,
227 .bit = 29,
228 },
229 .la = {
230 .reg = 0x344,
231 .shift = 0,
232 .mask = 0xff,
233 .def = 0x49,
234 },
235 }, {
236 .id = 0x1e,
237 .name = "ppcsahbslvr",
238 .swgroup = TEGRA_SWGROUP_PPCS,
239 .smmu = {
240 .reg = 0x228,
241 .bit = 30,
242 },
243 .la = {
244 .reg = 0x344,
245 .shift = 16,
246 .mask = 0xff,
247 .def = 0x1a,
248 },
249 }, {
250 .id = 0x1f,
251 .name = "satar",
252 .swgroup = TEGRA_SWGROUP_SATA,
253 .smmu = {
254 .reg = 0x228,
255 .bit = 31,
256 },
257 .la = {
258 .reg = 0x350,
259 .shift = 0,
260 .mask = 0xff,
261 .def = 0x65,
262 },
263 }, {
264 .id = 0x22,
265 .name = "vdebsevr",
266 .swgroup = TEGRA_SWGROUP_VDE,
267 .smmu = {
268 .reg = 0x22c,
269 .bit = 2,
270 },
271 .la = {
272 .reg = 0x354,
273 .shift = 0,
274 .mask = 0xff,
275 .def = 0x4f,
276 },
277 }, {
278 .id = 0x23,
279 .name = "vdember",
280 .swgroup = TEGRA_SWGROUP_VDE,
281 .smmu = {
282 .reg = 0x22c,
283 .bit = 3,
284 },
285 .la = {
286 .reg = 0x354,
287 .shift = 16,
288 .mask = 0xff,
289 .def = 0x3d,
290 },
291 }, {
292 .id = 0x24,
293 .name = "vdemcer",
294 .swgroup = TEGRA_SWGROUP_VDE,
295 .smmu = {
296 .reg = 0x22c,
297 .bit = 4,
298 },
299 .la = {
300 .reg = 0x358,
301 .shift = 0,
302 .mask = 0xff,
303 .def = 0x66,
304 },
305 }, {
306 .id = 0x25,
307 .name = "vdetper",
308 .swgroup = TEGRA_SWGROUP_VDE,
309 .smmu = {
310 .reg = 0x22c,
311 .bit = 5,
312 },
313 .la = {
314 .reg = 0x358,
315 .shift = 16,
316 .mask = 0xff,
317 .def = 0xa5,
318 },
319 }, {
320 .id = 0x26,
321 .name = "mpcorelpr",
322 .swgroup = TEGRA_SWGROUP_MPCORELP,
323 .la = {
324 .reg = 0x324,
325 .shift = 0,
326 .mask = 0xff,
327 .def = 0x04,
328 },
329 }, {
330 .id = 0x27,
331 .name = "mpcorer",
332 .swgroup = TEGRA_SWGROUP_MPCORE,
333 .la = {
334 .reg = 0x320,
335 .shift = 0,
336 .mask = 0xff,
337 .def = 0x04,
338 },
339 }, {
340 .id = 0x2b,
341 .name = "msencswr",
342 .swgroup = TEGRA_SWGROUP_MSENC,
343 .smmu = {
344 .reg = 0x22c,
345 .bit = 11,
346 },
347 .la = {
348 .reg = 0x328,
349 .shift = 16,
350 .mask = 0xff,
351 .def = 0x80,
352 },
353 }, {
354 .id = 0x31,
355 .name = "afiw",
356 .swgroup = TEGRA_SWGROUP_AFI,
357 .smmu = {
358 .reg = 0x22c,
359 .bit = 17,
360 },
361 .la = {
362 .reg = 0x2e0,
363 .shift = 16,
364 .mask = 0xff,
365 .def = 0x80,
366 },
367 }, {
368 .id = 0x32,
369 .name = "avpcarm7w",
370 .swgroup = TEGRA_SWGROUP_AVPC,
371 .smmu = {
372 .reg = 0x22c,
373 .bit = 18,
374 },
375 .la = {
376 .reg = 0x2e4,
377 .shift = 16,
378 .mask = 0xff,
379 .def = 0x80,
380 },
381 }, {
382 .id = 0x35,
383 .name = "hdaw",
384 .swgroup = TEGRA_SWGROUP_HDA,
385 .smmu = {
386 .reg = 0x22c,
387 .bit = 21,
388 },
389 .la = {
390 .reg = 0x318,
391 .shift = 16,
392 .mask = 0xff,
393 .def = 0x80,
394 },
395 }, {
396 .id = 0x36,
397 .name = "host1xw",
398 .swgroup = TEGRA_SWGROUP_HC,
399 .smmu = {
400 .reg = 0x22c,
401 .bit = 22,
402 },
403 .la = {
404 .reg = 0x314,
405 .shift = 0,
406 .mask = 0xff,
407 .def = 0x80,
408 },
409 }, {
410 .id = 0x38,
411 .name = "mpcorelpw",
412 .swgroup = TEGRA_SWGROUP_MPCORELP,
413 .la = {
414 .reg = 0x324,
415 .shift = 16,
416 .mask = 0xff,
417 .def = 0x80,
418 },
419 }, {
420 .id = 0x39,
421 .name = "mpcorew",
422 .swgroup = TEGRA_SWGROUP_MPCORE,
423 .la = {
424 .reg = 0x320,
425 .shift = 16,
426 .mask = 0xff,
427 .def = 0x80,
428 },
429 }, {
430 .id = 0x3b,
431 .name = "ppcsahbdmaw",
432 .swgroup = TEGRA_SWGROUP_PPCS,
433 .smmu = {
434 .reg = 0x22c,
435 .bit = 27,
436 },
437 .la = {
438 .reg = 0x348,
439 .shift = 0,
440 .mask = 0xff,
441 .def = 0x80,
442 },
443 }, {
444 .id = 0x3c,
445 .name = "ppcsahbslvw",
446 .swgroup = TEGRA_SWGROUP_PPCS,
447 .smmu = {
448 .reg = 0x22c,
449 .bit = 28,
450 },
451 .la = {
452 .reg = 0x348,
453 .shift = 16,
454 .mask = 0xff,
455 .def = 0x80,
456 },
457 }, {
458 .id = 0x3d,
459 .name = "sataw",
460 .swgroup = TEGRA_SWGROUP_SATA,
461 .smmu = {
462 .reg = 0x22c,
463 .bit = 29,
464 },
465 .la = {
466 .reg = 0x350,
467 .shift = 16,
468 .mask = 0xff,
469 .def = 0x65,
470 },
471 }, {
472 .id = 0x3e,
473 .name = "vdebsevw",
474 .swgroup = TEGRA_SWGROUP_VDE,
475 .smmu = {
476 .reg = 0x22c,
477 .bit = 30,
478 },
479 .la = {
480 .reg = 0x35c,
481 .shift = 0,
482 .mask = 0xff,
483 .def = 0x80,
484 },
485 }, {
486 .id = 0x3f,
487 .name = "vdedbgw",
488 .swgroup = TEGRA_SWGROUP_VDE,
489 .smmu = {
490 .reg = 0x22c,
491 .bit = 31,
492 },
493 .la = {
494 .reg = 0x35c,
495 .shift = 16,
496 .mask = 0xff,
497 .def = 0x80,
498 },
499 }, {
500 .id = 0x40,
501 .name = "vdembew",
502 .swgroup = TEGRA_SWGROUP_VDE,
503 .smmu = {
504 .reg = 0x230,
505 .bit = 0,
506 },
507 .la = {
508 .reg = 0x360,
509 .shift = 0,
510 .mask = 0xff,
511 .def = 0x80,
512 },
513 }, {
514 .id = 0x41,
515 .name = "vdetpmw",
516 .swgroup = TEGRA_SWGROUP_VDE,
517 .smmu = {
518 .reg = 0x230,
519 .bit = 1,
520 },
521 .la = {
522 .reg = 0x360,
523 .shift = 16,
524 .mask = 0xff,
525 .def = 0x80,
526 },
527 }, {
528 .id = 0x44,
529 .name = "ispra",
530 .swgroup = TEGRA_SWGROUP_ISP2,
531 .smmu = {
532 .reg = 0x230,
533 .bit = 4,
534 },
535 .la = {
536 .reg = 0x370,
537 .shift = 0,
538 .mask = 0xff,
539 .def = 0x18,
540 },
541 }, {
542 .id = 0x46,
543 .name = "ispwa",
544 .swgroup = TEGRA_SWGROUP_ISP2,
545 .smmu = {
546 .reg = 0x230,
547 .bit = 6,
548 },
549 .la = {
550 .reg = 0x374,
551 .shift = 0,
552 .mask = 0xff,
553 .def = 0x80,
554 },
555 }, {
556 .id = 0x47,
557 .name = "ispwb",
558 .swgroup = TEGRA_SWGROUP_ISP2,
559 .smmu = {
560 .reg = 0x230,
561 .bit = 7,
562 },
563 .la = {
564 .reg = 0x374,
565 .shift = 16,
566 .mask = 0xff,
567 .def = 0x80,
568 },
569 }, {
570 .id = 0x4a,
571 .name = "xusb_hostr",
572 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
573 .smmu = {
574 .reg = 0x230,
575 .bit = 10,
576 },
577 .la = {
578 .reg = 0x37c,
579 .shift = 0,
580 .mask = 0xff,
581 .def = 0x39,
582 },
583 }, {
584 .id = 0x4b,
585 .name = "xusb_hostw",
586 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
587 .smmu = {
588 .reg = 0x230,
589 .bit = 11,
590 },
591 .la = {
592 .reg = 0x37c,
593 .shift = 16,
594 .mask = 0xff,
595 .def = 0x80,
596 },
597 }, {
598 .id = 0x4c,
599 .name = "xusb_devr",
600 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
601 .smmu = {
602 .reg = 0x230,
603 .bit = 12,
604 },
605 .la = {
606 .reg = 0x380,
607 .shift = 0,
608 .mask = 0xff,
609 .def = 0x39,
610 },
611 }, {
612 .id = 0x4d,
613 .name = "xusb_devw",
614 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
615 .smmu = {
616 .reg = 0x230,
617 .bit = 13,
618 },
619 .la = {
620 .reg = 0x380,
621 .shift = 16,
622 .mask = 0xff,
623 .def = 0x80,
624 },
625 }, {
626 .id = 0x4e,
627 .name = "isprab",
628 .swgroup = TEGRA_SWGROUP_ISP2B,
629 .smmu = {
630 .reg = 0x230,
631 .bit = 14,
632 },
633 .la = {
634 .reg = 0x384,
635 .shift = 0,
636 .mask = 0xff,
637 .def = 0x18,
638 },
639 }, {
640 .id = 0x50,
641 .name = "ispwab",
642 .swgroup = TEGRA_SWGROUP_ISP2B,
643 .smmu = {
644 .reg = 0x230,
645 .bit = 16,
646 },
647 .la = {
648 .reg = 0x388,
649 .shift = 0,
650 .mask = 0xff,
651 .def = 0x80,
652 },
653 }, {
654 .id = 0x51,
655 .name = "ispwbb",
656 .swgroup = TEGRA_SWGROUP_ISP2B,
657 .smmu = {
658 .reg = 0x230,
659 .bit = 17,
660 },
661 .la = {
662 .reg = 0x388,
663 .shift = 16,
664 .mask = 0xff,
665 .def = 0x80,
666 },
667 }, {
668 .id = 0x54,
669 .name = "tsecsrd",
670 .swgroup = TEGRA_SWGROUP_TSEC,
671 .smmu = {
672 .reg = 0x230,
673 .bit = 20,
674 },
675 .la = {
676 .reg = 0x390,
677 .shift = 0,
678 .mask = 0xff,
679 .def = 0x9b,
680 },
681 }, {
682 .id = 0x55,
683 .name = "tsecswr",
684 .swgroup = TEGRA_SWGROUP_TSEC,
685 .smmu = {
686 .reg = 0x230,
687 .bit = 21,
688 },
689 .la = {
690 .reg = 0x390,
691 .shift = 16,
692 .mask = 0xff,
693 .def = 0x80,
694 },
695 }, {
696 .id = 0x56,
697 .name = "a9avpscr",
698 .swgroup = TEGRA_SWGROUP_A9AVP,
699 .smmu = {
700 .reg = 0x230,
701 .bit = 22,
702 },
703 .la = {
704 .reg = 0x3a4,
705 .shift = 0,
706 .mask = 0xff,
707 .def = 0x04,
708 },
709 }, {
710 .id = 0x57,
711 .name = "a9avpscw",
712 .swgroup = TEGRA_SWGROUP_A9AVP,
713 .smmu = {
714 .reg = 0x230,
715 .bit = 23,
716 },
717 .la = {
718 .reg = 0x3a4,
719 .shift = 16,
720 .mask = 0xff,
721 .def = 0x80,
722 },
723 }, {
724 .id = 0x58,
725 .name = "gpusrd",
726 .swgroup = TEGRA_SWGROUP_GPU,
727 .smmu = {
728 /* read-only */
729 .reg = 0x230,
730 .bit = 24,
731 },
732 .la = {
733 .reg = 0x3c8,
734 .shift = 0,
735 .mask = 0xff,
736 .def = 0x1a,
737 },
738 }, {
739 .id = 0x59,
740 .name = "gpuswr",
741 .swgroup = TEGRA_SWGROUP_GPU,
742 .smmu = {
743 /* read-only */
744 .reg = 0x230,
745 .bit = 25,
746 },
747 .la = {
748 .reg = 0x3c8,
749 .shift = 16,
750 .mask = 0xff,
751 .def = 0x80,
752 },
753 }, {
754 .id = 0x5a,
755 .name = "displayt",
756 .swgroup = TEGRA_SWGROUP_DC,
757 .smmu = {
758 .reg = 0x230,
759 .bit = 26,
760 },
761 .la = {
762 .reg = 0x2f0,
763 .shift = 16,
764 .mask = 0xff,
765 .def = 0x50,
766 },
767 }, {
768 .id = 0x60,
769 .name = "sdmmcra",
770 .swgroup = TEGRA_SWGROUP_SDMMC1A,
771 .smmu = {
772 .reg = 0x234,
773 .bit = 0,
774 },
775 .la = {
776 .reg = 0x3b8,
777 .shift = 0,
778 .mask = 0xff,
779 .def = 0x49,
780 },
781 }, {
782 .id = 0x61,
783 .name = "sdmmcraa",
784 .swgroup = TEGRA_SWGROUP_SDMMC2A,
785 .smmu = {
786 .reg = 0x234,
787 .bit = 1,
788 },
789 .la = {
790 .reg = 0x3bc,
791 .shift = 0,
792 .mask = 0xff,
793 .def = 0x49,
794 },
795 }, {
796 .id = 0x62,
797 .name = "sdmmcr",
798 .swgroup = TEGRA_SWGROUP_SDMMC3A,
799 .smmu = {
800 .reg = 0x234,
801 .bit = 2,
802 },
803 .la = {
804 .reg = 0x3c0,
805 .shift = 0,
806 .mask = 0xff,
807 .def = 0x49,
808 },
809 }, {
810 .id = 0x63,
811 .swgroup = TEGRA_SWGROUP_SDMMC4A,
812 .name = "sdmmcrab",
813 .smmu = {
814 .reg = 0x234,
815 .bit = 3,
816 },
817 .la = {
818 .reg = 0x3c4,
819 .shift = 0,
820 .mask = 0xff,
821 .def = 0x49,
822 },
823 }, {
824 .id = 0x64,
825 .name = "sdmmcwa",
826 .swgroup = TEGRA_SWGROUP_SDMMC1A,
827 .smmu = {
828 .reg = 0x234,
829 .bit = 4,
830 },
831 .la = {
832 .reg = 0x3b8,
833 .shift = 16,
834 .mask = 0xff,
835 .def = 0x80,
836 },
837 }, {
838 .id = 0x65,
839 .name = "sdmmcwaa",
840 .swgroup = TEGRA_SWGROUP_SDMMC2A,
841 .smmu = {
842 .reg = 0x234,
843 .bit = 5,
844 },
845 .la = {
846 .reg = 0x3bc,
847 .shift = 16,
848 .mask = 0xff,
849 .def = 0x80,
850 },
851 }, {
852 .id = 0x66,
853 .name = "sdmmcw",
854 .swgroup = TEGRA_SWGROUP_SDMMC3A,
855 .smmu = {
856 .reg = 0x234,
857 .bit = 6,
858 },
859 .la = {
860 .reg = 0x3c0,
861 .shift = 16,
862 .mask = 0xff,
863 .def = 0x80,
864 },
865 }, {
866 .id = 0x67,
867 .name = "sdmmcwab",
868 .swgroup = TEGRA_SWGROUP_SDMMC4A,
869 .smmu = {
870 .reg = 0x234,
871 .bit = 7,
872 },
873 .la = {
874 .reg = 0x3c4,
875 .shift = 16,
876 .mask = 0xff,
877 .def = 0x80,
878 },
879 }, {
880 .id = 0x6c,
881 .name = "vicsrd",
882 .swgroup = TEGRA_SWGROUP_VIC,
883 .smmu = {
884 .reg = 0x234,
885 .bit = 12,
886 },
887 .la = {
888 .reg = 0x394,
889 .shift = 0,
890 .mask = 0xff,
891 .def = 0x1a,
892 },
893 }, {
894 .id = 0x6d,
895 .name = "vicswr",
896 .swgroup = TEGRA_SWGROUP_VIC,
897 .smmu = {
898 .reg = 0x234,
899 .bit = 13,
900 },
901 .la = {
902 .reg = 0x394,
903 .shift = 16,
904 .mask = 0xff,
905 .def = 0x80,
906 },
907 }, {
908 .id = 0x72,
909 .name = "viw",
910 .swgroup = TEGRA_SWGROUP_VI,
911 .smmu = {
912 .reg = 0x234,
913 .bit = 18,
914 },
915 .la = {
916 .reg = 0x398,
917 .shift = 0,
918 .mask = 0xff,
919 .def = 0x80,
920 },
921 }, {
922 .id = 0x73,
923 .name = "displayd",
924 .swgroup = TEGRA_SWGROUP_DC,
925 .smmu = {
926 .reg = 0x234,
927 .bit = 19,
928 },
929 .la = {
930 .reg = 0x3c8,
931 .shift = 0,
932 .mask = 0xff,
933 .def = 0x50,
934 },
935 },
936};
937
938static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
939 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
940 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
941 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
942 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
943 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
944 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
945 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
946 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
947 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
948 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
949 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
950 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
951 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
952 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
953 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
954 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
955 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
956 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
957 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
958 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
959 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
960 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
961 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
962};
963
964static const unsigned int tegra124_group_drm[] = {
965 TEGRA_SWGROUP_DC,
966 TEGRA_SWGROUP_DCB,
967 TEGRA_SWGROUP_VIC,
968};
969
970static const struct tegra_smmu_group_soc tegra124_groups[] = {
971 {
972 .name = "drm",
973 .swgroups = tegra124_group_drm,
974 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
975 },
976};
977
978#define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
979 { \
980 .name = #_name, \
981 .id = TEGRA124_MC_RESET_##_name, \
982 .control = _control, \
983 .status = _status, \
984 .bit = _bit, \
985 }
986
987static const struct tegra_mc_reset tegra124_mc_resets[] = {
988 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
989 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
990 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
991 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
992 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
993 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
994 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
995 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
996 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
997 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
998 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
999 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1000 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1001 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1002 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1003 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1004 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1005 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1006 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1007 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1008 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1009 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1010 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1011 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1012};
1013
1014static int tegra124_mc_icc_set(struct icc_node *src, struct icc_node *dst)
1015{
1016 /* TODO: program PTSA */
1017 return 0;
1018}
1019
1020static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
1021 u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
1022{
1023 /*
1024 * ISO clients need to reserve extra bandwidth up-front because
1025 * there could be high bandwidth pressure during initial filling
1026 * of the client's FIFO buffers. Secondly, we need to take into
1027 * account impurities of the memory subsystem.
1028 */
1029 if (tag & TEGRA_MC_ICC_TAG_ISO)
1030 peak_bw = tegra_mc_scale_percents(peak_bw, 400);
1031
1032 *agg_avg += avg_bw;
1033 *agg_peak = max(*agg_peak, peak_bw);
1034
1035 return 0;
1036}
1037
1038static struct icc_node_data *
1039tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1040{
1041 struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1042 const struct tegra_mc_client *client;
1043 unsigned int i, idx = spec->args[0];
1044 struct icc_node_data *ndata;
1045 struct icc_node *node;
1046
1047 list_for_each_entry(node, &mc->provider.nodes, node_list) {
1048 if (node->id != idx)
1049 continue;
1050
1051 ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
1052 if (!ndata)
1053 return ERR_PTR(-ENOMEM);
1054
1055 client = &mc->soc->clients[idx];
1056 ndata->node = node;
1057
1058 switch (client->swgroup) {
1059 case TEGRA_SWGROUP_DC:
1060 case TEGRA_SWGROUP_DCB:
1061 case TEGRA_SWGROUP_PTC:
1062 case TEGRA_SWGROUP_VI:
1063 /* these clients are isochronous by default */
1064 ndata->tag = TEGRA_MC_ICC_TAG_ISO;
1065 break;
1066
1067 default:
1068 ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
1069 break;
1070 }
1071
1072 return ndata;
1073 }
1074
1075 for (i = 0; i < mc->soc->num_clients; i++) {
1076 if (mc->soc->clients[i].id == idx)
1077 return ERR_PTR(-EPROBE_DEFER);
1078 }
1079
1080 dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
1081
1082 return ERR_PTR(-EINVAL);
1083}
1084
1085static const struct tegra_mc_icc_ops tegra124_mc_icc_ops = {
1086 .xlate_extended = tegra124_mc_of_icc_xlate_extended,
1087 .aggregate = tegra124_mc_icc_aggreate,
1088 .set = tegra124_mc_icc_set,
1089};
1090
1091#ifdef CONFIG_ARCH_TEGRA_124_SOC
1092static const unsigned long tegra124_mc_emem_regs[] = {
1093 MC_EMEM_ARB_CFG,
1094 MC_EMEM_ARB_OUTSTANDING_REQ,
1095 MC_EMEM_ARB_TIMING_RCD,
1096 MC_EMEM_ARB_TIMING_RP,
1097 MC_EMEM_ARB_TIMING_RC,
1098 MC_EMEM_ARB_TIMING_RAS,
1099 MC_EMEM_ARB_TIMING_FAW,
1100 MC_EMEM_ARB_TIMING_RRD,
1101 MC_EMEM_ARB_TIMING_RAP2PRE,
1102 MC_EMEM_ARB_TIMING_WAP2PRE,
1103 MC_EMEM_ARB_TIMING_R2R,
1104 MC_EMEM_ARB_TIMING_W2W,
1105 MC_EMEM_ARB_TIMING_R2W,
1106 MC_EMEM_ARB_TIMING_W2R,
1107 MC_EMEM_ARB_DA_TURNS,
1108 MC_EMEM_ARB_DA_COVERS,
1109 MC_EMEM_ARB_MISC0,
1110 MC_EMEM_ARB_MISC1,
1111 MC_EMEM_ARB_RING1_THROTTLE
1112};
1113
1114static const struct tegra_smmu_soc tegra124_smmu_soc = {
1115 .clients = tegra124_mc_clients,
1116 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1117 .swgroups = tegra124_swgroups,
1118 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1119 .groups = tegra124_groups,
1120 .num_groups = ARRAY_SIZE(tegra124_groups),
1121 .supports_round_robin_arbitration = true,
1122 .supports_request_limit = true,
1123 .num_tlb_lines = 32,
1124 .num_asids = 128,
1125};
1126
1127const struct tegra_mc_soc tegra124_mc_soc = {
1128 .clients = tegra124_mc_clients,
1129 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1130 .num_address_bits = 34,
1131 .atom_size = 32,
1132 .client_id_mask = 0x7f,
1133 .smmu = &tegra124_smmu_soc,
1134 .emem_regs = tegra124_mc_emem_regs,
1135 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1136 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1137 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1138 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1139 .reset_ops = &tegra_mc_reset_ops_common,
1140 .resets = tegra124_mc_resets,
1141 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1142 .icc_ops = &tegra124_mc_icc_ops,
1143};
1144#endif /* CONFIG_ARCH_TEGRA_124_SOC */
1145
1146#ifdef CONFIG_ARCH_TEGRA_132_SOC
1147static const struct tegra_smmu_soc tegra132_smmu_soc = {
1148 .clients = tegra124_mc_clients,
1149 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1150 .swgroups = tegra124_swgroups,
1151 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1152 .groups = tegra124_groups,
1153 .num_groups = ARRAY_SIZE(tegra124_groups),
1154 .supports_round_robin_arbitration = true,
1155 .supports_request_limit = true,
1156 .num_tlb_lines = 32,
1157 .num_asids = 128,
1158};
1159
1160const struct tegra_mc_soc tegra132_mc_soc = {
1161 .clients = tegra124_mc_clients,
1162 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1163 .num_address_bits = 34,
1164 .atom_size = 32,
1165 .client_id_mask = 0x7f,
1166 .smmu = &tegra132_smmu_soc,
1167 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1168 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1169 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1170 .reset_ops = &tegra_mc_reset_ops_common,
1171 .resets = tegra124_mc_resets,
1172 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1173 .icc_ops = &tegra124_mc_icc_ops,
1174};
1175#endif /* CONFIG_ARCH_TEGRA_132_SOC */