tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/amdgpu_drm.h>
29
30#include "amdgpu.h"
31#include "amdgpu_atombios.h"
32#include "amdgpu_ih.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "amdgpu_ucode.h"
36#include "amdgpu_psp.h"
37#include "atom.h"
38#include "amd_pcie.h"
39
40#include "gc/gc_10_1_0_offset.h"
41#include "gc/gc_10_1_0_sh_mask.h"
42#include "mp/mp_11_0_offset.h"
43
44#include "soc15.h"
45#include "soc15_common.h"
46#include "gmc_v10_0.h"
47#include "gfxhub_v2_0.h"
48#include "mmhub_v2_0.h"
49#include "nbio_v2_3.h"
50#include "nbio_v7_2.h"
51#include "hdp_v5_0.h"
52#include "nv.h"
53#include "navi10_ih.h"
54#include "gfx_v10_0.h"
55#include "sdma_v5_0.h"
56#include "sdma_v5_2.h"
57#include "vcn_v2_0.h"
58#include "jpeg_v2_0.h"
59#include "vcn_v3_0.h"
60#include "jpeg_v3_0.h"
61#include "dce_virtual.h"
62#include "mes_v10_1.h"
63#include "mxgpu_nv.h"
64#include "smuio_v11_0.h"
65#include "smuio_v11_0_6.h"
66
67static const struct amd_ip_funcs nv_common_ip_funcs;
68
69/* Navi */
70static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
71{
72 {
73 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
74 .max_width = 4096,
75 .max_height = 2304,
76 .max_pixels_per_frame = 4096 * 2304,
77 .max_level = 0,
78 },
79 {
80 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
81 .max_width = 4096,
82 .max_height = 2304,
83 .max_pixels_per_frame = 4096 * 2304,
84 .max_level = 0,
85 },
86};
87
88static const struct amdgpu_video_codecs nv_video_codecs_encode =
89{
90 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
91 .codec_array = nv_video_codecs_encode_array,
92};
93
94/* Navi1x */
95static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
96{
97 {
98 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
99 .max_width = 4096,
100 .max_height = 4096,
101 .max_pixels_per_frame = 4096 * 4096,
102 .max_level = 3,
103 },
104 {
105 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
106 .max_width = 4096,
107 .max_height = 4096,
108 .max_pixels_per_frame = 4096 * 4096,
109 .max_level = 5,
110 },
111 {
112 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
113 .max_width = 4096,
114 .max_height = 4096,
115 .max_pixels_per_frame = 4096 * 4096,
116 .max_level = 52,
117 },
118 {
119 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
120 .max_width = 4096,
121 .max_height = 4096,
122 .max_pixels_per_frame = 4096 * 4096,
123 .max_level = 4,
124 },
125 {
126 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
127 .max_width = 8192,
128 .max_height = 4352,
129 .max_pixels_per_frame = 8192 * 4352,
130 .max_level = 186,
131 },
132 {
133 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
134 .max_width = 4096,
135 .max_height = 4096,
136 .max_pixels_per_frame = 4096 * 4096,
137 .max_level = 0,
138 },
139 {
140 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
141 .max_width = 8192,
142 .max_height = 4352,
143 .max_pixels_per_frame = 8192 * 4352,
144 .max_level = 0,
145 },
146};
147
148static const struct amdgpu_video_codecs nv_video_codecs_decode =
149{
150 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
151 .codec_array = nv_video_codecs_decode_array,
152};
153
154/* Sienna Cichlid */
155static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
156{
157 {
158 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
159 .max_width = 4096,
160 .max_height = 4096,
161 .max_pixels_per_frame = 4096 * 4096,
162 .max_level = 3,
163 },
164 {
165 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
166 .max_width = 4096,
167 .max_height = 4096,
168 .max_pixels_per_frame = 4096 * 4096,
169 .max_level = 5,
170 },
171 {
172 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
173 .max_width = 4096,
174 .max_height = 4096,
175 .max_pixels_per_frame = 4096 * 4096,
176 .max_level = 52,
177 },
178 {
179 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
180 .max_width = 4096,
181 .max_height = 4096,
182 .max_pixels_per_frame = 4096 * 4096,
183 .max_level = 4,
184 },
185 {
186 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
187 .max_width = 8192,
188 .max_height = 4352,
189 .max_pixels_per_frame = 8192 * 4352,
190 .max_level = 186,
191 },
192 {
193 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
194 .max_width = 4096,
195 .max_height = 4096,
196 .max_pixels_per_frame = 4096 * 4096,
197 .max_level = 0,
198 },
199 {
200 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
201 .max_width = 8192,
202 .max_height = 4352,
203 .max_pixels_per_frame = 8192 * 4352,
204 .max_level = 0,
205 },
206 {
207 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
208 .max_width = 8192,
209 .max_height = 4352,
210 .max_pixels_per_frame = 8192 * 4352,
211 .max_level = 0,
212 },
213};
214
215static const struct amdgpu_video_codecs sc_video_codecs_decode =
216{
217 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
218 .codec_array = sc_video_codecs_decode_array,
219};
220
221static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
222 const struct amdgpu_video_codecs **codecs)
223{
224 switch (adev->asic_type) {
225 case CHIP_SIENNA_CICHLID:
226 case CHIP_NAVY_FLOUNDER:
227 case CHIP_DIMGREY_CAVEFISH:
228 case CHIP_VANGOGH:
229 if (encode)
230 *codecs = &nv_video_codecs_encode;
231 else
232 *codecs = &sc_video_codecs_decode;
233 return 0;
234 case CHIP_NAVI10:
235 case CHIP_NAVI14:
236 case CHIP_NAVI12:
237 if (encode)
238 *codecs = &nv_video_codecs_encode;
239 else
240 *codecs = &nv_video_codecs_decode;
241 return 0;
242 default:
243 return -EINVAL;
244 }
245}
246
247/*
248 * Indirect registers accessor
249 */
250static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
251{
252 unsigned long address, data;
253 address = adev->nbio.funcs->get_pcie_index_offset(adev);
254 data = adev->nbio.funcs->get_pcie_data_offset(adev);
255
256 return amdgpu_device_indirect_rreg(adev, address, data, reg);
257}
258
259static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
260{
261 unsigned long address, data;
262
263 address = adev->nbio.funcs->get_pcie_index_offset(adev);
264 data = adev->nbio.funcs->get_pcie_data_offset(adev);
265
266 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
267}
268
269static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
270{
271 unsigned long address, data;
272 address = adev->nbio.funcs->get_pcie_index_offset(adev);
273 data = adev->nbio.funcs->get_pcie_data_offset(adev);
274
275 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
276}
277
278static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
279{
280 unsigned long flags, address, data;
281 u32 r;
282 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
283 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
284
285 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
286 WREG32(address, reg * 4);
287 (void)RREG32(address);
288 r = RREG32(data);
289 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
290 return r;
291}
292
293static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
294{
295 unsigned long address, data;
296
297 address = adev->nbio.funcs->get_pcie_index_offset(adev);
298 data = adev->nbio.funcs->get_pcie_data_offset(adev);
299
300 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
301}
302
303static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
304{
305 unsigned long flags, address, data;
306
307 address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
308 data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
309
310 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
311 WREG32(address, reg * 4);
312 (void)RREG32(address);
313 WREG32(data, v);
314 (void)RREG32(data);
315 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
316}
317
318static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
319{
320 unsigned long flags, address, data;
321 u32 r;
322
323 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
324 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
325
326 spin_lock_irqsave(&adev->didt_idx_lock, flags);
327 WREG32(address, (reg));
328 r = RREG32(data);
329 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
330 return r;
331}
332
333static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
334{
335 unsigned long flags, address, data;
336
337 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
338 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
339
340 spin_lock_irqsave(&adev->didt_idx_lock, flags);
341 WREG32(address, (reg));
342 WREG32(data, (v));
343 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
344}
345
346static u32 nv_get_config_memsize(struct amdgpu_device *adev)
347{
348 return adev->nbio.funcs->get_memsize(adev);
349}
350
351static u32 nv_get_xclk(struct amdgpu_device *adev)
352{
353 return adev->clock.spll.reference_freq;
354}
355
356
357void nv_grbm_select(struct amdgpu_device *adev,
358 u32 me, u32 pipe, u32 queue, u32 vmid)
359{
360 u32 grbm_gfx_cntl = 0;
361 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
362 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
363 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
364 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
365
366 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
367}
368
369static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
370{
371 /* todo */
372}
373
374static bool nv_read_disabled_bios(struct amdgpu_device *adev)
375{
376 /* todo */
377 return false;
378}
379
380static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
381 u8 *bios, u32 length_bytes)
382{
383 u32 *dw_ptr;
384 u32 i, length_dw;
385 u32 rom_index_offset, rom_data_offset;
386
387 if (bios == NULL)
388 return false;
389 if (length_bytes == 0)
390 return false;
391 /* APU vbios image is part of sbios image */
392 if (adev->flags & AMD_IS_APU)
393 return false;
394
395 dw_ptr = (u32 *)bios;
396 length_dw = ALIGN(length_bytes, 4) / 4;
397
398 rom_index_offset =
399 adev->smuio.funcs->get_rom_index_offset(adev);
400 rom_data_offset =
401 adev->smuio.funcs->get_rom_data_offset(adev);
402
403 /* set rom index to 0 */
404 WREG32(rom_index_offset, 0);
405 /* read out the rom data */
406 for (i = 0; i < length_dw; i++)
407 dw_ptr[i] = RREG32(rom_data_offset);
408
409 return true;
410}
411
412static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
413 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
414 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
415 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
416 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
417 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
418 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
419 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
420 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
421 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
422 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
423 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
424 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
425 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
426 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
427 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
428 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
429 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
430 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
431 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
432};
433
434static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
435 u32 sh_num, u32 reg_offset)
436{
437 uint32_t val;
438
439 mutex_lock(&adev->grbm_idx_mutex);
440 if (se_num != 0xffffffff || sh_num != 0xffffffff)
441 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
442
443 val = RREG32(reg_offset);
444
445 if (se_num != 0xffffffff || sh_num != 0xffffffff)
446 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
447 mutex_unlock(&adev->grbm_idx_mutex);
448 return val;
449}
450
451static uint32_t nv_get_register_value(struct amdgpu_device *adev,
452 bool indexed, u32 se_num,
453 u32 sh_num, u32 reg_offset)
454{
455 if (indexed) {
456 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
457 } else {
458 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
459 return adev->gfx.config.gb_addr_config;
460 return RREG32(reg_offset);
461 }
462}
463
464static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
465 u32 sh_num, u32 reg_offset, u32 *value)
466{
467 uint32_t i;
468 struct soc15_allowed_register_entry *en;
469
470 *value = 0;
471 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
472 en = &nv_allowed_read_registers[i];
473 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
474 reg_offset !=
475 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
476 continue;
477
478 *value = nv_get_register_value(adev,
479 nv_allowed_read_registers[i].grbm_indexed,
480 se_num, sh_num, reg_offset);
481 return 0;
482 }
483 return -EINVAL;
484}
485
486static int nv_asic_mode2_reset(struct amdgpu_device *adev)
487{
488 u32 i;
489 int ret = 0;
490
491 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
492
493 /* disable BM */
494 pci_clear_master(adev->pdev);
495
496 amdgpu_device_cache_pci_state(adev->pdev);
497
498 ret = amdgpu_dpm_mode2_reset(adev);
499 if (ret)
500 dev_err(adev->dev, "GPU mode2 reset failed\n");
501
502 amdgpu_device_load_pci_state(adev->pdev);
503
504 /* wait for asic to come out of reset */
505 for (i = 0; i < adev->usec_timeout; i++) {
506 u32 memsize = adev->nbio.funcs->get_memsize(adev);
507
508 if (memsize != 0xffffffff)
509 break;
510 udelay(1);
511 }
512
513 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
514
515 return ret;
516}
517
518static enum amd_reset_method
519nv_asic_reset_method(struct amdgpu_device *adev)
520{
521 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
522 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
523 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
524 amdgpu_reset_method == AMD_RESET_METHOD_PCI)
525 return amdgpu_reset_method;
526
527 if (amdgpu_reset_method != -1)
528 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
529 amdgpu_reset_method);
530
531 switch (adev->asic_type) {
532 case CHIP_VANGOGH:
533 return AMD_RESET_METHOD_MODE2;
534 case CHIP_SIENNA_CICHLID:
535 case CHIP_NAVY_FLOUNDER:
536 case CHIP_DIMGREY_CAVEFISH:
537 return AMD_RESET_METHOD_MODE1;
538 default:
539 if (amdgpu_dpm_is_baco_supported(adev))
540 return AMD_RESET_METHOD_BACO;
541 else
542 return AMD_RESET_METHOD_MODE1;
543 }
544}
545
546static int nv_asic_reset(struct amdgpu_device *adev)
547{
548 int ret = 0;
549
550 switch (nv_asic_reset_method(adev)) {
551 case AMD_RESET_METHOD_PCI:
552 dev_info(adev->dev, "PCI reset\n");
553 ret = amdgpu_device_pci_reset(adev);
554 break;
555 case AMD_RESET_METHOD_BACO:
556 dev_info(adev->dev, "BACO reset\n");
557 ret = amdgpu_dpm_baco_reset(adev);
558 break;
559 case AMD_RESET_METHOD_MODE2:
560 dev_info(adev->dev, "MODE2 reset\n");
561 ret = nv_asic_mode2_reset(adev);
562 break;
563 default:
564 dev_info(adev->dev, "MODE1 reset\n");
565 ret = amdgpu_device_mode1_reset(adev);
566 break;
567 }
568
569 return ret;
570}
571
572static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
573{
574 /* todo */
575 return 0;
576}
577
578static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
579{
580 /* todo */
581 return 0;
582}
583
584static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
585{
586 if (pci_is_root_bus(adev->pdev->bus))
587 return;
588
589 if (amdgpu_pcie_gen2 == 0)
590 return;
591
592 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
593 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
594 return;
595
596 /* todo */
597}
598
599static void nv_program_aspm(struct amdgpu_device *adev)
600{
601 if (amdgpu_aspm != 1)
602 return;
603
604 if (!(adev->flags & AMD_IS_APU) &&
605 (adev->nbio.funcs->program_aspm))
606 adev->nbio.funcs->program_aspm(adev);
607
608}
609
610static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
611 bool enable)
612{
613 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
614 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
615}
616
617static const struct amdgpu_ip_block_version nv_common_ip_block =
618{
619 .type = AMD_IP_BLOCK_TYPE_COMMON,
620 .major = 1,
621 .minor = 0,
622 .rev = 0,
623 .funcs = &nv_common_ip_funcs,
624};
625
626static bool nv_is_headless_sku(struct pci_dev *pdev)
627{
628 if ((pdev->device == 0x731E &&
629 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
630 (pdev->device == 0x7340 && pdev->revision == 0xC9) ||
631 (pdev->device == 0x7360 && pdev->revision == 0xC7))
632 return true;
633 return false;
634}
635
636static int nv_reg_base_init(struct amdgpu_device *adev)
637{
638 int r;
639
640 if (amdgpu_discovery) {
641 r = amdgpu_discovery_reg_base_init(adev);
642 if (r) {
643 DRM_WARN("failed to init reg base from ip discovery table, "
644 "fallback to legacy init method\n");
645 goto legacy_init;
646 }
647
648 amdgpu_discovery_harvest_ip(adev);
649 if (nv_is_headless_sku(adev->pdev)) {
650 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
651 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
652 }
653
654 return 0;
655 }
656
657legacy_init:
658 switch (adev->asic_type) {
659 case CHIP_NAVI10:
660 navi10_reg_base_init(adev);
661 break;
662 case CHIP_NAVI14:
663 navi14_reg_base_init(adev);
664 break;
665 case CHIP_NAVI12:
666 navi12_reg_base_init(adev);
667 break;
668 case CHIP_SIENNA_CICHLID:
669 case CHIP_NAVY_FLOUNDER:
670 sienna_cichlid_reg_base_init(adev);
671 break;
672 case CHIP_VANGOGH:
673 vangogh_reg_base_init(adev);
674 break;
675 case CHIP_DIMGREY_CAVEFISH:
676 dimgrey_cavefish_reg_base_init(adev);
677 break;
678 default:
679 return -EINVAL;
680 }
681
682 return 0;
683}
684
685void nv_set_virt_ops(struct amdgpu_device *adev)
686{
687 adev->virt.ops = &xgpu_nv_virt_ops;
688}
689
690int nv_set_ip_blocks(struct amdgpu_device *adev)
691{
692 int r;
693
694 if (adev->flags & AMD_IS_APU) {
695 adev->nbio.funcs = &nbio_v7_2_funcs;
696 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
697 } else {
698 adev->nbio.funcs = &nbio_v2_3_funcs;
699 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
700 }
701 adev->hdp.funcs = &hdp_v5_0_funcs;
702
703 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
704 adev->smuio.funcs = &smuio_v11_0_6_funcs;
705 else
706 adev->smuio.funcs = &smuio_v11_0_funcs;
707
708 if (adev->asic_type == CHIP_SIENNA_CICHLID)
709 adev->gmc.xgmi.supported = true;
710
711 /* Set IP register base before any HW register access */
712 r = nv_reg_base_init(adev);
713 if (r)
714 return r;
715
716 switch (adev->asic_type) {
717 case CHIP_NAVI10:
718 case CHIP_NAVI14:
719 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
720 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
721 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
722 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
723 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
724 !amdgpu_sriov_vf(adev))
725 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
726 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
727 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
728#if defined(CONFIG_DRM_AMD_DC)
729 else if (amdgpu_device_has_dc_support(adev))
730 amdgpu_device_ip_block_add(adev, &dm_ip_block);
731#endif
732 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
733 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
734 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
735 !amdgpu_sriov_vf(adev))
736 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
737 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
738 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
739 if (adev->enable_mes)
740 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
741 break;
742 case CHIP_NAVI12:
743 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
744 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
745 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
746 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
747 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
748 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
749 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
750 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
751#if defined(CONFIG_DRM_AMD_DC)
752 else if (amdgpu_device_has_dc_support(adev))
753 amdgpu_device_ip_block_add(adev, &dm_ip_block);
754#endif
755 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
756 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
757 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
758 !amdgpu_sriov_vf(adev))
759 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
760 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
761 if (!amdgpu_sriov_vf(adev))
762 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
763 break;
764 case CHIP_SIENNA_CICHLID:
765 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
766 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
767 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
768 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
769 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
770 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
771 is_support_sw_smu(adev))
772 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
773 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
774 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
775#if defined(CONFIG_DRM_AMD_DC)
776 else if (amdgpu_device_has_dc_support(adev))
777 amdgpu_device_ip_block_add(adev, &dm_ip_block);
778#endif
779 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
780 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
781 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
782 if (!amdgpu_sriov_vf(adev))
783 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
784 if (adev->enable_mes)
785 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
786 break;
787 case CHIP_NAVY_FLOUNDER:
788 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
789 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
790 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
791 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
792 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
793 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
794 is_support_sw_smu(adev))
795 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
796 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
797 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
798#if defined(CONFIG_DRM_AMD_DC)
799 else if (amdgpu_device_has_dc_support(adev))
800 amdgpu_device_ip_block_add(adev, &dm_ip_block);
801#endif
802 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
803 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
804 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
805 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
806 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
807 is_support_sw_smu(adev))
808 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
809 break;
810 case CHIP_VANGOGH:
811 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
812 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
813 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
814 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
815 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
816 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
817 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
818 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
819#if defined(CONFIG_DRM_AMD_DC)
820 else if (amdgpu_device_has_dc_support(adev))
821 amdgpu_device_ip_block_add(adev, &dm_ip_block);
822#endif
823 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
824 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
825 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
826 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
827 break;
828 case CHIP_DIMGREY_CAVEFISH:
829 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
830 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
831 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
832 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
833 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
834 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
835 is_support_sw_smu(adev))
836 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
837 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
838 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
839#if defined(CONFIG_DRM_AMD_DC)
840 else if (amdgpu_device_has_dc_support(adev))
841 amdgpu_device_ip_block_add(adev, &dm_ip_block);
842#endif
843 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
844 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
845 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
846 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
847 break;
848 default:
849 return -EINVAL;
850 }
851
852 return 0;
853}
854
855static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
856{
857 return adev->nbio.funcs->get_rev_id(adev);
858}
859
860static bool nv_need_full_reset(struct amdgpu_device *adev)
861{
862 return true;
863}
864
865static bool nv_need_reset_on_init(struct amdgpu_device *adev)
866{
867 u32 sol_reg;
868
869 if (adev->flags & AMD_IS_APU)
870 return false;
871
872 /* Check sOS sign of life register to confirm sys driver and sOS
873 * are already been loaded.
874 */
875 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
876 if (sol_reg)
877 return true;
878
879 return false;
880}
881
882static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
883{
884
885 /* TODO
886 * dummy implement for pcie_replay_count sysfs interface
887 * */
888
889 return 0;
890}
891
892static void nv_init_doorbell_index(struct amdgpu_device *adev)
893{
894 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
895 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
896 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
897 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
898 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
899 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
900 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
901 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
902 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
903 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
904 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
905 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
906 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
907 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
908 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
909 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
910 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
911 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
912 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
913 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
914 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
915 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
916 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
917 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
918 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
919
920 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
921 adev->doorbell_index.sdma_doorbell_range = 20;
922}
923
924static void nv_pre_asic_init(struct amdgpu_device *adev)
925{
926}
927
928static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
929 bool enter)
930{
931 if (enter)
932 amdgpu_gfx_rlc_enter_safe_mode(adev);
933 else
934 amdgpu_gfx_rlc_exit_safe_mode(adev);
935
936 if (adev->gfx.funcs->update_perfmon_mgcg)
937 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
938
939 if (!(adev->flags & AMD_IS_APU) &&
940 (adev->nbio.funcs->enable_aspm))
941 adev->nbio.funcs->enable_aspm(adev, !enter);
942
943 return 0;
944}
945
946static const struct amdgpu_asic_funcs nv_asic_funcs =
947{
948 .read_disabled_bios = &nv_read_disabled_bios,
949 .read_bios_from_rom = &nv_read_bios_from_rom,
950 .read_register = &nv_read_register,
951 .reset = &nv_asic_reset,
952 .reset_method = &nv_asic_reset_method,
953 .set_vga_state = &nv_vga_set_state,
954 .get_xclk = &nv_get_xclk,
955 .set_uvd_clocks = &nv_set_uvd_clocks,
956 .set_vce_clocks = &nv_set_vce_clocks,
957 .get_config_memsize = &nv_get_config_memsize,
958 .init_doorbell_index = &nv_init_doorbell_index,
959 .need_full_reset = &nv_need_full_reset,
960 .need_reset_on_init = &nv_need_reset_on_init,
961 .get_pcie_replay_count = &nv_get_pcie_replay_count,
962 .supports_baco = &amdgpu_dpm_is_baco_supported,
963 .pre_asic_init = &nv_pre_asic_init,
964 .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
965 .query_video_codecs = &nv_query_video_codecs,
966};
967
968static int nv_common_early_init(void *handle)
969{
970#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
972
973 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
974 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
975 adev->smc_rreg = NULL;
976 adev->smc_wreg = NULL;
977 adev->pcie_rreg = &nv_pcie_rreg;
978 adev->pcie_wreg = &nv_pcie_wreg;
979 adev->pcie_rreg64 = &nv_pcie_rreg64;
980 adev->pcie_wreg64 = &nv_pcie_wreg64;
981 adev->pciep_rreg = &nv_pcie_port_rreg;
982 adev->pciep_wreg = &nv_pcie_port_wreg;
983
984 /* TODO: will add them during VCN v2 implementation */
985 adev->uvd_ctx_rreg = NULL;
986 adev->uvd_ctx_wreg = NULL;
987
988 adev->didt_rreg = &nv_didt_rreg;
989 adev->didt_wreg = &nv_didt_wreg;
990
991 adev->asic_funcs = &nv_asic_funcs;
992
993 adev->rev_id = nv_get_rev_id(adev);
994 adev->external_rev_id = 0xff;
995 switch (adev->asic_type) {
996 case CHIP_NAVI10:
997 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
998 AMD_CG_SUPPORT_GFX_CGCG |
999 AMD_CG_SUPPORT_IH_CG |
1000 AMD_CG_SUPPORT_HDP_MGCG |
1001 AMD_CG_SUPPORT_HDP_LS |
1002 AMD_CG_SUPPORT_SDMA_MGCG |
1003 AMD_CG_SUPPORT_SDMA_LS |
1004 AMD_CG_SUPPORT_MC_MGCG |
1005 AMD_CG_SUPPORT_MC_LS |
1006 AMD_CG_SUPPORT_ATHUB_MGCG |
1007 AMD_CG_SUPPORT_ATHUB_LS |
1008 AMD_CG_SUPPORT_VCN_MGCG |
1009 AMD_CG_SUPPORT_JPEG_MGCG |
1010 AMD_CG_SUPPORT_BIF_MGCG |
1011 AMD_CG_SUPPORT_BIF_LS;
1012 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1013 AMD_PG_SUPPORT_VCN_DPG |
1014 AMD_PG_SUPPORT_JPEG |
1015 AMD_PG_SUPPORT_ATHUB;
1016 adev->external_rev_id = adev->rev_id + 0x1;
1017 break;
1018 case CHIP_NAVI14:
1019 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1020 AMD_CG_SUPPORT_GFX_CGCG |
1021 AMD_CG_SUPPORT_IH_CG |
1022 AMD_CG_SUPPORT_HDP_MGCG |
1023 AMD_CG_SUPPORT_HDP_LS |
1024 AMD_CG_SUPPORT_SDMA_MGCG |
1025 AMD_CG_SUPPORT_SDMA_LS |
1026 AMD_CG_SUPPORT_MC_MGCG |
1027 AMD_CG_SUPPORT_MC_LS |
1028 AMD_CG_SUPPORT_ATHUB_MGCG |
1029 AMD_CG_SUPPORT_ATHUB_LS |
1030 AMD_CG_SUPPORT_VCN_MGCG |
1031 AMD_CG_SUPPORT_JPEG_MGCG |
1032 AMD_CG_SUPPORT_BIF_MGCG |
1033 AMD_CG_SUPPORT_BIF_LS;
1034 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1035 AMD_PG_SUPPORT_JPEG |
1036 AMD_PG_SUPPORT_VCN_DPG;
1037 adev->external_rev_id = adev->rev_id + 20;
1038 break;
1039 case CHIP_NAVI12:
1040 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1041 AMD_CG_SUPPORT_GFX_MGLS |
1042 AMD_CG_SUPPORT_GFX_CGCG |
1043 AMD_CG_SUPPORT_GFX_CP_LS |
1044 AMD_CG_SUPPORT_GFX_RLC_LS |
1045 AMD_CG_SUPPORT_IH_CG |
1046 AMD_CG_SUPPORT_HDP_MGCG |
1047 AMD_CG_SUPPORT_HDP_LS |
1048 AMD_CG_SUPPORT_SDMA_MGCG |
1049 AMD_CG_SUPPORT_SDMA_LS |
1050 AMD_CG_SUPPORT_MC_MGCG |
1051 AMD_CG_SUPPORT_MC_LS |
1052 AMD_CG_SUPPORT_ATHUB_MGCG |
1053 AMD_CG_SUPPORT_ATHUB_LS |
1054 AMD_CG_SUPPORT_VCN_MGCG |
1055 AMD_CG_SUPPORT_JPEG_MGCG;
1056 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1057 AMD_PG_SUPPORT_VCN_DPG |
1058 AMD_PG_SUPPORT_JPEG |
1059 AMD_PG_SUPPORT_ATHUB;
1060 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1061 * as a consequence, the rev_id and external_rev_id are wrong.
1062 * workaround it by hardcoding rev_id to 0 (default value).
1063 */
1064 if (amdgpu_sriov_vf(adev))
1065 adev->rev_id = 0;
1066 adev->external_rev_id = adev->rev_id + 0xa;
1067 break;
1068 case CHIP_SIENNA_CICHLID:
1069 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1070 AMD_CG_SUPPORT_GFX_CGCG |
1071 AMD_CG_SUPPORT_GFX_3D_CGCG |
1072 AMD_CG_SUPPORT_MC_MGCG |
1073 AMD_CG_SUPPORT_VCN_MGCG |
1074 AMD_CG_SUPPORT_JPEG_MGCG |
1075 AMD_CG_SUPPORT_HDP_MGCG |
1076 AMD_CG_SUPPORT_HDP_LS |
1077 AMD_CG_SUPPORT_IH_CG |
1078 AMD_CG_SUPPORT_MC_LS;
1079 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1080 AMD_PG_SUPPORT_VCN_DPG |
1081 AMD_PG_SUPPORT_JPEG |
1082 AMD_PG_SUPPORT_ATHUB |
1083 AMD_PG_SUPPORT_MMHUB;
1084 if (amdgpu_sriov_vf(adev)) {
1085 /* hypervisor control CG and PG enablement */
1086 adev->cg_flags = 0;
1087 adev->pg_flags = 0;
1088 }
1089 adev->external_rev_id = adev->rev_id + 0x28;
1090 break;
1091 case CHIP_NAVY_FLOUNDER:
1092 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1093 AMD_CG_SUPPORT_GFX_CGCG |
1094 AMD_CG_SUPPORT_GFX_3D_CGCG |
1095 AMD_CG_SUPPORT_VCN_MGCG |
1096 AMD_CG_SUPPORT_JPEG_MGCG |
1097 AMD_CG_SUPPORT_MC_MGCG |
1098 AMD_CG_SUPPORT_MC_LS |
1099 AMD_CG_SUPPORT_HDP_MGCG |
1100 AMD_CG_SUPPORT_HDP_LS |
1101 AMD_CG_SUPPORT_IH_CG;
1102 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1103 AMD_PG_SUPPORT_VCN_DPG |
1104 AMD_PG_SUPPORT_JPEG |
1105 AMD_PG_SUPPORT_ATHUB |
1106 AMD_PG_SUPPORT_MMHUB;
1107 adev->external_rev_id = adev->rev_id + 0x32;
1108 break;
1109
1110 case CHIP_VANGOGH:
1111 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1112 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1113 AMD_CG_SUPPORT_GFX_MGLS |
1114 AMD_CG_SUPPORT_GFX_CP_LS |
1115 AMD_CG_SUPPORT_GFX_RLC_LS |
1116 AMD_CG_SUPPORT_GFX_CGCG |
1117 AMD_CG_SUPPORT_GFX_CGLS |
1118 AMD_CG_SUPPORT_GFX_3D_CGCG |
1119 AMD_CG_SUPPORT_GFX_3D_CGLS |
1120 AMD_CG_SUPPORT_MC_MGCG |
1121 AMD_CG_SUPPORT_MC_LS |
1122 AMD_CG_SUPPORT_GFX_FGCG |
1123 AMD_CG_SUPPORT_VCN_MGCG |
1124 AMD_CG_SUPPORT_JPEG_MGCG;
1125 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1126 AMD_PG_SUPPORT_VCN |
1127 AMD_PG_SUPPORT_VCN_DPG |
1128 AMD_PG_SUPPORT_JPEG;
1129 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1130 adev->external_rev_id = adev->rev_id + 0x01;
1131 break;
1132 case CHIP_DIMGREY_CAVEFISH:
1133 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1134 AMD_CG_SUPPORT_GFX_CGCG |
1135 AMD_CG_SUPPORT_GFX_3D_CGCG |
1136 AMD_CG_SUPPORT_VCN_MGCG |
1137 AMD_CG_SUPPORT_JPEG_MGCG |
1138 AMD_CG_SUPPORT_MC_MGCG |
1139 AMD_CG_SUPPORT_MC_LS |
1140 AMD_CG_SUPPORT_HDP_MGCG |
1141 AMD_CG_SUPPORT_HDP_LS |
1142 AMD_CG_SUPPORT_IH_CG;
1143 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1144 AMD_PG_SUPPORT_VCN_DPG |
1145 AMD_PG_SUPPORT_JPEG |
1146 AMD_PG_SUPPORT_ATHUB |
1147 AMD_PG_SUPPORT_MMHUB;
1148 adev->external_rev_id = adev->rev_id + 0x3c;
1149 break;
1150 default:
1151 /* FIXME: not supported yet */
1152 return -EINVAL;
1153 }
1154
1155 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1156 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1157 AMD_PG_SUPPORT_VCN_DPG |
1158 AMD_PG_SUPPORT_JPEG);
1159
1160 if (amdgpu_sriov_vf(adev)) {
1161 amdgpu_virt_init_setting(adev);
1162 xgpu_nv_mailbox_set_irq_funcs(adev);
1163 }
1164
1165 return 0;
1166}
1167
1168static int nv_common_late_init(void *handle)
1169{
1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171
1172 if (amdgpu_sriov_vf(adev))
1173 xgpu_nv_mailbox_get_irq(adev);
1174
1175 return 0;
1176}
1177
1178static int nv_common_sw_init(void *handle)
1179{
1180 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1181
1182 if (amdgpu_sriov_vf(adev))
1183 xgpu_nv_mailbox_add_irq_id(adev);
1184
1185 return 0;
1186}
1187
1188static int nv_common_sw_fini(void *handle)
1189{
1190 return 0;
1191}
1192
1193static int nv_common_hw_init(void *handle)
1194{
1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196
1197 /* enable pcie gen2/3 link */
1198 nv_pcie_gen3_enable(adev);
1199 /* enable aspm */
1200 nv_program_aspm(adev);
1201 /* setup nbio registers */
1202 adev->nbio.funcs->init_registers(adev);
1203 /* remap HDP registers to a hole in mmio space,
1204 * for the purpose of expose those registers
1205 * to process space
1206 */
1207 if (adev->nbio.funcs->remap_hdp_registers)
1208 adev->nbio.funcs->remap_hdp_registers(adev);
1209 /* enable the doorbell aperture */
1210 nv_enable_doorbell_aperture(adev, true);
1211
1212 return 0;
1213}
1214
1215static int nv_common_hw_fini(void *handle)
1216{
1217 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218
1219 /* disable the doorbell aperture */
1220 nv_enable_doorbell_aperture(adev, false);
1221
1222 return 0;
1223}
1224
1225static int nv_common_suspend(void *handle)
1226{
1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228
1229 return nv_common_hw_fini(adev);
1230}
1231
1232static int nv_common_resume(void *handle)
1233{
1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235
1236 return nv_common_hw_init(adev);
1237}
1238
1239static bool nv_common_is_idle(void *handle)
1240{
1241 return true;
1242}
1243
1244static int nv_common_wait_for_idle(void *handle)
1245{
1246 return 0;
1247}
1248
1249static int nv_common_soft_reset(void *handle)
1250{
1251 return 0;
1252}
1253
1254static int nv_common_set_clockgating_state(void *handle,
1255 enum amd_clockgating_state state)
1256{
1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258
1259 if (amdgpu_sriov_vf(adev))
1260 return 0;
1261
1262 switch (adev->asic_type) {
1263 case CHIP_NAVI10:
1264 case CHIP_NAVI14:
1265 case CHIP_NAVI12:
1266 case CHIP_SIENNA_CICHLID:
1267 case CHIP_NAVY_FLOUNDER:
1268 case CHIP_DIMGREY_CAVEFISH:
1269 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1270 state == AMD_CG_STATE_GATE);
1271 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1272 state == AMD_CG_STATE_GATE);
1273 adev->hdp.funcs->update_clock_gating(adev,
1274 state == AMD_CG_STATE_GATE);
1275 adev->smuio.funcs->update_rom_clock_gating(adev,
1276 state == AMD_CG_STATE_GATE);
1277 break;
1278 default:
1279 break;
1280 }
1281 return 0;
1282}
1283
1284static int nv_common_set_powergating_state(void *handle,
1285 enum amd_powergating_state state)
1286{
1287 /* TODO */
1288 return 0;
1289}
1290
1291static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1292{
1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1294
1295 if (amdgpu_sriov_vf(adev))
1296 *flags = 0;
1297
1298 adev->nbio.funcs->get_clockgating_state(adev, flags);
1299
1300 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1301
1302 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1303
1304 return;
1305}
1306
1307static const struct amd_ip_funcs nv_common_ip_funcs = {
1308 .name = "nv_common",
1309 .early_init = nv_common_early_init,
1310 .late_init = nv_common_late_init,
1311 .sw_init = nv_common_sw_init,
1312 .sw_fini = nv_common_sw_fini,
1313 .hw_init = nv_common_hw_init,
1314 .hw_fini = nv_common_hw_fini,
1315 .suspend = nv_common_suspend,
1316 .resume = nv_common_resume,
1317 .is_idle = nv_common_is_idle,
1318 .wait_for_idle = nv_common_wait_for_idle,
1319 .soft_reset = nv_common_soft_reset,
1320 .set_clockgating_state = nv_common_set_clockgating_state,
1321 .set_powergating_state = nv_common_set_powergating_state,
1322 .get_clockgating_state = nv_common_get_clockgating_state,
1323};