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linux
1#
2# EDAC Kconfig
3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
4# Licensed and distributed under the GPL
5
6config EDAC_ATOMIC_SCRUB
7 bool
8
9config EDAC_SUPPORT
10 bool
11
12menuconfig EDAC
13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
15 help
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
21
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
23
24if EDAC
25
26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
34config EDAC_DEBUG
35 bool "Debugging"
36 select DEBUG_FS
37 help
38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
42
43config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
45 depends on CPU_SUP_AMD && X86_MCE_AMD
46 default y
47 help
48 Enable this option if you want to decode Machine Check Exceptions
49 occurring on your machine in human-readable form.
50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
55config EDAC_GHES
56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
57 depends on ACPI_APEI_GHES && (EDAC=y)
58 help
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
61 APEI/GHES driver. By enabling this option, the error reports provided
62 by GHES are sent to userspace via the EDAC API.
63
64 When this option is enabled, it will disable the hardware-driven
65 mechanisms, if a GHES BIOS is detected, entering into the
66 "Firmware First" mode.
67
68 It should be noticed that keeping both GHES and a hardware-driven
69 error mechanism won't work well, as BIOS will race with OS, while
70 reading the error registers. So, if you want to not use "Firmware
71 first" GHES error mechanism, you should disable GHES either at
72 compilation time or by passing "ghes.disable=1" Kernel parameter
73 at boot time.
74
75 In doubt, say 'Y'.
76
77config EDAC_AMD64
78 tristate "AMD64 (Opteron, Athlon64)"
79 depends on AMD_NB && EDAC_DECODE_MCE
80 help
81 Support for error detection and correction of DRAM ECC errors on
82 the AMD64 families (>= K8) of memory controllers.
83
84 When EDAC_DEBUG is enabled, hardware error injection facilities
85 through sysfs are available:
86
87 AMD CPUs up to and excluding family 0x17 provide for Memory
88 Error Injection into the ECC detection circuits. The amd64_edac
89 module allows the operator/user to inject Uncorrectable and
90 Correctable errors into DRAM.
91
92 When enabled, in each of the respective memory controller directories
93 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
94
95 - inject_section (0..3, 16-byte section of 64-byte cacheline),
96 - inject_word (0..8, 16-bit word of 16-byte section),
97 - inject_ecc_vector (hex ecc vector: select bits of inject word)
98
99 In addition, there are two control files, inject_read and inject_write,
100 which trigger the DRAM ECC Read and Write respectively.
101
102config EDAC_AL_MC
103 tristate "Amazon's Annapurna Lab Memory Controller"
104 depends on (ARCH_ALPINE || COMPILE_TEST)
105 help
106 Support for error detection and correction for Amazon's Annapurna
107 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
108
109config EDAC_AMD76X
110 tristate "AMD 76x (760, 762, 768)"
111 depends on PCI && X86_32
112 help
113 Support for error detection and correction on the AMD 76x
114 series of chipsets used with the Athlon processor.
115
116config EDAC_E7XXX
117 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
118 depends on PCI && X86_32
119 help
120 Support for error detection and correction on the Intel
121 E7205, E7500, E7501 and E7505 server chipsets.
122
123config EDAC_E752X
124 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
125 depends on PCI && X86
126 help
127 Support for error detection and correction on the Intel
128 E7520, E7525, E7320 server chipsets.
129
130config EDAC_I82443BXGX
131 tristate "Intel 82443BX/GX (440BX/GX)"
132 depends on PCI && X86_32
133 depends on BROKEN
134 help
135 Support for error detection and correction on the Intel
136 82443BX/GX memory controllers (440BX/GX chipsets).
137
138config EDAC_I82875P
139 tristate "Intel 82875p (D82875P, E7210)"
140 depends on PCI && X86_32
141 help
142 Support for error detection and correction on the Intel
143 DP82785P and E7210 server chipsets.
144
145config EDAC_I82975X
146 tristate "Intel 82975x (D82975x)"
147 depends on PCI && X86
148 help
149 Support for error detection and correction on the Intel
150 DP82975x server chipsets.
151
152config EDAC_I3000
153 tristate "Intel 3000/3010"
154 depends on PCI && X86
155 help
156 Support for error detection and correction on the Intel
157 3000 and 3010 server chipsets.
158
159config EDAC_I3200
160 tristate "Intel 3200"
161 depends on PCI && X86
162 help
163 Support for error detection and correction on the Intel
164 3200 and 3210 server chipsets.
165
166config EDAC_IE31200
167 tristate "Intel e312xx"
168 depends on PCI && X86
169 help
170 Support for error detection and correction on the Intel
171 E3-1200 based DRAM controllers.
172
173config EDAC_X38
174 tristate "Intel X38"
175 depends on PCI && X86
176 help
177 Support for error detection and correction on the Intel
178 X38 server chipsets.
179
180config EDAC_I5400
181 tristate "Intel 5400 (Seaburg) chipsets"
182 depends on PCI && X86
183 help
184 Support for error detection and correction the Intel
185 i5400 MCH chipset (Seaburg).
186
187config EDAC_I7CORE
188 tristate "Intel i7 Core (Nehalem) processors"
189 depends on PCI && X86 && X86_MCE_INTEL
190 help
191 Support for error detection and correction the Intel
192 i7 Core (Nehalem) Integrated Memory Controller that exists on
193 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
194 and Xeon 55xx processors.
195
196config EDAC_I82860
197 tristate "Intel 82860"
198 depends on PCI && X86_32
199 help
200 Support for error detection and correction on the Intel
201 82860 chipset.
202
203config EDAC_R82600
204 tristate "Radisys 82600 embedded chipset"
205 depends on PCI && X86_32
206 help
207 Support for error detection and correction on the Radisys
208 82600 embedded chipset.
209
210config EDAC_I5000
211 tristate "Intel Greencreek/Blackford chipset"
212 depends on X86 && PCI
213 help
214 Support for error detection and correction the Intel
215 Greekcreek/Blackford chipsets.
216
217config EDAC_I5100
218 tristate "Intel San Clemente MCH"
219 depends on X86 && PCI
220 help
221 Support for error detection and correction the Intel
222 San Clemente MCH.
223
224config EDAC_I7300
225 tristate "Intel Clarksboro MCH"
226 depends on X86 && PCI
227 help
228 Support for error detection and correction the Intel
229 Clarksboro MCH (Intel 7300 chipset).
230
231config EDAC_SBRIDGE
232 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
233 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
234 help
235 Support for error detection and correction the Intel
236 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
237
238config EDAC_SKX
239 tristate "Intel Skylake server Integrated MC"
240 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
241 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
242 select DMI
243 select ACPI_ADXL
244 help
245 Support for error detection and correction the Intel
246 Skylake server Integrated Memory Controllers. If your
247 system has non-volatile DIMMs you should also manually
248 select CONFIG_ACPI_NFIT.
249
250config EDAC_I10NM
251 tristate "Intel 10nm server Integrated MC"
252 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
253 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
254 select DMI
255 select ACPI_ADXL
256 help
257 Support for error detection and correction the Intel
258 10nm server Integrated Memory Controllers. If your
259 system has non-volatile DIMMs you should also manually
260 select CONFIG_ACPI_NFIT.
261
262config EDAC_PND2
263 tristate "Intel Pondicherry2"
264 depends on PCI && X86_64 && X86_MCE_INTEL
265 help
266 Support for error detection and correction on the Intel
267 Pondicherry2 Integrated Memory Controller. This SoC IP is
268 first used on the Apollo Lake platform and Denverton
269 micro-server but may appear on others in the future.
270
271config EDAC_IGEN6
272 tristate "Intel client SoC Integrated MC"
273 depends on PCI && X86_64 && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
274 help
275 Support for error detection and correction on the Intel
276 client SoC Integrated Memory Controller using In-Band ECC IP.
277 This In-Band ECC is first used on the Elkhart Lake SoC but
278 may appear on others in the future.
279
280config EDAC_MPC85XX
281 bool "Freescale MPC83xx / MPC85xx"
282 depends on FSL_SOC && EDAC=y
283 help
284 Support for error detection and correction on the Freescale
285 MPC8349, MPC8560, MPC8540, MPC8548, T4240
286
287config EDAC_LAYERSCAPE
288 tristate "Freescale Layerscape DDR"
289 depends on ARCH_LAYERSCAPE || SOC_LS1021A
290 help
291 Support for error detection and correction on Freescale memory
292 controllers on Layerscape SoCs.
293
294config EDAC_PASEMI
295 tristate "PA Semi PWRficient"
296 depends on PPC_PASEMI && PCI
297 help
298 Support for error detection and correction on PA Semi
299 PWRficient.
300
301config EDAC_CELL
302 tristate "Cell Broadband Engine memory controller"
303 depends on PPC_CELL_COMMON
304 help
305 Support for error detection and correction on the
306 Cell Broadband Engine internal memory controller
307 on platform without a hypervisor
308
309config EDAC_PPC4XX
310 tristate "PPC4xx IBM DDR2 Memory Controller"
311 depends on 4xx
312 help
313 This enables support for EDAC on the ECC memory used
314 with the IBM DDR2 memory controller found in various
315 PowerPC 4xx embedded processors such as the 405EX[r],
316 440SP, 440SPe, 460EX, 460GT and 460SX.
317
318config EDAC_AMD8131
319 tristate "AMD8131 HyperTransport PCI-X Tunnel"
320 depends on PCI && PPC_MAPLE
321 help
322 Support for error detection and correction on the
323 AMD8131 HyperTransport PCI-X Tunnel chip.
324 Note, add more Kconfig dependency if it's adopted
325 on some machine other than Maple.
326
327config EDAC_AMD8111
328 tristate "AMD8111 HyperTransport I/O Hub"
329 depends on PCI && PPC_MAPLE
330 help
331 Support for error detection and correction on the
332 AMD8111 HyperTransport I/O Hub chip.
333 Note, add more Kconfig dependency if it's adopted
334 on some machine other than Maple.
335
336config EDAC_CPC925
337 tristate "IBM CPC925 Memory Controller (PPC970FX)"
338 depends on PPC64
339 help
340 Support for error detection and correction on the
341 IBM CPC925 Bridge and Memory Controller, which is
342 a companion chip to the PowerPC 970 family of
343 processors.
344
345config EDAC_HIGHBANK_MC
346 tristate "Highbank Memory Controller"
347 depends on ARCH_HIGHBANK
348 help
349 Support for error detection and correction on the
350 Calxeda Highbank memory controller.
351
352config EDAC_HIGHBANK_L2
353 tristate "Highbank L2 Cache"
354 depends on ARCH_HIGHBANK
355 help
356 Support for error detection and correction on the
357 Calxeda Highbank memory controller.
358
359config EDAC_OCTEON_PC
360 tristate "Cavium Octeon Primary Caches"
361 depends on CPU_CAVIUM_OCTEON
362 help
363 Support for error detection and correction on the primary caches of
364 the cnMIPS cores of Cavium Octeon family SOCs.
365
366config EDAC_OCTEON_L2C
367 tristate "Cavium Octeon Secondary Caches (L2C)"
368 depends on CAVIUM_OCTEON_SOC
369 help
370 Support for error detection and correction on the
371 Cavium Octeon family of SOCs.
372
373config EDAC_OCTEON_LMC
374 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
375 depends on CAVIUM_OCTEON_SOC
376 help
377 Support for error detection and correction on the
378 Cavium Octeon family of SOCs.
379
380config EDAC_OCTEON_PCI
381 tristate "Cavium Octeon PCI Controller"
382 depends on PCI && CAVIUM_OCTEON_SOC
383 help
384 Support for error detection and correction on the
385 Cavium Octeon family of SOCs.
386
387config EDAC_THUNDERX
388 tristate "Cavium ThunderX EDAC"
389 depends on ARM64
390 depends on PCI
391 help
392 Support for error detection and correction on the
393 Cavium ThunderX memory controllers (LMC), Cache
394 Coherent Processor Interconnect (CCPI) and L2 cache
395 blocks (TAD, CBC, MCI).
396
397config EDAC_ALTERA
398 bool "Altera SOCFPGA ECC"
399 depends on EDAC=y && ARCH_INTEL_SOCFPGA
400 help
401 Support for error detection and correction on the
402 Altera SOCs. This is the global enable for the
403 various Altera peripherals.
404
405config EDAC_ALTERA_SDRAM
406 bool "Altera SDRAM ECC"
407 depends on EDAC_ALTERA=y
408 help
409 Support for error detection and correction on the
410 Altera SDRAM Memory for Altera SoCs. Note that the
411 preloader must initialize the SDRAM before loading
412 the kernel.
413
414config EDAC_ALTERA_L2C
415 bool "Altera L2 Cache ECC"
416 depends on EDAC_ALTERA=y && CACHE_L2X0
417 help
418 Support for error detection and correction on the
419 Altera L2 cache Memory for Altera SoCs. This option
420 requires L2 cache.
421
422config EDAC_ALTERA_OCRAM
423 bool "Altera On-Chip RAM ECC"
424 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
425 help
426 Support for error detection and correction on the
427 Altera On-Chip RAM Memory for Altera SoCs.
428
429config EDAC_ALTERA_ETHERNET
430 bool "Altera Ethernet FIFO ECC"
431 depends on EDAC_ALTERA=y
432 help
433 Support for error detection and correction on the
434 Altera Ethernet FIFO Memory for Altera SoCs.
435
436config EDAC_ALTERA_NAND
437 bool "Altera NAND FIFO ECC"
438 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
439 help
440 Support for error detection and correction on the
441 Altera NAND FIFO Memory for Altera SoCs.
442
443config EDAC_ALTERA_DMA
444 bool "Altera DMA FIFO ECC"
445 depends on EDAC_ALTERA=y && PL330_DMA=y
446 help
447 Support for error detection and correction on the
448 Altera DMA FIFO Memory for Altera SoCs.
449
450config EDAC_ALTERA_USB
451 bool "Altera USB FIFO ECC"
452 depends on EDAC_ALTERA=y && USB_DWC2
453 help
454 Support for error detection and correction on the
455 Altera USB FIFO Memory for Altera SoCs.
456
457config EDAC_ALTERA_QSPI
458 bool "Altera QSPI FIFO ECC"
459 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
460 help
461 Support for error detection and correction on the
462 Altera QSPI FIFO Memory for Altera SoCs.
463
464config EDAC_ALTERA_SDMMC
465 bool "Altera SDMMC FIFO ECC"
466 depends on EDAC_ALTERA=y && MMC_DW
467 help
468 Support for error detection and correction on the
469 Altera SDMMC FIFO Memory for Altera SoCs.
470
471config EDAC_SIFIVE
472 bool "Sifive platform EDAC driver"
473 depends on EDAC=y && SIFIVE_L2
474 help
475 Support for error detection and correction on the SiFive SoCs.
476
477config EDAC_ARMADA_XP
478 bool "Marvell Armada XP DDR and L2 Cache ECC"
479 depends on MACH_MVEBU_V7
480 help
481 Support for error correction and detection on the Marvell Aramada XP
482 DDR RAM and L2 cache controllers.
483
484config EDAC_SYNOPSYS
485 tristate "Synopsys DDR Memory Controller"
486 depends on ARCH_ZYNQ || ARCH_ZYNQMP
487 help
488 Support for error detection and correction on the Synopsys DDR
489 memory controller.
490
491config EDAC_XGENE
492 tristate "APM X-Gene SoC"
493 depends on (ARM64 || COMPILE_TEST)
494 help
495 Support for error detection and correction on the
496 APM X-Gene family of SOCs.
497
498config EDAC_TI
499 tristate "Texas Instruments DDR3 ECC Controller"
500 depends on ARCH_KEYSTONE || SOC_DRA7XX
501 help
502 Support for error detection and correction on the TI SoCs.
503
504config EDAC_QCOM
505 tristate "QCOM EDAC Controller"
506 depends on ARCH_QCOM && QCOM_LLCC
507 help
508 Support for error detection and correction on the
509 Qualcomm Technologies, Inc. SoCs.
510
511 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
512 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
513 of Tag RAM and Data RAM.
514
515 For debugging issues having to do with stability and overall system
516 health, you should probably say 'Y' here.
517
518config EDAC_ASPEED
519 tristate "Aspeed AST BMC SoC"
520 depends on ARCH_ASPEED
521 help
522 Support for error detection and correction on the Aspeed AST BMC SoC.
523
524 First, ECC must be configured in the bootloader. Then, this driver
525 will expose error counters via the EDAC kernel framework.
526
527config EDAC_BLUEFIELD
528 tristate "Mellanox BlueField Memory ECC"
529 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
530 help
531 Support for error detection and correction on the
532 Mellanox BlueField SoCs.
533
534config EDAC_DMC520
535 tristate "ARM DMC-520 ECC"
536 depends on ARM64
537 help
538 Support for error detection and correction on the
539 SoCs with ARM DMC-520 DRAM controller.
540
541endif # EDAC