tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2021 Linaro Ltd. */
4
5#include <linux/log2.h>
6
7#include "gsi.h"
8#include "ipa_data.h"
9#include "ipa_endpoint.h"
10#include "ipa_mem.h"
11
12/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.9 */
13enum ipa_resource_type {
14 /* Source resource types; first must have value 0 */
15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20
21 /* Destination resource types; first must have value 0 */
22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
23 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24};
25
26/* Resource groups used for an SoC having IPA v4.9 */
27enum ipa_rsrc_group_id {
28 /* Source resource group identifiers */
29 IPA_RSRC_GROUP_SRC_UL_DL = 0,
30 IPA_RSRC_GROUP_SRC_DMA,
31 IPA_RSRC_GROUP_SRC_UC_RX_Q,
32 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
33
34 /* Destination resource group identifiers */
35 IPA_RSRC_GROUP_DST_UL_DL_DPL = 0,
36 IPA_RSRC_GROUP_DST_DMA,
37 IPA_RSRC_GROUP_DST_UC,
38 IPA_RSRC_GROUP_DST_DRB_IP,
39 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
40};
41
42/* QSB configuration data for an SoC having IPA v4.9 */
43static const struct ipa_qsb_data ipa_qsb_data[] = {
44 [IPA_QSB_MASTER_DDR] = {
45 .max_writes = 8,
46 .max_reads = 0, /* no limit (hardware max) */
47 .max_reads_beats = 120,
48 },
49};
50
51/* Endpoint configuration data for an SoC having IPA v4.9 */
52static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
53 [IPA_ENDPOINT_AP_COMMAND_TX] = {
54 .ee_id = GSI_EE_AP,
55 .channel_id = 6,
56 .endpoint_id = 7,
57 .toward_ipa = true,
58 .channel = {
59 .tre_count = 256,
60 .event_count = 256,
61 .tlv_count = 20,
62 },
63 .endpoint = {
64 .config = {
65 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
66 .dma_mode = true,
67 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
68 .tx = {
69 .seq_type = IPA_SEQ_DMA,
70 },
71 },
72 },
73 },
74 [IPA_ENDPOINT_AP_LAN_RX] = {
75 .ee_id = GSI_EE_AP,
76 .channel_id = 7,
77 .endpoint_id = 11,
78 .toward_ipa = false,
79 .channel = {
80 .tre_count = 256,
81 .event_count = 256,
82 .tlv_count = 9,
83 },
84 .endpoint = {
85 .config = {
86 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
87 .aggregation = true,
88 .status_enable = true,
89 .rx = {
90 .pad_align = ilog2(sizeof(u32)),
91 },
92 },
93 },
94 },
95 [IPA_ENDPOINT_AP_MODEM_TX] = {
96 .ee_id = GSI_EE_AP,
97 .channel_id = 2,
98 .endpoint_id = 2,
99 .toward_ipa = true,
100 .channel = {
101 .tre_count = 512,
102 .event_count = 512,
103 .tlv_count = 16,
104 },
105 .endpoint = {
106 .filter_support = true,
107 .config = {
108 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
109 .qmap = true,
110 .status_enable = true,
111 .tx = {
112 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
113 .status_endpoint =
114 IPA_ENDPOINT_MODEM_AP_RX,
115 },
116 },
117 },
118 },
119 [IPA_ENDPOINT_AP_MODEM_RX] = {
120 .ee_id = GSI_EE_AP,
121 .channel_id = 12,
122 .endpoint_id = 20,
123 .toward_ipa = false,
124 .channel = {
125 .tre_count = 256,
126 .event_count = 256,
127 .tlv_count = 9,
128 },
129 .endpoint = {
130 .config = {
131 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
132 .qmap = true,
133 .aggregation = true,
134 .rx = {
135 .aggr_close_eof = true,
136 },
137 },
138 },
139 },
140 [IPA_ENDPOINT_MODEM_AP_TX] = {
141 .ee_id = GSI_EE_MODEM,
142 .channel_id = 0,
143 .endpoint_id = 5,
144 .toward_ipa = true,
145 .endpoint = {
146 .filter_support = true,
147 },
148 },
149 [IPA_ENDPOINT_MODEM_AP_RX] = {
150 .ee_id = GSI_EE_MODEM,
151 .channel_id = 7,
152 .endpoint_id = 16,
153 .toward_ipa = false,
154 },
155 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
156 .ee_id = GSI_EE_MODEM,
157 .channel_id = 2,
158 .endpoint_id = 8,
159 .toward_ipa = true,
160 .endpoint = {
161 .filter_support = true,
162 },
163 },
164};
165
166/* Source resource configuration data for an SoC having IPA v4.9 */
167static const struct ipa_resource ipa_resource_src[] = {
168 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
169 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
170 .min = 1, .max = 12,
171 },
172 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
173 .min = 1, .max = 1,
174 },
175 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
176 .min = 1, .max = 12,
177 },
178 },
179 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
180 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
181 .min = 20, .max = 20,
182 },
183 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
184 .min = 2, .max = 2,
185 },
186 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
187 .min = 3, .max = 3,
188 },
189 },
190 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
191 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
192 .min = 38, .max = 38,
193 },
194 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
195 .min = 4, .max = 4,
196 },
197 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
198 .min = 8, .max = 8,
199 },
200 },
201 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
202 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
203 .min = 0, .max = 4,
204 },
205 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
206 .min = 0, .max = 4,
207 },
208 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
209 .min = 0, .max = 4,
210 },
211 },
212 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
213 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
214 .min = 30, .max = 30,
215 },
216 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
217 .min = 8, .max = 8,
218 },
219 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
220 .min = 8, .max = 8,
221 },
222 },
223};
224
225/* Destination resource configuration data for an SoC having IPA v4.9 */
226static const struct ipa_resource ipa_resource_dst[] = {
227 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
228 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
229 .min = 9, .max = 9,
230 },
231 .limits[IPA_RSRC_GROUP_DST_DMA] = {
232 .min = 1, .max = 1,
233 },
234 .limits[IPA_RSRC_GROUP_DST_UC] = {
235 .min = 1, .max = 1,
236 },
237 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
238 .min = 39, .max = 39,
239 },
240 },
241 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
242 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
243 .min = 2, .max = 3,
244 },
245 .limits[IPA_RSRC_GROUP_DST_DMA] = {
246 .min = 1, .max = 2,
247 },
248 .limits[IPA_RSRC_GROUP_DST_UC] = {
249 .min = 0, .max = 2,
250 },
251 },
252};
253
254/* Resource configuration data for an SoC having IPA v4.9 */
255static const struct ipa_resource_data ipa_resource_data = {
256 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
257 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
258 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
259 .resource_src = ipa_resource_src,
260 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
261 .resource_dst = ipa_resource_dst,
262};
263
264/* IPA-resident memory region data for an SoC having IPA v4.9 */
265static const struct ipa_mem ipa_mem_local_data[] = {
266 [IPA_MEM_UC_SHARED] = {
267 .offset = 0x0000,
268 .size = 0x0080,
269 .canary_count = 0,
270 },
271 [IPA_MEM_UC_INFO] = {
272 .offset = 0x0080,
273 .size = 0x0200,
274 .canary_count = 0,
275 },
276 [IPA_MEM_V4_FILTER_HASHED] = { .offset = 0x0288,
277 .size = 0x0078,
278 .canary_count = 2,
279 },
280 [IPA_MEM_V4_FILTER] = {
281 .offset = 0x0308,
282 .size = 0x0078,
283 .canary_count = 2,
284 },
285 [IPA_MEM_V6_FILTER_HASHED] = {
286 .offset = 0x0388,
287 .size = 0x0078,
288 .canary_count = 2,
289 },
290 [IPA_MEM_V6_FILTER] = {
291 .offset = 0x0408,
292 .size = 0x0078,
293 .canary_count = 2,
294 },
295 [IPA_MEM_V4_ROUTE_HASHED] = {
296 .offset = 0x0488,
297 .size = 0x0078,
298 .canary_count = 2,
299 },
300 [IPA_MEM_V4_ROUTE] = {
301 .offset = 0x0508,
302 .size = 0x0078,
303 .canary_count = 2,
304 },
305 [IPA_MEM_V6_ROUTE_HASHED] = {
306 .offset = 0x0588,
307 .size = 0x0078,
308 .canary_count = 2,
309 },
310 [IPA_MEM_V6_ROUTE] = {
311 .offset = 0x0608,
312 .size = 0x0078,
313 .canary_count = 2,
314 },
315 [IPA_MEM_MODEM_HEADER] = {
316 .offset = 0x0688,
317 .size = 0x0240,
318 .canary_count = 2,
319 },
320 [IPA_MEM_AP_HEADER] = {
321 .offset = 0x08c8,
322 .size = 0x0200,
323 .canary_count = 0,
324 },
325 [IPA_MEM_MODEM_PROC_CTX] = {
326 .offset = 0x0ad0,
327 .size = 0x0b20,
328 .canary_count = 2,
329 },
330 [IPA_MEM_AP_PROC_CTX] = {
331 .offset = 0x15f0,
332 .size = 0x0200,
333 .canary_count = 0,
334 },
335 [IPA_MEM_NAT_TABLE] = {
336 .offset = 0x1800,
337 .size = 0x0d00,
338 .canary_count = 4,
339 },
340 [IPA_MEM_STATS_QUOTA_MODEM] = {
341 .offset = 0x2510,
342 .size = 0x0030,
343 .canary_count = 4,
344 },
345 [IPA_MEM_STATS_QUOTA_AP] = {
346 .offset = 0x2540,
347 .size = 0x0048,
348 .canary_count = 0,
349 },
350 [IPA_MEM_STATS_TETHERING] = {
351 .offset = 0x2588,
352 .size = 0x0238,
353 .canary_count = 0,
354 },
355 [IPA_MEM_STATS_FILTER_ROUTE] = {
356 .offset = 0x27c0,
357 .size = 0x0800,
358 .canary_count = 0,
359 },
360 [IPA_MEM_STATS_DROP] = {
361 .offset = 0x2fc0,
362 .size = 0x0020,
363 .canary_count = 0,
364 },
365 [IPA_MEM_MODEM] = {
366 .offset = 0x2fe8,
367 .size = 0x0800,
368 .canary_count = 2,
369 },
370 [IPA_MEM_UC_EVENT_RING] = {
371 .offset = 0x3800,
372 .size = 0x1000,
373 .canary_count = 1,
374 },
375 [IPA_MEM_PDN_CONFIG] = {
376 .offset = 0x4800,
377 .size = 0x0050,
378 .canary_count = 0,
379 },
380};
381
382/* Memory configuration data for an SoC having IPA v4.9 */
383static const struct ipa_mem_data ipa_mem_data = {
384 .local_count = ARRAY_SIZE(ipa_mem_local_data),
385 .local = ipa_mem_local_data,
386 .imem_addr = 0x146bd000,
387 .imem_size = 0x00002000,
388 .smem_id = 497,
389 .smem_size = 0x00009000,
390};
391
392/* Interconnect rates are in 1000 byte/second units */
393static const struct ipa_interconnect_data ipa_interconnect_data[] = {
394 {
395 .name = "ipa_to_llcc",
396 .peak_bandwidth = 600000, /* 600 MBps */
397 .average_bandwidth = 150000, /* 150 MBps */
398 },
399 {
400 .name = "llcc_to_ebi1",
401 .peak_bandwidth = 1804000, /* 1.804 GBps */
402 .average_bandwidth = 150000, /* 150 MBps */
403 },
404 /* Average rate is unused for the next interconnect */
405 {
406 .name = "appss_to_ipa",
407 .peak_bandwidth = 74000, /* 74 MBps */
408 .average_bandwidth = 0, /* unused */
409 },
410
411};
412
413/* Clock and interconnect configuration data for an SoC having IPA v4.9 */
414static const struct ipa_clock_data ipa_clock_data = {
415 .core_clock_rate = 60 * 1000 * 1000, /* Hz */
416 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
417 .interconnect_data = ipa_interconnect_data,
418};
419
420/* Configuration data for an SoC having IPA v4.9. */
421const struct ipa_data ipa_data_v4_9 = {
422 .version = IPA_VERSION_4_9,
423 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
424 .qsb_data = ipa_qsb_data,
425 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
426 .endpoint_data = ipa_gsi_endpoint_data,
427 .resource_data = &ipa_resource_data,
428 .mem_data = &ipa_mem_data,
429 .clock_data = &ipa_clock_data,
430};