tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm Quad Serial Peripheral Interface (QSPI)
9
10maintainers:
11 - Mukesh Savaliya <msavaliy@codeaurora.org>
12 - Akash Asthana <akashast@codeaurora.org>
13
14description: The QSPI controller allows SPI protocol communication in single,
15 dual, or quad wire transmission modes for read/write access to slaves such
16 as NOR flash.
17
18allOf:
19 - $ref: /spi/spi-controller.yaml#
20
21properties:
22 compatible:
23 items:
24 - const: qcom,sdm845-qspi
25 - const: qcom,qspi-v1
26
27 reg:
28 maxItems: 1
29
30 interrupts:
31 maxItems: 1
32
33 clock-names:
34 items:
35 - const: iface
36 - const: core
37
38 clocks:
39 items:
40 - description: AHB clock
41 - description: QSPI core clock
42
43 interconnects:
44 minItems: 1
45 maxItems: 2
46
47 interconnect-names:
48 items:
49 - const: qspi-config
50 - const: qspi-memory
51
52required:
53 - compatible
54 - reg
55 - interrupts
56 - clock-names
57 - clocks
58
59unevaluatedProperties: false
60
61examples:
62 - |
63 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
64 #include <dt-bindings/interrupt-controller/arm-gic.h>
65
66 soc: soc {
67 #address-cells = <2>;
68 #size-cells = <2>;
69
70 qspi: spi@88df000 {
71 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
72 reg = <0 0x88df000 0 0x600>;
73 #address-cells = <1>;
74 #size-cells = <0>;
75 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
76 clock-names = "iface", "core";
77 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
78 <&gcc GCC_QSPI_CORE_CLK>;
79
80 flash@0 {
81 compatible = "jedec,spi-nor";
82 reg = <0>;
83 spi-max-frequency = <25000000>;
84 spi-tx-bus-width = <2>;
85 spi-rx-bus-width = <2>;
86 };
87
88 };
89 };
90...