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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Allwinner H6 CPU OPP Device Tree Bindings
8
9maintainers:
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
12
13description: |
14 For some SoCs, the CPU frequency subset and voltage value of each
15 OPP varies based on the silicon variant in use. Allwinner Process
16 Voltage Scaling Tables defines the voltage and frequency value based
17 on the speedbin blown in the efuse combination. The
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
20
21properties:
22 compatible:
23 const: allwinner,sun50i-h6-operating-points
24
25 nvmem-cells:
26 description: |
27 A phandle pointing to a nvmem-cells node representing the efuse
28 registers that has information about the speedbin that is used
29 to select the right frequency/voltage value pair. Please refer
30 the for nvmem-cells bindings
31 Documentation/devicetree/bindings/nvmem/nvmem.txt and also
32 examples below.
33
34 opp-shared: true
35
36required:
37 - compatible
38 - nvmem-cells
39
40patternProperties:
41 "opp-[0-9]+":
42 type: object
43
44 properties:
45 opp-hz: true
46
47 patternProperties:
48 "opp-microvolt-.*": true
49
50 required:
51 - opp-hz
52 - opp-microvolt-speed0
53 - opp-microvolt-speed1
54 - opp-microvolt-speed2
55
56 unevaluatedProperties: false
57
58additionalProperties: false
59
60examples:
61 - |
62 cpu_opp_table: opp-table {
63 compatible = "allwinner,sun50i-h6-operating-points";
64 nvmem-cells = <&speedbin_efuse>;
65 opp-shared;
66
67 opp-480000000 {
68 clock-latency-ns = <244144>; /* 8 32k periods */
69 opp-hz = /bits/ 64 <480000000>;
70
71 opp-microvolt-speed0 = <880000>;
72 opp-microvolt-speed1 = <820000>;
73 opp-microvolt-speed2 = <800000>;
74 };
75
76 opp-720000000 {
77 clock-latency-ns = <244144>; /* 8 32k periods */
78 opp-hz = /bits/ 64 <720000000>;
79
80 opp-microvolt-speed0 = <880000>;
81 opp-microvolt-speed1 = <820000>;
82 opp-microvolt-speed2 = <800000>;
83 };
84
85 opp-816000000 {
86 clock-latency-ns = <244144>; /* 8 32k periods */
87 opp-hz = /bits/ 64 <816000000>;
88
89 opp-microvolt-speed0 = <880000>;
90 opp-microvolt-speed1 = <820000>;
91 opp-microvolt-speed2 = <800000>;
92 };
93
94 opp-888000000 {
95 clock-latency-ns = <244144>; /* 8 32k periods */
96 opp-hz = /bits/ 64 <888000000>;
97
98 opp-microvolt-speed0 = <940000>;
99 opp-microvolt-speed1 = <820000>;
100 opp-microvolt-speed2 = <800000>;
101 };
102
103 opp-1080000000 {
104 clock-latency-ns = <244144>; /* 8 32k periods */
105 opp-hz = /bits/ 64 <1080000000>;
106
107 opp-microvolt-speed0 = <1060000>;
108 opp-microvolt-speed1 = <880000>;
109 opp-microvolt-speed2 = <840000>;
110 };
111
112 opp-1320000000 {
113 clock-latency-ns = <244144>; /* 8 32k periods */
114 opp-hz = /bits/ 64 <1320000000>;
115
116 opp-microvolt-speed0 = <1160000>;
117 opp-microvolt-speed1 = <940000>;
118 opp-microvolt-speed2 = <900000>;
119 };
120
121 opp-1488000000 {
122 clock-latency-ns = <244144>; /* 8 32k periods */
123 opp-hz = /bits/ 64 <1488000000>;
124
125 opp-microvolt-speed0 = <1160000>;
126 opp-microvolt-speed1 = <1000000>;
127 opp-microvolt-speed2 = <960000>;
128 };
129 };
130
131...