tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

kernel / include / linux / mfd / rohm-bd70528.h
at v5.12-rc5 391 lines 11 kB view raw
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* Copyright (C) 2018 ROHM Semiconductors */ 3 4#ifndef __LINUX_MFD_BD70528_H__ 5#define __LINUX_MFD_BD70528_H__ 6 7#include <linux/bits.h> 8#include <linux/device.h> 9#include <linux/mfd/rohm-generic.h> 10#include <linux/mfd/rohm-shared.h> 11#include <linux/regmap.h> 12 13enum { 14 BD70528_BUCK1, 15 BD70528_BUCK2, 16 BD70528_BUCK3, 17 BD70528_LDO1, 18 BD70528_LDO2, 19 BD70528_LDO3, 20 BD70528_LED1, 21 BD70528_LED2, 22}; 23 24struct bd70528_data { 25 struct rohm_regmap_dev chip; 26 struct mutex rtc_timer_lock; 27}; 28 29#define BD70528_BUCK_VOLTS 17 30#define BD70528_BUCK_VOLTS 17 31#define BD70528_BUCK_VOLTS 17 32#define BD70528_LDO_VOLTS 0x20 33 34#define BD70528_REG_BUCK1_EN 0x0F 35#define BD70528_REG_BUCK1_VOLT 0x15 36#define BD70528_REG_BUCK2_EN 0x10 37#define BD70528_REG_BUCK2_VOLT 0x16 38#define BD70528_REG_BUCK3_EN 0x11 39#define BD70528_REG_BUCK3_VOLT 0x17 40#define BD70528_REG_LDO1_EN 0x1b 41#define BD70528_REG_LDO1_VOLT 0x1e 42#define BD70528_REG_LDO2_EN 0x1c 43#define BD70528_REG_LDO2_VOLT 0x1f 44#define BD70528_REG_LDO3_EN 0x1d 45#define BD70528_REG_LDO3_VOLT 0x20 46#define BD70528_REG_LED_CTRL 0x2b 47#define BD70528_REG_LED_VOLT 0x29 48#define BD70528_REG_LED_EN 0x2a 49 50/* main irq registers */ 51#define BD70528_REG_INT_MAIN 0x7E 52#define BD70528_REG_INT_MAIN_MASK 0x74 53 54/* 'sub irq' registers */ 55#define BD70528_REG_INT_SHDN 0x7F 56#define BD70528_REG_INT_PWR_FLT 0x80 57#define BD70528_REG_INT_VR_FLT 0x81 58#define BD70528_REG_INT_MISC 0x82 59#define BD70528_REG_INT_BAT1 0x83 60#define BD70528_REG_INT_BAT2 0x84 61#define BD70528_REG_INT_RTC 0x85 62#define BD70528_REG_INT_GPIO 0x86 63#define BD70528_REG_INT_OP_FAIL 0x87 64 65#define BD70528_REG_INT_SHDN_MASK 0x75 66#define BD70528_REG_INT_PWR_FLT_MASK 0x76 67#define BD70528_REG_INT_VR_FLT_MASK 0x77 68#define BD70528_REG_INT_MISC_MASK 0x78 69#define BD70528_REG_INT_BAT1_MASK 0x79 70#define BD70528_REG_INT_BAT2_MASK 0x7a 71#define BD70528_REG_INT_RTC_MASK 0x7b 72#define BD70528_REG_INT_GPIO_MASK 0x7c 73#define BD70528_REG_INT_OP_FAIL_MASK 0x7d 74 75/* Reset related 'magic' registers */ 76#define BD70528_REG_SHIPMODE 0x03 77#define BD70528_REG_HWRESET 0x04 78#define BD70528_REG_WARMRESET 0x05 79#define BD70528_REG_STANDBY 0x06 80 81/* GPIO registers */ 82#define BD70528_REG_GPIO_STATE 0x8F 83 84#define BD70528_REG_GPIO1_IN 0x4d 85#define BD70528_REG_GPIO2_IN 0x4f 86#define BD70528_REG_GPIO3_IN 0x51 87#define BD70528_REG_GPIO4_IN 0x53 88#define BD70528_REG_GPIO1_OUT 0x4e 89#define BD70528_REG_GPIO2_OUT 0x50 90#define BD70528_REG_GPIO3_OUT 0x52 91#define BD70528_REG_GPIO4_OUT 0x54 92 93/* RTC */ 94 95#define BD70528_REG_RTC_COUNT_H 0x2d 96#define BD70528_REG_RTC_COUNT_L 0x2e 97#define BD70528_REG_RTC_SEC 0x2f 98#define BD70528_REG_RTC_MINUTE 0x30 99#define BD70528_REG_RTC_HOUR 0x31 100#define BD70528_REG_RTC_WEEK 0x32 101#define BD70528_REG_RTC_DAY 0x33 102#define BD70528_REG_RTC_MONTH 0x34 103#define BD70528_REG_RTC_YEAR 0x35 104 105#define BD70528_REG_RTC_ALM_SEC 0x36 106#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC 107#define BD70528_REG_RTC_ALM_MINUTE 0x37 108#define BD70528_REG_RTC_ALM_HOUR 0x38 109#define BD70528_REG_RTC_ALM_WEEK 0x39 110#define BD70528_REG_RTC_ALM_DAY 0x3a 111#define BD70528_REG_RTC_ALM_MONTH 0x3b 112#define BD70528_REG_RTC_ALM_YEAR 0x3c 113#define BD70528_REG_RTC_ALM_MASK 0x3d 114#define BD70528_REG_RTC_ALM_REPEAT 0x3e 115#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC 116 117#define BD70528_REG_RTC_WAKE_SEC 0x43 118#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC 119#define BD70528_REG_RTC_WAKE_MIN 0x44 120#define BD70528_REG_RTC_WAKE_HOUR 0x45 121#define BD70528_REG_RTC_WAKE_CTRL 0x46 122 123#define BD70528_REG_ELAPSED_TIMER_EN 0x42 124#define BD70528_REG_WAKE_EN 0x46 125 126/* WDT registers */ 127#define BD70528_REG_WDT_CTRL 0x4A 128#define BD70528_REG_WDT_HOUR 0x49 129#define BD70528_REG_WDT_MINUTE 0x48 130#define BD70528_REG_WDT_SEC 0x47 131 132/* Charger / Battery */ 133#define BD70528_REG_CHG_CURR_STAT 0x59 134#define BD70528_REG_CHG_BAT_STAT 0x57 135#define BD70528_REG_CHG_BAT_TEMP 0x58 136#define BD70528_REG_CHG_IN_STAT 0x56 137#define BD70528_REG_CHG_DCIN_ILIM 0x5d 138#define BD70528_REG_CHG_CHG_CURR_WARM 0x61 139#define BD70528_REG_CHG_CHG_CURR_COLD 0x62 140 141/* Masks for main IRQ register bits */ 142enum { 143 BD70528_INT_SHDN, 144#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN) 145 BD70528_INT_PWR_FLT, 146#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT) 147 BD70528_INT_VR_FLT, 148#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT) 149 BD70528_INT_MISC, 150#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC) 151 BD70528_INT_BAT1, 152#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1) 153 BD70528_INT_RTC, 154#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC) 155 BD70528_INT_GPIO, 156#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO) 157 BD70528_INT_OP_FAIL, 158#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL) 159}; 160 161/* IRQs */ 162enum { 163 /* Shutdown register IRQs */ 164 BD70528_INT_LONGPUSH, 165 BD70528_INT_WDT, 166 BD70528_INT_HWRESET, 167 BD70528_INT_RSTB_FAULT, 168 BD70528_INT_VBAT_UVLO, 169 BD70528_INT_TSD, 170 BD70528_INT_RSTIN, 171 /* Power failure register IRQs */ 172 BD70528_INT_BUCK1_FAULT, 173 BD70528_INT_BUCK2_FAULT, 174 BD70528_INT_BUCK3_FAULT, 175 BD70528_INT_LDO1_FAULT, 176 BD70528_INT_LDO2_FAULT, 177 BD70528_INT_LDO3_FAULT, 178 BD70528_INT_LED1_FAULT, 179 BD70528_INT_LED2_FAULT, 180 /* VR FAULT register IRQs */ 181 BD70528_INT_BUCK1_OCP, 182 BD70528_INT_BUCK2_OCP, 183 BD70528_INT_BUCK3_OCP, 184 BD70528_INT_LED1_OCP, 185 BD70528_INT_LED2_OCP, 186 BD70528_INT_BUCK1_FULLON, 187 BD70528_INT_BUCK2_FULLON, 188 /* PMU register interrupts */ 189 BD70528_INT_SHORTPUSH, 190 BD70528_INT_AUTO_WAKEUP, 191 BD70528_INT_STATE_CHANGE, 192 /* Charger 1 register IRQs */ 193 BD70528_INT_BAT_OV_RES, 194 BD70528_INT_BAT_OV_DET, 195 BD70528_INT_DBAT_DET, 196 BD70528_INT_BATTSD_COLD_RES, 197 BD70528_INT_BATTSD_COLD_DET, 198 BD70528_INT_BATTSD_HOT_RES, 199 BD70528_INT_BATTSD_HOT_DET, 200 BD70528_INT_CHG_TSD, 201 /* Charger 2 register IRQs */ 202 BD70528_INT_BAT_RMV, 203 BD70528_INT_BAT_DET, 204 BD70528_INT_DCIN2_OV_RES, 205 BD70528_INT_DCIN2_OV_DET, 206 BD70528_INT_DCIN2_RMV, 207 BD70528_INT_DCIN2_DET, 208 BD70528_INT_DCIN1_RMV, 209 BD70528_INT_DCIN1_DET, 210 /* RTC register IRQs */ 211 BD70528_INT_RTC_ALARM, 212 BD70528_INT_ELPS_TIM, 213 /* GPIO register IRQs */ 214 BD70528_INT_GPIO0, 215 BD70528_INT_GPIO1, 216 BD70528_INT_GPIO2, 217 BD70528_INT_GPIO3, 218 /* Invalid operation register IRQs */ 219 BD70528_INT_BUCK1_DVS_OPFAIL, 220 BD70528_INT_BUCK2_DVS_OPFAIL, 221 BD70528_INT_BUCK3_DVS_OPFAIL, 222 BD70528_INT_LED1_VOLT_OPFAIL, 223 BD70528_INT_LED2_VOLT_OPFAIL, 224}; 225 226/* Masks */ 227#define BD70528_INT_LONGPUSH_MASK 0x1 228#define BD70528_INT_WDT_MASK 0x2 229#define BD70528_INT_HWRESET_MASK 0x4 230#define BD70528_INT_RSTB_FAULT_MASK 0x8 231#define BD70528_INT_VBAT_UVLO_MASK 0x10 232#define BD70528_INT_TSD_MASK 0x20 233#define BD70528_INT_RSTIN_MASK 0x40 234 235#define BD70528_INT_BUCK1_FAULT_MASK 0x1 236#define BD70528_INT_BUCK2_FAULT_MASK 0x2 237#define BD70528_INT_BUCK3_FAULT_MASK 0x4 238#define BD70528_INT_LDO1_FAULT_MASK 0x8 239#define BD70528_INT_LDO2_FAULT_MASK 0x10 240#define BD70528_INT_LDO3_FAULT_MASK 0x20 241#define BD70528_INT_LED1_FAULT_MASK 0x40 242#define BD70528_INT_LED2_FAULT_MASK 0x80 243 244#define BD70528_INT_BUCK1_OCP_MASK 0x1 245#define BD70528_INT_BUCK2_OCP_MASK 0x2 246#define BD70528_INT_BUCK3_OCP_MASK 0x4 247#define BD70528_INT_LED1_OCP_MASK 0x8 248#define BD70528_INT_LED2_OCP_MASK 0x10 249#define BD70528_INT_BUCK1_FULLON_MASK 0x20 250#define BD70528_INT_BUCK2_FULLON_MASK 0x40 251 252#define BD70528_INT_SHORTPUSH_MASK 0x1 253#define BD70528_INT_AUTO_WAKEUP_MASK 0x2 254#define BD70528_INT_STATE_CHANGE_MASK 0x10 255 256#define BD70528_INT_BAT_OV_RES_MASK 0x1 257#define BD70528_INT_BAT_OV_DET_MASK 0x2 258#define BD70528_INT_DBAT_DET_MASK 0x4 259#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8 260#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10 261#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20 262#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40 263#define BD70528_INT_CHG_TSD_MASK 0x80 264 265#define BD70528_INT_BAT_RMV_MASK 0x1 266#define BD70528_INT_BAT_DET_MASK 0x2 267#define BD70528_INT_DCIN2_OV_RES_MASK 0x4 268#define BD70528_INT_DCIN2_OV_DET_MASK 0x8 269#define BD70528_INT_DCIN2_RMV_MASK 0x10 270#define BD70528_INT_DCIN2_DET_MASK 0x20 271#define BD70528_INT_DCIN1_RMV_MASK 0x40 272#define BD70528_INT_DCIN1_DET_MASK 0x80 273 274#define BD70528_INT_RTC_ALARM_MASK 0x1 275#define BD70528_INT_ELPS_TIM_MASK 0x2 276 277#define BD70528_INT_GPIO0_MASK 0x1 278#define BD70528_INT_GPIO1_MASK 0x2 279#define BD70528_INT_GPIO2_MASK 0x4 280#define BD70528_INT_GPIO3_MASK 0x8 281 282#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1 283#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2 284#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4 285#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10 286#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20 287 288#define BD70528_DEBOUNCE_MASK 0x3 289 290#define BD70528_DEBOUNCE_DISABLE 0 291#define BD70528_DEBOUNCE_15MS 1 292#define BD70528_DEBOUNCE_30MS 2 293#define BD70528_DEBOUNCE_50MS 3 294 295#define BD70528_GPIO_DRIVE_MASK 0x2 296#define BD70528_GPIO_PUSH_PULL 0x0 297#define BD70528_GPIO_OPEN_DRAIN 0x2 298 299#define BD70528_GPIO_OUT_EN_MASK 0x80 300#define BD70528_GPIO_OUT_ENABLE 0x80 301#define BD70528_GPIO_OUT_DISABLE 0x0 302 303#define BD70528_GPIO_OUT_HI 0x1 304#define BD70528_GPIO_OUT_LO 0x0 305#define BD70528_GPIO_OUT_MASK 0x1 306 307#define BD70528_GPIO_IN_STATE_BASE 1 308 309/* RTC masks to mask out reserved bits */ 310 311#define BD70528_MASK_ELAPSED_TIMER_EN 0x1 312/* Mask second, min and hour fields 313 * HW would support ALM irq for over 24h 314 * (by setting day, month and year too) 315 * but as we wish to keep this same as for 316 * wake-up we limit ALM to 24H and only 317 * unmask sec, min and hour 318 */ 319#define BD70528_MASK_WAKE_EN 0x1 320 321/* WDT masks */ 322#define BD70528_MASK_WDT_EN 0x1 323#define BD70528_MASK_WDT_HOUR 0x1 324#define BD70528_MASK_WDT_MINUTE 0x7f 325#define BD70528_MASK_WDT_SEC 0x7f 326 327#define BD70528_WDT_STATE_BIT 0x1 328#define BD70528_ELAPSED_STATE_BIT 0x2 329#define BD70528_WAKE_STATE_BIT 0x4 330 331/* Charger masks */ 332#define BD70528_MASK_CHG_STAT 0x7f 333#define BD70528_MASK_CHG_BAT_TIMER 0x20 334#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10 335#define BD70528_MASK_CHG_BAT_DETECT 0x1 336#define BD70528_MASK_CHG_DCIN1_UVLO 0x1 337#define BD70528_MASK_CHG_DCIN_ILIM 0x3f 338#define BD70528_MASK_CHG_CHG_CURR 0x1f 339#define BD70528_MASK_CHG_TRICKLE_CURR 0x10 340 341/* 342 * Note, external battery register is the lonely rider at 343 * address 0xc5. See how to stuff that in the regmap 344 */ 345#define BD70528_MAX_REGISTER 0x94 346 347/* Buck control masks */ 348#define BD70528_MASK_RUN_EN 0x4 349#define BD70528_MASK_STBY_EN 0x2 350#define BD70528_MASK_IDLE_EN 0x1 351#define BD70528_MASK_LED1_EN 0x1 352#define BD70528_MASK_LED2_EN 0x10 353 354#define BD70528_MASK_BUCK_VOLT 0xf 355#define BD70528_MASK_LDO_VOLT 0x1f 356#define BD70528_MASK_LED1_VOLT 0x1 357#define BD70528_MASK_LED2_VOLT 0x10 358 359/* Misc irq masks */ 360#define BD70528_INT_MASK_SHORT_PUSH 1 361#define BD70528_INT_MASK_AUTO_WAKE 2 362#define BD70528_INT_MASK_POWER_STATE 4 363 364#define BD70528_MASK_BUCK_RAMP 0x10 365#define BD70528_SIFT_BUCK_RAMP 4 366 367#if IS_ENABLED(CONFIG_BD70528_WATCHDOG) 368 369int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state); 370void bd70528_wdt_lock(struct rohm_regmap_dev *data); 371void bd70528_wdt_unlock(struct rohm_regmap_dev *data); 372 373#else /* CONFIG_BD70528_WATCHDOG */ 374 375static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, 376 int *old_state) 377{ 378 return 0; 379} 380 381static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data) 382{ 383} 384 385static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data) 386{ 387} 388 389#endif /* CONFIG_BD70528_WATCHDOG */ 390 391#endif /* __LINUX_MFD_BD70528_H__ */