tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11 - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17 compatible:
18 oneOf:
19 - items:
20 - enum:
21 - qcom,ipq8074-qusb2-phy
22 - qcom,msm8996-qusb2-phy
23 - qcom,msm8998-qusb2-phy
24 - qcom,sdm660-qusb2-phy
25 - qcom,ipq6018-qusb2-phy
26 - items:
27 - enum:
28 - qcom,sc7180-qusb2-phy
29 - qcom,sdm845-qusb2-phy
30 - const: qcom,qusb2-v2-phy
31 reg:
32 maxItems: 1
33
34 "#phy-cells":
35 const: 0
36
37 clocks:
38 minItems: 2
39 maxItems: 3
40 items:
41 - description: phy config clock
42 - description: 19.2 MHz ref clk
43 - description: phy interface clock (Optional)
44
45 clock-names:
46 minItems: 2
47 maxItems: 3
48 items:
49 - const: cfg_ahb
50 - const: ref
51 - const: iface
52
53 vdda-pll-supply:
54 description:
55 Phandle to 1.8V regulator supply to PHY refclk pll block.
56
57 vdda-phy-dpdm-supply:
58 description:
59 Phandle to 3.1V regulator supply to Dp/Dm port signals.
60
61 resets:
62 maxItems: 1
63 description:
64 Phandle to reset to phy block.
65
66 nvmem-cells:
67 maxItems: 1
68 description:
69 Phandle to nvmem cell that contains 'HS Tx trim'
70 tuning parameter value for qusb2 phy.
71
72 qcom,tcsr-syscon:
73 description:
74 Phandle to TCSR syscon register region.
75 $ref: /schemas/types.yaml#/definitions/phandle
76
77if:
78 properties:
79 compatible:
80 contains:
81 const: qcom,qusb2-v2-phy
82then:
83 properties:
84 qcom,imp-res-offset-value:
85 description:
86 It is a 6 bit value that specifies offset to be
87 added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
88 tuning parameter that may vary for different boards of same SOC.
89 $ref: /schemas/types.yaml#/definitions/uint32
90 minimum: 0
91 maximum: 63
92 default: 0
93
94 qcom,bias-ctrl-value:
95 description:
96 It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
97 tuning parameter that may vary for different boards of same SOC.
98 $ref: /schemas/types.yaml#/definitions/uint32
99 minimum: 0
100 maximum: 63
101 default: 32
102
103 qcom,charge-ctrl-value:
104 description:
105 It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
106 tuning parameter that may vary for different boards of same SOC.
107 $ref: /schemas/types.yaml#/definitions/uint32
108 minimum: 0
109 maximum: 3
110 default: 0
111
112 qcom,hstx-trim-value:
113 description:
114 It is a 4 bit value that specifies tuning for HSTX
115 output current.
116 Possible range is - 15mA to 24mA (stepsize of 600 uA).
117 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
118 $ref: /schemas/types.yaml#/definitions/uint32
119 minimum: 0
120 maximum: 15
121 default: 3
122
123 qcom,preemphasis-level:
124 description:
125 It is a 2 bit value that specifies pre-emphasis level.
126 Possible range is 0 to 15% (stepsize of 5%).
127 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
128 $ref: /schemas/types.yaml#/definitions/uint32
129 minimum: 0
130 maximum: 3
131 default: 2
132
133 qcom,preemphasis-width:
134 description:
135 It is a 1 bit value that specifies how long the HSTX
136 pre-emphasis (specified using qcom,preemphasis-level) must be in
137 effect. Duration could be half-bit of full-bit.
138 See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
139 $ref: /schemas/types.yaml#/definitions/uint32
140 minimum: 0
141 maximum: 1
142 default: 0
143
144 qcom,hsdisc-trim-value:
145 description:
146 It is a 2 bit value tuning parameter that control disconnect
147 threshold and may vary for different boards of same SOC.
148 $ref: /schemas/types.yaml#/definitions/uint32
149 minimum: 0
150 maximum: 3
151 default: 0
152
153required:
154 - compatible
155 - reg
156 - "#phy-cells"
157 - clocks
158 - clock-names
159 - vdda-pll-supply
160 - vdda-phy-dpdm-supply
161 - resets
162
163additionalProperties: false
164
165examples:
166 - |
167 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
168 hsusb_phy: phy@7411000 {
169 compatible = "qcom,msm8996-qusb2-phy";
170 reg = <0x7411000 0x180>;
171 #phy-cells = <0>;
172
173 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
174 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
175 clock-names = "cfg_ahb", "ref";
176
177 vdda-pll-supply = <&pm8994_l12>;
178 vdda-phy-dpdm-supply = <&pm8994_l24>;
179
180 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
181 nvmem-cells = <&qusb2p_hstx_trim>;
182 };