tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2019 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#include <linux/err.h>
17
18#define ZYNQMP_PM_VERSION_MAJOR 1
19#define ZYNQMP_PM_VERSION_MINOR 0
20
21#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
23
24#define ZYNQMP_TZ_VERSION_MAJOR 1
25#define ZYNQMP_TZ_VERSION_MINOR 0
26
27#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
29
30/* SMC SIP service Call Function Identifier Prefix */
31#define PM_SIP_SVC 0xC2000000
32#define PM_GET_TRUSTZONE_VERSION 0xa03
33#define PM_SET_SUSPEND_MODE 0xa02
34#define GET_CALLBACK_DATA 0xa01
35
36/* Number of 32bits values in payload */
37#define PAYLOAD_ARG_CNT 4U
38
39/* Number of arguments for a callback */
40#define CB_ARG_CNT 4
41
42/* Payload size (consists of callback API ID + arguments) */
43#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
44
45#define ZYNQMP_PM_MAX_QOS 100U
46
47#define GSS_NUM_REGS (4)
48
49/* Node capabilities */
50#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
51#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
52#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
53#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
54
55/*
56 * Firmware FPGA Manager flags
57 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
58 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
59 */
60#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
61#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
62
63enum pm_api_id {
64 PM_GET_API_VERSION = 1,
65 PM_SYSTEM_SHUTDOWN = 12,
66 PM_REQUEST_NODE = 13,
67 PM_RELEASE_NODE = 14,
68 PM_SET_REQUIREMENT = 15,
69 PM_RESET_ASSERT = 17,
70 PM_RESET_GET_STATUS = 18,
71 PM_PM_INIT_FINALIZE = 21,
72 PM_FPGA_LOAD = 22,
73 PM_FPGA_GET_STATUS = 23,
74 PM_GET_CHIPID = 24,
75 PM_IOCTL = 34,
76 PM_QUERY_DATA = 35,
77 PM_CLOCK_ENABLE = 36,
78 PM_CLOCK_DISABLE = 37,
79 PM_CLOCK_GETSTATE = 38,
80 PM_CLOCK_SETDIVIDER = 39,
81 PM_CLOCK_GETDIVIDER = 40,
82 PM_CLOCK_SETRATE = 41,
83 PM_CLOCK_GETRATE = 42,
84 PM_CLOCK_SETPARENT = 43,
85 PM_CLOCK_GETPARENT = 44,
86 PM_SECURE_AES = 47,
87 PM_FEATURE_CHECK = 63,
88};
89
90/* PMU-FW return status codes */
91enum pm_ret_status {
92 XST_PM_SUCCESS = 0,
93 XST_PM_NO_FEATURE = 19,
94 XST_PM_INTERNAL = 2000,
95 XST_PM_CONFLICT = 2001,
96 XST_PM_NO_ACCESS = 2002,
97 XST_PM_INVALID_NODE = 2003,
98 XST_PM_DOUBLE_REQ = 2004,
99 XST_PM_ABORT_SUSPEND = 2005,
100 XST_PM_MULT_USER = 2008,
101};
102
103enum pm_ioctl_id {
104 IOCTL_SD_DLL_RESET = 6,
105 IOCTL_SET_SD_TAPDELAY = 7,
106 IOCTL_SET_PLL_FRAC_MODE = 8,
107 IOCTL_GET_PLL_FRAC_MODE = 9,
108 IOCTL_SET_PLL_FRAC_DATA = 10,
109 IOCTL_GET_PLL_FRAC_DATA = 11,
110 IOCTL_WRITE_GGS = 12,
111 IOCTL_READ_GGS = 13,
112 IOCTL_WRITE_PGGS = 14,
113 IOCTL_READ_PGGS = 15,
114 /* Set healthy bit value */
115 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
116};
117
118enum pm_query_id {
119 PM_QID_INVALID = 0,
120 PM_QID_CLOCK_GET_NAME = 1,
121 PM_QID_CLOCK_GET_TOPOLOGY = 2,
122 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
123 PM_QID_CLOCK_GET_PARENTS = 4,
124 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
125 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
126 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
127};
128
129enum zynqmp_pm_reset_action {
130 PM_RESET_ACTION_RELEASE = 0,
131 PM_RESET_ACTION_ASSERT = 1,
132 PM_RESET_ACTION_PULSE = 2,
133};
134
135enum zynqmp_pm_reset {
136 ZYNQMP_PM_RESET_START = 1000,
137 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
138 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
139 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
140 ZYNQMP_PM_RESET_DP = 1003,
141 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
142 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
143 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
144 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
145 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
146 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
147 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
148 ZYNQMP_PM_RESET_GDMA = 1011,
149 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
150 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
151 ZYNQMP_PM_RESET_GPU = 1014,
152 ZYNQMP_PM_RESET_GT = 1015,
153 ZYNQMP_PM_RESET_SATA = 1016,
154 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
155 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
156 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
157 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
158 ZYNQMP_PM_RESET_APU_L2 = 1021,
159 ZYNQMP_PM_RESET_ACPU3 = 1022,
160 ZYNQMP_PM_RESET_ACPU2 = 1023,
161 ZYNQMP_PM_RESET_ACPU1 = 1024,
162 ZYNQMP_PM_RESET_ACPU0 = 1025,
163 ZYNQMP_PM_RESET_DDR = 1026,
164 ZYNQMP_PM_RESET_APM_FPD = 1027,
165 ZYNQMP_PM_RESET_SOFT = 1028,
166 ZYNQMP_PM_RESET_GEM0 = 1029,
167 ZYNQMP_PM_RESET_GEM1 = 1030,
168 ZYNQMP_PM_RESET_GEM2 = 1031,
169 ZYNQMP_PM_RESET_GEM3 = 1032,
170 ZYNQMP_PM_RESET_QSPI = 1033,
171 ZYNQMP_PM_RESET_UART0 = 1034,
172 ZYNQMP_PM_RESET_UART1 = 1035,
173 ZYNQMP_PM_RESET_SPI0 = 1036,
174 ZYNQMP_PM_RESET_SPI1 = 1037,
175 ZYNQMP_PM_RESET_SDIO0 = 1038,
176 ZYNQMP_PM_RESET_SDIO1 = 1039,
177 ZYNQMP_PM_RESET_CAN0 = 1040,
178 ZYNQMP_PM_RESET_CAN1 = 1041,
179 ZYNQMP_PM_RESET_I2C0 = 1042,
180 ZYNQMP_PM_RESET_I2C1 = 1043,
181 ZYNQMP_PM_RESET_TTC0 = 1044,
182 ZYNQMP_PM_RESET_TTC1 = 1045,
183 ZYNQMP_PM_RESET_TTC2 = 1046,
184 ZYNQMP_PM_RESET_TTC3 = 1047,
185 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
186 ZYNQMP_PM_RESET_NAND = 1049,
187 ZYNQMP_PM_RESET_ADMA = 1050,
188 ZYNQMP_PM_RESET_GPIO = 1051,
189 ZYNQMP_PM_RESET_IOU_CC = 1052,
190 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
191 ZYNQMP_PM_RESET_RPU_R50 = 1054,
192 ZYNQMP_PM_RESET_RPU_R51 = 1055,
193 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
194 ZYNQMP_PM_RESET_OCM = 1057,
195 ZYNQMP_PM_RESET_RPU_PGE = 1058,
196 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
197 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
198 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
199 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
200 ZYNQMP_PM_RESET_USB0_APB = 1063,
201 ZYNQMP_PM_RESET_USB1_APB = 1064,
202 ZYNQMP_PM_RESET_IPI = 1065,
203 ZYNQMP_PM_RESET_APM_LPD = 1066,
204 ZYNQMP_PM_RESET_RTC = 1067,
205 ZYNQMP_PM_RESET_SYSMON = 1068,
206 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
207 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
208 ZYNQMP_PM_RESET_FPD = 1071,
209 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
210 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
211 ZYNQMP_PM_RESET_DBG_LPD = 1074,
212 ZYNQMP_PM_RESET_DBG_FPD = 1075,
213 ZYNQMP_PM_RESET_APLL = 1076,
214 ZYNQMP_PM_RESET_DPLL = 1077,
215 ZYNQMP_PM_RESET_VPLL = 1078,
216 ZYNQMP_PM_RESET_IOPLL = 1079,
217 ZYNQMP_PM_RESET_RPLL = 1080,
218 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
219 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
220 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
221 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
222 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
223 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
224 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
225 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
226 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
227 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
228 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
229 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
230 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
231 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
232 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
233 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
234 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
235 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
236 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
237 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
238 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
239 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
240 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
241 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
242 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
243 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
244 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
245 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
246 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
247 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
248 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
249 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
250 ZYNQMP_PM_RESET_RPU_LS = 1113,
251 ZYNQMP_PM_RESET_PS_ONLY = 1114,
252 ZYNQMP_PM_RESET_PL = 1115,
253 ZYNQMP_PM_RESET_PS_PL0 = 1116,
254 ZYNQMP_PM_RESET_PS_PL1 = 1117,
255 ZYNQMP_PM_RESET_PS_PL2 = 1118,
256 ZYNQMP_PM_RESET_PS_PL3 = 1119,
257 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
258};
259
260enum zynqmp_pm_suspend_reason {
261 SUSPEND_POWER_REQUEST = 201,
262 SUSPEND_ALERT = 202,
263 SUSPEND_SYSTEM_SHUTDOWN = 203,
264};
265
266enum zynqmp_pm_request_ack {
267 ZYNQMP_PM_REQUEST_ACK_NO = 1,
268 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
269 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
270};
271
272enum pm_node_id {
273 NODE_SD_0 = 39,
274 NODE_SD_1 = 40,
275};
276
277enum tap_delay_type {
278 PM_TAPDELAY_INPUT = 0,
279 PM_TAPDELAY_OUTPUT = 1,
280};
281
282enum dll_reset_type {
283 PM_DLL_RESET_ASSERT = 0,
284 PM_DLL_RESET_RELEASE = 1,
285 PM_DLL_RESET_PULSE = 2,
286};
287
288enum zynqmp_pm_shutdown_type {
289 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
290 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
291 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
292};
293
294enum zynqmp_pm_shutdown_subtype {
295 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
296 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
297 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
298};
299
300/**
301 * struct zynqmp_pm_query_data - PM query data
302 * @qid: query ID
303 * @arg1: Argument 1 of query data
304 * @arg2: Argument 2 of query data
305 * @arg3: Argument 3 of query data
306 */
307struct zynqmp_pm_query_data {
308 u32 qid;
309 u32 arg1;
310 u32 arg2;
311 u32 arg3;
312};
313
314int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
315 u32 arg2, u32 arg3, u32 *ret_payload);
316
317#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
318int zynqmp_pm_get_api_version(u32 *version);
319int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
320int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
321int zynqmp_pm_clock_enable(u32 clock_id);
322int zynqmp_pm_clock_disable(u32 clock_id);
323int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
324int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
325int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
326int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
327int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
328int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
329int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
330int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
331int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
332int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
333int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
334int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
335int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
336int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
337 const enum zynqmp_pm_reset_action assert_flag);
338int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
339int zynqmp_pm_init_finalize(void);
340int zynqmp_pm_set_suspend_mode(u32 mode);
341int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
342 const u32 qos, const enum zynqmp_pm_request_ack ack);
343int zynqmp_pm_release_node(const u32 node);
344int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
345 const u32 qos,
346 const enum zynqmp_pm_request_ack ack);
347int zynqmp_pm_aes_engine(const u64 address, u32 *out);
348int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
349int zynqmp_pm_fpga_get_status(u32 *value);
350int zynqmp_pm_write_ggs(u32 index, u32 value);
351int zynqmp_pm_read_ggs(u32 index, u32 *value);
352int zynqmp_pm_write_pggs(u32 index, u32 value);
353int zynqmp_pm_read_pggs(u32 index, u32 *value);
354int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
355int zynqmp_pm_set_boot_health_status(u32 value);
356#else
357static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
358{
359 return ERR_PTR(-ENODEV);
360}
361
362static inline int zynqmp_pm_get_api_version(u32 *version)
363{
364 return -ENODEV;
365}
366
367static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
368{
369 return -ENODEV;
370}
371
372static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
373 u32 *out)
374{
375 return -ENODEV;
376}
377
378static inline int zynqmp_pm_clock_enable(u32 clock_id)
379{
380 return -ENODEV;
381}
382
383static inline int zynqmp_pm_clock_disable(u32 clock_id)
384{
385 return -ENODEV;
386}
387
388static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
389{
390 return -ENODEV;
391}
392
393static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
394{
395 return -ENODEV;
396}
397
398static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
399{
400 return -ENODEV;
401}
402
403static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
404{
405 return -ENODEV;
406}
407
408static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
409{
410 return -ENODEV;
411}
412
413static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
414{
415 return -ENODEV;
416}
417
418static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
419{
420 return -ENODEV;
421}
422
423static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
424{
425 return -ENODEV;
426}
427
428static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
429{
430 return -ENODEV;
431}
432
433static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
434{
435 return -ENODEV;
436}
437
438static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
439{
440 return -ENODEV;
441}
442
443static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
444{
445 return -ENODEV;
446}
447
448static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
449{
450 return -ENODEV;
451}
452
453static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
454 const enum zynqmp_pm_reset_action assert_flag)
455{
456 return -ENODEV;
457}
458
459static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
460 u32 *status)
461{
462 return -ENODEV;
463}
464
465static inline int zynqmp_pm_init_finalize(void)
466{
467 return -ENODEV;
468}
469
470static inline int zynqmp_pm_set_suspend_mode(u32 mode)
471{
472 return -ENODEV;
473}
474
475static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
476 const u32 qos,
477 const enum zynqmp_pm_request_ack ack)
478{
479 return -ENODEV;
480}
481
482static inline int zynqmp_pm_release_node(const u32 node)
483{
484 return -ENODEV;
485}
486
487static inline int zynqmp_pm_set_requirement(const u32 node,
488 const u32 capabilities,
489 const u32 qos,
490 const enum zynqmp_pm_request_ack ack)
491{
492 return -ENODEV;
493}
494
495static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
496{
497 return -ENODEV;
498}
499
500static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
501 const u32 flags)
502{
503 return -ENODEV;
504}
505
506static inline int zynqmp_pm_fpga_get_status(u32 *value)
507{
508 return -ENODEV;
509}
510
511static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
512{
513 return -ENODEV;
514}
515
516static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
517{
518 return -ENODEV;
519}
520
521static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
522{
523 return -ENODEV;
524}
525
526static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
527{
528 return -ENODEV;
529}
530
531static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
532{
533 return -ENODEV;
534}
535
536static inline int zynqmp_pm_set_boot_health_status(u32 value)
537{
538 return -ENODEV;
539}
540#endif
541
542#endif /* __FIRMWARE_ZYNQMP_H__ */