tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/of_address.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#include <dt-bindings/phy/phy.h>
24
25#include "phy-qcom-qmp.h"
26
27/* QPHY_SW_RESET bit */
28#define SW_RESET BIT(0)
29/* QPHY_POWER_DOWN_CONTROL */
30#define SW_PWRDN BIT(0)
31#define REFCLK_DRV_DSBL BIT(1)
32/* QPHY_START_CONTROL bits */
33#define SERDES_START BIT(0)
34#define PCS_START BIT(1)
35#define PLL_READY_GATE_EN BIT(3)
36/* QPHY_PCS_STATUS bit */
37#define PHYSTATUS BIT(6)
38/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
39#define PCS_READY BIT(0)
40
41/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
42/* DP PHY soft reset */
43#define SW_DPPHY_RESET BIT(0)
44/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
45#define SW_DPPHY_RESET_MUX BIT(1)
46/* USB3 PHY soft reset */
47#define SW_USB3PHY_RESET BIT(2)
48/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
49#define SW_USB3PHY_RESET_MUX BIT(3)
50
51/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
52#define USB3_MODE BIT(0) /* enables USB3 mode */
53#define DP_MODE BIT(1) /* enables DP mode */
54
55/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
56#define ARCVR_DTCT_EN BIT(0)
57#define ALFPS_DTCT_EN BIT(1)
58#define ARCVR_DTCT_EVENT_SEL BIT(4)
59
60/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
61#define IRQ_CLEAR BIT(0)
62
63/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
64#define RCVR_DETECT BIT(0)
65
66/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
67#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
68
69#define PHY_INIT_COMPLETE_TIMEOUT 10000
70#define POWER_DOWN_DELAY_US_MIN 10
71#define POWER_DOWN_DELAY_US_MAX 11
72
73#define MAX_PROP_NAME 32
74
75/* Define the assumed distance between lanes for underspecified device trees. */
76#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
77
78struct qmp_phy_init_tbl {
79 unsigned int offset;
80 unsigned int val;
81 /*
82 * register part of layout ?
83 * if yes, then offset gives index in the reg-layout
84 */
85 bool in_layout;
86 /*
87 * mask of lanes for which this register is written
88 * for cases when second lane needs different values
89 */
90 u8 lane_mask;
91};
92
93#define QMP_PHY_INIT_CFG(o, v) \
94 { \
95 .offset = o, \
96 .val = v, \
97 .lane_mask = 0xff, \
98 }
99
100#define QMP_PHY_INIT_CFG_L(o, v) \
101 { \
102 .offset = o, \
103 .val = v, \
104 .in_layout = true, \
105 .lane_mask = 0xff, \
106 }
107
108#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
109 { \
110 .offset = o, \
111 .val = v, \
112 .lane_mask = l, \
113 }
114
115/* set of registers with offsets different per-PHY */
116enum qphy_reg_layout {
117 /* Common block control registers */
118 QPHY_COM_SW_RESET,
119 QPHY_COM_POWER_DOWN_CONTROL,
120 QPHY_COM_START_CONTROL,
121 QPHY_COM_PCS_READY_STATUS,
122 /* PCS registers */
123 QPHY_PLL_LOCK_CHK_DLY_TIME,
124 QPHY_FLL_CNTRL1,
125 QPHY_FLL_CNTRL2,
126 QPHY_FLL_CNT_VAL_L,
127 QPHY_FLL_CNT_VAL_H_TOL,
128 QPHY_FLL_MAN_CODE,
129 QPHY_SW_RESET,
130 QPHY_START_CTRL,
131 QPHY_PCS_READY_STATUS,
132 QPHY_PCS_STATUS,
133 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
134 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
135 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
136 QPHY_PCS_POWER_DOWN_CONTROL,
137 /* Keep last to ensure regs_layout arrays are properly initialized */
138 QPHY_LAYOUT_SIZE
139};
140
141static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
142 [QPHY_START_CTRL] = 0x00,
143 [QPHY_PCS_READY_STATUS] = 0x168,
144};
145
146static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
147 [QPHY_COM_SW_RESET] = 0x400,
148 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
149 [QPHY_COM_START_CONTROL] = 0x408,
150 [QPHY_COM_PCS_READY_STATUS] = 0x448,
151 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
152 [QPHY_FLL_CNTRL1] = 0xc4,
153 [QPHY_FLL_CNTRL2] = 0xc8,
154 [QPHY_FLL_CNT_VAL_L] = 0xcc,
155 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
156 [QPHY_FLL_MAN_CODE] = 0xd4,
157 [QPHY_SW_RESET] = 0x00,
158 [QPHY_START_CTRL] = 0x08,
159 [QPHY_PCS_STATUS] = 0x174,
160};
161
162static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
163 [QPHY_FLL_CNTRL1] = 0xc0,
164 [QPHY_FLL_CNTRL2] = 0xc4,
165 [QPHY_FLL_CNT_VAL_L] = 0xc8,
166 [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
167 [QPHY_FLL_MAN_CODE] = 0xd0,
168 [QPHY_SW_RESET] = 0x00,
169 [QPHY_START_CTRL] = 0x08,
170 [QPHY_PCS_STATUS] = 0x17c,
171 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
172 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
173 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
174};
175
176static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
177 [QPHY_SW_RESET] = 0x00,
178 [QPHY_START_CTRL] = 0x08,
179 [QPHY_PCS_STATUS] = 0x174,
180 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
181 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
182 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
183};
184
185static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
186 [QPHY_SW_RESET] = 0x00,
187 [QPHY_START_CTRL] = 0x08,
188 [QPHY_PCS_STATUS] = 0x174,
189};
190
191static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
192 [QPHY_SW_RESET] = 0x00,
193 [QPHY_START_CTRL] = 0x08,
194 [QPHY_PCS_STATUS] = 0x2ac,
195};
196
197static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
198 [QPHY_SW_RESET] = 0x00,
199 [QPHY_START_CTRL] = 0x44,
200 [QPHY_PCS_STATUS] = 0x14,
201 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
202 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
203 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
204};
205
206static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
207 [QPHY_SW_RESET] = 0x00,
208 [QPHY_START_CTRL] = 0x44,
209 [QPHY_PCS_STATUS] = 0x14,
210 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
211 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
212 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
213};
214
215static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
216 [QPHY_SW_RESET] = 0x00,
217 [QPHY_START_CTRL] = 0x44,
218 [QPHY_PCS_STATUS] = 0x14,
219 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
220 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
221 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
222};
223
224static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
225 [QPHY_START_CTRL] = 0x00,
226 [QPHY_PCS_READY_STATUS] = 0x160,
227};
228
229static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
230 [QPHY_SW_RESET] = 0x00,
231 [QPHY_START_CTRL] = 0x44,
232 [QPHY_PCS_STATUS] = 0x14,
233 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
234};
235
236static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
237 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
238 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
239 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
240};
241
242static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
243 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
244 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
245 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
246 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
247 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
248 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
249 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
250 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
251 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
252 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
253 /* PLL and Loop filter settings */
254 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
255 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
256 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
257 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
258 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
259 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
260 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
261 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
262 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
263 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
264 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
265 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
266 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
267 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
268 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
269 /* SSC settings */
270 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
271 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
272 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
273 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
274 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
275 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
276 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
277};
278
279static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
280 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
281 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
282 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
283 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
284 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
285 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
286 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
287 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
288 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
289};
290
291static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
315};
316
317static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
318 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
319 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
320 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
321 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
322 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
323 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
324 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
325 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
326 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
327 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
328 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
329 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
330 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
331 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
332 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
333 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
334 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
335 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
336 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
337 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
338 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
339 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
340 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
341 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
342 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
343 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
344 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
345 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
346 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
349 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
351 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
352 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
353 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
354 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
355 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
356 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
357 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
358 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
359 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
360 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
361};
362
363static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
364 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
365 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
366};
367
368static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
369 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
370 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
371 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
372 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
373 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
374 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
375 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
376 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
377 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
378 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
379};
380
381static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
382 QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
383 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
384 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
385
386 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
387
388 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
389 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
390 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
391 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
392 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
393};
394
395static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
438};
439
440static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
441 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
442 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
443 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
444 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
445};
446
447static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
449 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
450 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
451 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
452 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
453 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
454 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
457 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
458 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
459 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
460 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
462};
463
464static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
475};
476
477static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
478 QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
479 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
480 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
481 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
482 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
483 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
484 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
485 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
486 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
487 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
488 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
489 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
490 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
491 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
492 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
493 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
494 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
495 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
496 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
497 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
498 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
499 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
500 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
501 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
502 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
503 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
504 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
505 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
506 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
507 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
508 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
509 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
510 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
511 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
512 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
513 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
514 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
515 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
516 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
517 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
518 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
519 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
520 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
521 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
522 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
523 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
524 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
525};
526
527static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
528 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
529 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
530};
531
532static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
533 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
534 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
535 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
536 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
537 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
538 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
539 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
540 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
541 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
542 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
543 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
544};
545
546static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
547 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
548 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
549 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
550 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
551 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
552 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
553 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
554 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
555 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
556 /* PLL and Loop filter settings */
557 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
558 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
559 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
560 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
561 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
562 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
563 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
564 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
565 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
566 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
567 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
568 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
569 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
570 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
571 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
572 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
573 /* SSC settings */
574 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
575 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
576 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
577 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
578 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
579 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
580 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
581};
582
583static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
584 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
585 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
586 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
587};
588
589static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
590 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
591 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
592 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
593 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
594 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
595 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
596 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
597 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
598 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
599 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
600};
601
602static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
603 /* FLL settings */
604 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
605 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
606 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
607 QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
608 QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
609
610 /* Lock Det settings */
611 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
612 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
613 QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
614 QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
615};
616
617static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
618 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
619 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
620 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
621 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
622 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
623 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
624 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
625 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
626 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
627 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
628 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
629 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
630 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
631 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
632 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
633 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
634 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
635 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
636 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
637 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
638 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
639 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
640 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
641 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
642 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
643 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
644 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
645 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
646 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
647 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
648 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
649 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
650 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
651 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
652 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
653 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
654 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
655 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
656 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
657 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
658};
659
660static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
661 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
662 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
663 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
664 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
665 QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
666 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
667};
668
669static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
670 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
671 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
672 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
673 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
674 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
675 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
676 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
677};
678
679static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
680 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
681 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
682 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
683 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
684 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
685 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
686 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
687 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
688 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
689 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
690 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
691 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
692 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
693};
694
695static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
696 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
697 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
698 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
699 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
700 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
701 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
702 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
703 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
704 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
705 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
706 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
707 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
708 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
709 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
710 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
711 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
712 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
713 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
714 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
715 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
716 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
717 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
718 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
719 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
720 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
721 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
722 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
723 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
724 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
725 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
726 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
727 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
728 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
729 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
730 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
731 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
732 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
733 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
734 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
735 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
736 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
737 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
738};
739
740static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
741 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
742 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
743 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
744 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
745};
746
747static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
748 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
749 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
750 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
751 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
752 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
753 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
754 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
755 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
756 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
757 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
758 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
759 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
760 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
761 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
762 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
763 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
764};
765
766static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
767 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
768
769 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
770 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
771 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
772 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
773 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
774
775 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
776 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
777 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
778 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
779 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
780 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
781 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
782
783 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
784 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
785 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
786
787 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
788};
789
790static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
791 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
792 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
793 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
794 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
795 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
796};
797
798static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
799 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
800 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
801 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
802 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
803 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
804 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
805 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
806 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
807 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
808 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
809 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
810 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
811 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
812 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
813 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
814 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
815 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
816 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
817 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
818 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
819 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
820 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
821 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
822 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
823 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
824 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
825 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
826 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
827 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
828 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
829 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
830 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
831 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
832 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
833 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
834 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
835 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
836 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
837 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
838 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
839 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
840 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
841 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
842 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
843 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
844};
845
846static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
847 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
848 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
849 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
850 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
851 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
852 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
853 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
854 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
855 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
856 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
857 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
858 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
859 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
860 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
861 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
862 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
863 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
864 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
865 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
866 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
867 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
868 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
869 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
870 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
871 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
872 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
873 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
874 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
875 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
876 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
877 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
878 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
879 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
880 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
881 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
882 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
883 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
884 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
885 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
886 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
887 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
888 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
889 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
890 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
891 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
892 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
893 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
894 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
895 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
896 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
897 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
898 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
899 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
900 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
901 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
902 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
903};
904
905static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
906};
907
908static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
909 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
910 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
911 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
912 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
913 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
914 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
915 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
916};
917
918static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
919 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
920 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
921 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
922 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
923 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
924 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
925 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
926 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
927 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
928 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
929 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
930 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
931 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
932 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
933 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
934 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
935 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
936 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
937 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
938 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
939 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
940 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
941 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
942 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
943 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
944 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
945 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
946 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
947 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
948 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
949 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
950 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
951 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
952 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
953 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
954 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
955};
956
957static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
958 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
959 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
960 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
961 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
962 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
963};
964
965static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
966 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
967 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
968 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
969 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
970 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
971 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
972 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
973 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
974 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
975 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
976 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
977 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
978 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
979 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
980 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
981 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
982 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
983 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
984 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
985 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
986 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
987};
988
989static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
990 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
991 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
992 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
993 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
994 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
995 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
996 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
997};
998
999static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
1000 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
1001 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1002 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1003 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1004 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
1005 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
1006 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1007};
1008
1009static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
1010 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1011 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1012 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1013 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1014 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1015 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1016 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1017};
1018
1019static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1020 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1021 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1022 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1023 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1024 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1025 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1026 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1027};
1028
1029static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1030 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1031 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1032 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1033 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1034 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1035 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1036 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1037 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1038 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1039 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1040 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1041 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1042 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1043 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1044 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1045};
1046
1047static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1048 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1049 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1050 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1051 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1052 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1053 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1054 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1055 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1056 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1057};
1058
1059static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1060 /* FLL settings */
1061 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1062 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1063 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1064 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1065 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1066
1067 /* Lock Det settings */
1068 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1069 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1070 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1071 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1072
1073 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1074 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1075 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1076 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1077 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1078 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1079 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1080 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1081 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1082 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1083 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1084 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1085 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1086 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1087 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1088 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1089 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1090 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1091 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1092
1093 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1094 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1095 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1096 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1097 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1098 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1099 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1100 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1101 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1102 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1103 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1104};
1105
1106static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1143};
1144
1145static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1146 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1147 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1148 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1149 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1150 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1151};
1152
1153static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1159 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1160 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1161 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1162 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1163 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1164 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1165};
1166
1167static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1168 /* FLL settings */
1169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1174
1175 /* Lock Det settings */
1176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1180
1181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1200
1201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1212
1213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1215};
1216
1217static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1254
1255 /* Rate B */
1256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1257};
1258
1259static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1260 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1263};
1264
1265static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1266 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1267 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1268 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1269 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1270 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1271 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1272 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1273 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1278 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1279 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1280 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1281 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1282};
1283
1284static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1293};
1294
1295static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1329 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1330 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1331 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1332 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1333 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1334};
1335
1336static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1341};
1342
1343static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1344 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1345 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1346 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1347 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1348 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1349 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1351 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1352 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1353 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1354 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1359 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1360 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1361};
1362
1363static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1402};
1403
1404static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1405 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1406 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1407 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1408 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1409 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1410 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1411 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1412 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1413 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1414 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1415 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1416 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1417 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1418 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1419 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1420 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1421 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1422 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1423 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1424 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1425 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1426 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1427 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1428 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1429
1430 /* Rate B */
1431 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1432};
1433
1434static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1435 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1436 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1437 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1438 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1439 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1440 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1441};
1442
1443static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1478
1479};
1480
1481static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1489};
1490
1491static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1516 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1517 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1518 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1519 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1520 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1532};
1533
1534static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1535 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1536 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1537 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1538 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1539 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1540};
1541
1542static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1561 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1562 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1563 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1564 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1565 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1566 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1567 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1579};
1580
1581static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1582 /* Lock Det settings */
1583 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1584 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1585 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1586
1587 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1588 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1589 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1590 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1591 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1592 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1593 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1594 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1595 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1596 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1597};
1598
1599static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1601 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1602 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1603 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1604 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1605 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1606 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1607 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1608 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1640};
1641
1642static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1643 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1644 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1645 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1646 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1647};
1648
1649static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1686};
1687
1688static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1696 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1705};
1706
1707static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1708 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1709 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1710 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1711 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1712 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1713 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1714 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1715 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1716};
1717
1718static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1720 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1721 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1722 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1723 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1724 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1725 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1726 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1727 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1734 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1735 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1736 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1737 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1738 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1739 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1740 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1741 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1742 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1743 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1744 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1745 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1746 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1747 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1748 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1749 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1750 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1751 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1752 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1757};
1758
1759static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1760 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1762 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1763 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1764 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1765 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1766 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1767 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1769 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1770 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1771 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1772 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1773 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1774};
1775
1776static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
1777 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1778 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1779 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
1780 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1781 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1782 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1783};
1784
1785static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
1786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
1788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
1806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1822};
1823
1824static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
1825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1827 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1838 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1840 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1841};
1842
1843static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
1844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
1849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
1851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
1852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1885};
1886
1887static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1889};
1890
1891static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1892 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1893 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1894 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1895};
1896
1897static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1898 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1899 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1900 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1901 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1902 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1903 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1905 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1906 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1909 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1928};
1929
1930static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1937};
1938
1939static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1940 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1941 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1942 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1943};
1944
1945static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1946 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1947 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1948};
1949
1950static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1951 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1952 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1953 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1954 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1957 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1958};
1959
1960static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1963};
1964
1965static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1966 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1967};
1968
1969static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1970 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1971 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1972 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1973 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1974};
1975
1976static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1977 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1978 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1979};
1980
1981static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1982 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1983 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1984};
1985
1986static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
1987 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1988 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1989 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
1990 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1991 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
1992};
1993
1994static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
1995 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
1996 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
2007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
2009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
2010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
2015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2027 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
2029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2031};
2032
2033static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
2034 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
2035 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
2036 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2037 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2038 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2039 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2040 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
2041 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2042 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2043 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
2044 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
2045 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
2046 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2047 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
2048 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
2049 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2050 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
2051 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
2052 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
2053 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
2054 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
2055 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
2056 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
2057 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
2058
2059 /* Rate B */
2060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
2061};
2062
2063static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
2064 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
2065 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
2066 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
2067 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
2068 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
2069 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2070 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
2071 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
2072 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
2073};
2074
2075static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
2076 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
2077 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
2078 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2079 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
2080 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
2081 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
2082 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
2083 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
2084 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
2085 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
2086 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
2087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
2088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
2090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
2091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
2092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
2094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
2095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
2098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
2099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
2100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
2101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
2102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
2103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
2104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
2105 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
2106 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
2107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
2108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
2109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
2110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
2111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
2112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2113};
2114
2115static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
2116 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
2117 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
2118 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
2119 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
2120 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
2121 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
2122 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
2123 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
2124 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
2125 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
2126 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
2127 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
2128 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
2129 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
2130 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
2131};
2132
2133static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
2134 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
2135 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
2136 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2137 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2138 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
2139 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2140 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
2141 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
2142 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
2143 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2144};
2145
2146static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
2147 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2148 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2149 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2151 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2157 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
2169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
2170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
2171 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
2172 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
2173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
2177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
2178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
2180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
2185};
2186
2187static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
2188 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
2189 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
2190 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2191 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2192 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2193 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2194 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2195 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2196 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2197 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2198 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2199 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2200 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2201 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2202 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2204 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2205 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
2206};
2207
2208static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
2209 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2210 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2211 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2212 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2213 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2214 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
2215 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2216};
2217
2218static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
2219 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
2220 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2221 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2222 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2223 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2224 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2225 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2226 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2227 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2228 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2229 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2230 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2231 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2232 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2233 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2234 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2235 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2236 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2237 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2238 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2239 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2240 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2241 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2242 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2243 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2244 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2245 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2246 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2247 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2248 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2249 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2250};
2251
2252static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
2253 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2254 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2255 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2256 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2257 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2258 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2259 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2260 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2261 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2262 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2263 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2264 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2265 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2266 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2267 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2268 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2269};
2270
2271/* struct qmp_phy_cfg - per-PHY initialization config */
2272struct qmp_phy_cfg {
2273 /* phy-type - PCIE/UFS/USB */
2274 unsigned int type;
2275 /* number of lanes provided by phy */
2276 int nlanes;
2277
2278 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
2279 const struct qmp_phy_init_tbl *serdes_tbl;
2280 int serdes_tbl_num;
2281 const struct qmp_phy_init_tbl *serdes_tbl_sec;
2282 int serdes_tbl_num_sec;
2283 const struct qmp_phy_init_tbl *tx_tbl;
2284 int tx_tbl_num;
2285 const struct qmp_phy_init_tbl *tx_tbl_sec;
2286 int tx_tbl_num_sec;
2287 const struct qmp_phy_init_tbl *rx_tbl;
2288 int rx_tbl_num;
2289 const struct qmp_phy_init_tbl *rx_tbl_sec;
2290 int rx_tbl_num_sec;
2291 const struct qmp_phy_init_tbl *pcs_tbl;
2292 int pcs_tbl_num;
2293 const struct qmp_phy_init_tbl *pcs_tbl_sec;
2294 int pcs_tbl_num_sec;
2295 const struct qmp_phy_init_tbl *pcs_misc_tbl;
2296 int pcs_misc_tbl_num;
2297 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
2298 int pcs_misc_tbl_num_sec;
2299
2300 /* Init sequence for DP PHY block link rates */
2301 const struct qmp_phy_init_tbl *serdes_tbl_rbr;
2302 int serdes_tbl_rbr_num;
2303 const struct qmp_phy_init_tbl *serdes_tbl_hbr;
2304 int serdes_tbl_hbr_num;
2305 const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
2306 int serdes_tbl_hbr2_num;
2307 const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
2308 int serdes_tbl_hbr3_num;
2309
2310 /* clock ids to be requested */
2311 const char * const *clk_list;
2312 int num_clks;
2313 /* resets to be requested */
2314 const char * const *reset_list;
2315 int num_resets;
2316 /* regulators to be requested */
2317 const char * const *vreg_list;
2318 int num_vregs;
2319
2320 /* array of registers with different offsets */
2321 const unsigned int *regs;
2322
2323 unsigned int start_ctrl;
2324 unsigned int pwrdn_ctrl;
2325 unsigned int mask_com_pcs_ready;
2326
2327 /* true, if PHY has a separate PHY_COM control block */
2328 bool has_phy_com_ctrl;
2329 /* true, if PHY has a reset for individual lanes */
2330 bool has_lane_rst;
2331 /* true, if PHY needs delay after POWER_DOWN */
2332 bool has_pwrdn_delay;
2333 /* power_down delay in usec */
2334 int pwrdn_delay_min;
2335 int pwrdn_delay_max;
2336
2337 /* true, if PHY has a separate DP_COM control block */
2338 bool has_phy_dp_com_ctrl;
2339 /* true, if PHY has secondary tx/rx lanes to be configured */
2340 bool is_dual_lane_phy;
2341
2342 /* true, if PCS block has no separate SW_RESET register */
2343 bool no_pcs_sw_reset;
2344};
2345
2346struct qmp_phy_combo_cfg {
2347 const struct qmp_phy_cfg *usb_cfg;
2348 const struct qmp_phy_cfg *dp_cfg;
2349};
2350
2351/**
2352 * struct qmp_phy - per-lane phy descriptor
2353 *
2354 * @phy: generic phy
2355 * @cfg: phy specific configuration
2356 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
2357 * @tx: iomapped memory space for lane's tx
2358 * @rx: iomapped memory space for lane's rx
2359 * @pcs: iomapped memory space for lane's pcs
2360 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
2361 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
2362 * @pcs_misc: iomapped memory space for lane's pcs_misc
2363 * @pipe_clk: pipe lock
2364 * @index: lane index
2365 * @qmp: QMP phy to which this lane belongs
2366 * @lane_rst: lane's reset controller
2367 * @mode: current PHY mode
2368 */
2369struct qmp_phy {
2370 struct phy *phy;
2371 const struct qmp_phy_cfg *cfg;
2372 void __iomem *serdes;
2373 void __iomem *tx;
2374 void __iomem *rx;
2375 void __iomem *pcs;
2376 void __iomem *tx2;
2377 void __iomem *rx2;
2378 void __iomem *pcs_misc;
2379 struct clk *pipe_clk;
2380 unsigned int index;
2381 struct qcom_qmp *qmp;
2382 struct reset_control *lane_rst;
2383 enum phy_mode mode;
2384 unsigned int dp_aux_cfg;
2385 struct phy_configure_opts_dp dp_opts;
2386 struct qmp_phy_dp_clks *dp_clks;
2387};
2388
2389struct qmp_phy_dp_clks {
2390 struct qmp_phy *qphy;
2391 struct clk_hw dp_link_hw;
2392 struct clk_hw dp_pixel_hw;
2393};
2394
2395/**
2396 * struct qcom_qmp - structure holding QMP phy block attributes
2397 *
2398 * @dev: device
2399 * @dp_com: iomapped memory space for phy's dp_com control block
2400 *
2401 * @clks: array of clocks required by phy
2402 * @resets: array of resets required by phy
2403 * @vregs: regulator supplies bulk data
2404 *
2405 * @phys: array of per-lane phy descriptors
2406 * @phy_mutex: mutex lock for PHY common block initialization
2407 * @init_count: phy common block initialization count
2408 * @ufs_reset: optional UFS PHY reset handle
2409 */
2410struct qcom_qmp {
2411 struct device *dev;
2412 void __iomem *dp_com;
2413
2414 struct clk_bulk_data *clks;
2415 struct reset_control **resets;
2416 struct regulator_bulk_data *vregs;
2417
2418 struct qmp_phy **phys;
2419
2420 struct mutex phy_mutex;
2421 int init_count;
2422
2423 struct reset_control *ufs_reset;
2424};
2425
2426static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
2427{
2428 u32 reg;
2429
2430 reg = readl(base + offset);
2431 reg |= val;
2432 writel(reg, base + offset);
2433
2434 /* ensure that above write is through */
2435 readl(base + offset);
2436}
2437
2438static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
2439{
2440 u32 reg;
2441
2442 reg = readl(base + offset);
2443 reg &= ~val;
2444 writel(reg, base + offset);
2445
2446 /* ensure that above write is through */
2447 readl(base + offset);
2448}
2449
2450/* list of clocks required by phy */
2451static const char * const msm8996_phy_clk_l[] = {
2452 "aux", "cfg_ahb", "ref",
2453};
2454
2455static const char * const msm8996_ufs_phy_clk_l[] = {
2456 "ref",
2457};
2458
2459static const char * const qmp_v3_phy_clk_l[] = {
2460 "aux", "cfg_ahb", "ref", "com_aux",
2461};
2462
2463static const char * const sdm845_pciephy_clk_l[] = {
2464 "aux", "cfg_ahb", "ref", "refgen",
2465};
2466
2467static const char * const qmp_v4_phy_clk_l[] = {
2468 "aux", "ref_clk_src", "ref", "com_aux",
2469};
2470
2471/* the primary usb3 phy on sm8250 doesn't have a ref clock */
2472static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
2473 "aux", "ref_clk_src", "com_aux"
2474};
2475
2476static const char * const sdm845_ufs_phy_clk_l[] = {
2477 "ref", "ref_aux",
2478};
2479
2480/* usb3 phy on sdx55 doesn't have com_aux clock */
2481static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
2482 "aux", "cfg_ahb", "ref"
2483};
2484
2485/* list of resets */
2486static const char * const msm8996_pciephy_reset_l[] = {
2487 "phy", "common", "cfg",
2488};
2489
2490static const char * const msm8996_usb3phy_reset_l[] = {
2491 "phy", "common",
2492};
2493
2494static const char * const sc7180_usb3phy_reset_l[] = {
2495 "phy",
2496};
2497
2498static const char * const sdm845_pciephy_reset_l[] = {
2499 "phy",
2500};
2501
2502/* list of regulators */
2503static const char * const qmp_phy_vreg_l[] = {
2504 "vdda-phy", "vdda-pll",
2505};
2506
2507static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
2508 .type = PHY_TYPE_USB3,
2509 .nlanes = 1,
2510
2511 .serdes_tbl = ipq8074_usb3_serdes_tbl,
2512 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
2513 .tx_tbl = msm8996_usb3_tx_tbl,
2514 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
2515 .rx_tbl = ipq8074_usb3_rx_tbl,
2516 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
2517 .pcs_tbl = ipq8074_usb3_pcs_tbl,
2518 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
2519 .clk_list = msm8996_phy_clk_l,
2520 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2521 .reset_list = msm8996_usb3phy_reset_l,
2522 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2523 .vreg_list = qmp_phy_vreg_l,
2524 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2525 .regs = usb3phy_regs_layout,
2526
2527 .start_ctrl = SERDES_START | PCS_START,
2528 .pwrdn_ctrl = SW_PWRDN,
2529};
2530
2531static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
2532 .type = PHY_TYPE_PCIE,
2533 .nlanes = 3,
2534
2535 .serdes_tbl = msm8996_pcie_serdes_tbl,
2536 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
2537 .tx_tbl = msm8996_pcie_tx_tbl,
2538 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
2539 .rx_tbl = msm8996_pcie_rx_tbl,
2540 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
2541 .pcs_tbl = msm8996_pcie_pcs_tbl,
2542 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
2543 .clk_list = msm8996_phy_clk_l,
2544 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2545 .reset_list = msm8996_pciephy_reset_l,
2546 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
2547 .vreg_list = qmp_phy_vreg_l,
2548 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2549 .regs = pciephy_regs_layout,
2550
2551 .start_ctrl = PCS_START | PLL_READY_GATE_EN,
2552 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2553 .mask_com_pcs_ready = PCS_READY,
2554
2555 .has_phy_com_ctrl = true,
2556 .has_lane_rst = true,
2557 .has_pwrdn_delay = true,
2558 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
2559 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
2560};
2561
2562static const struct qmp_phy_cfg msm8996_ufs_cfg = {
2563 .type = PHY_TYPE_UFS,
2564 .nlanes = 1,
2565
2566 .serdes_tbl = msm8996_ufs_serdes_tbl,
2567 .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
2568 .tx_tbl = msm8996_ufs_tx_tbl,
2569 .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
2570 .rx_tbl = msm8996_ufs_rx_tbl,
2571 .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
2572
2573 .clk_list = msm8996_ufs_phy_clk_l,
2574 .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
2575
2576 .vreg_list = qmp_phy_vreg_l,
2577 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2578
2579 .regs = msm8996_ufsphy_regs_layout,
2580
2581 .start_ctrl = SERDES_START,
2582 .pwrdn_ctrl = SW_PWRDN,
2583
2584 .no_pcs_sw_reset = true,
2585};
2586
2587static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
2588 .type = PHY_TYPE_USB3,
2589 .nlanes = 1,
2590
2591 .serdes_tbl = msm8996_usb3_serdes_tbl,
2592 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
2593 .tx_tbl = msm8996_usb3_tx_tbl,
2594 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
2595 .rx_tbl = msm8996_usb3_rx_tbl,
2596 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
2597 .pcs_tbl = msm8996_usb3_pcs_tbl,
2598 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
2599 .clk_list = msm8996_phy_clk_l,
2600 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2601 .reset_list = msm8996_usb3phy_reset_l,
2602 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2603 .vreg_list = qmp_phy_vreg_l,
2604 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2605 .regs = usb3phy_regs_layout,
2606
2607 .start_ctrl = SERDES_START | PCS_START,
2608 .pwrdn_ctrl = SW_PWRDN,
2609};
2610
2611static const char * const ipq8074_pciephy_clk_l[] = {
2612 "aux", "cfg_ahb",
2613};
2614/* list of resets */
2615static const char * const ipq8074_pciephy_reset_l[] = {
2616 "phy", "common",
2617};
2618
2619static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
2620 .type = PHY_TYPE_PCIE,
2621 .nlanes = 1,
2622
2623 .serdes_tbl = ipq8074_pcie_serdes_tbl,
2624 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
2625 .tx_tbl = ipq8074_pcie_tx_tbl,
2626 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
2627 .rx_tbl = ipq8074_pcie_rx_tbl,
2628 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
2629 .pcs_tbl = ipq8074_pcie_pcs_tbl,
2630 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
2631 .clk_list = ipq8074_pciephy_clk_l,
2632 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
2633 .reset_list = ipq8074_pciephy_reset_l,
2634 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2635 .vreg_list = NULL,
2636 .num_vregs = 0,
2637 .regs = pciephy_regs_layout,
2638
2639 .start_ctrl = SERDES_START | PCS_START,
2640 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2641
2642 .has_phy_com_ctrl = false,
2643 .has_lane_rst = false,
2644 .has_pwrdn_delay = true,
2645 .pwrdn_delay_min = 995, /* us */
2646 .pwrdn_delay_max = 1005, /* us */
2647};
2648
2649static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2650 .type = PHY_TYPE_PCIE,
2651 .nlanes = 1,
2652
2653 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
2654 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
2655 .tx_tbl = sdm845_qmp_pcie_tx_tbl,
2656 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
2657 .rx_tbl = sdm845_qmp_pcie_rx_tbl,
2658 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
2659 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
2660 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
2661 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
2662 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
2663 .clk_list = sdm845_pciephy_clk_l,
2664 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2665 .reset_list = sdm845_pciephy_reset_l,
2666 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2667 .vreg_list = qmp_phy_vreg_l,
2668 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2669 .regs = sdm845_qmp_pciephy_regs_layout,
2670
2671 .start_ctrl = PCS_START | SERDES_START,
2672 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2673
2674 .has_pwrdn_delay = true,
2675 .pwrdn_delay_min = 995, /* us */
2676 .pwrdn_delay_max = 1005, /* us */
2677};
2678
2679static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
2680 .type = PHY_TYPE_PCIE,
2681 .nlanes = 1,
2682
2683 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
2684 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2685 .tx_tbl = sdm845_qhp_pcie_tx_tbl,
2686 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2687 .rx_tbl = sdm845_qhp_pcie_rx_tbl,
2688 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
2689 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
2690 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2691 .clk_list = sdm845_pciephy_clk_l,
2692 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2693 .reset_list = sdm845_pciephy_reset_l,
2694 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2695 .vreg_list = qmp_phy_vreg_l,
2696 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2697 .regs = sdm845_qhp_pciephy_regs_layout,
2698
2699 .start_ctrl = PCS_START | SERDES_START,
2700 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2701
2702 .has_pwrdn_delay = true,
2703 .pwrdn_delay_min = 995, /* us */
2704 .pwrdn_delay_max = 1005, /* us */
2705};
2706
2707static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
2708 .type = PHY_TYPE_PCIE,
2709 .nlanes = 1,
2710
2711 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
2712 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2713 .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
2714 .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
2715 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
2716 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2717 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
2718 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2719 .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
2720 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
2721 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
2722 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2723 .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
2724 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
2725 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
2726 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2727 .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
2728 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
2729 .clk_list = sdm845_pciephy_clk_l,
2730 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2731 .reset_list = sdm845_pciephy_reset_l,
2732 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2733 .vreg_list = qmp_phy_vreg_l,
2734 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2735 .regs = sm8250_pcie_regs_layout,
2736
2737 .start_ctrl = PCS_START | SERDES_START,
2738 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2739
2740 .has_pwrdn_delay = true,
2741 .pwrdn_delay_min = 995, /* us */
2742 .pwrdn_delay_max = 1005, /* us */
2743};
2744
2745static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
2746 .type = PHY_TYPE_PCIE,
2747 .nlanes = 2,
2748
2749 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
2750 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2751 .tx_tbl = sm8250_qmp_pcie_tx_tbl,
2752 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2753 .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
2754 .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
2755 .rx_tbl = sm8250_qmp_pcie_rx_tbl,
2756 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2757 .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
2758 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
2759 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
2760 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2761 .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
2762 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
2763 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
2764 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2765 .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
2766 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
2767 .clk_list = sdm845_pciephy_clk_l,
2768 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
2769 .reset_list = sdm845_pciephy_reset_l,
2770 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2771 .vreg_list = qmp_phy_vreg_l,
2772 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2773 .regs = sm8250_pcie_regs_layout,
2774
2775 .start_ctrl = PCS_START | SERDES_START,
2776 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2777
2778 .is_dual_lane_phy = true,
2779 .has_pwrdn_delay = true,
2780 .pwrdn_delay_min = 995, /* us */
2781 .pwrdn_delay_max = 1005, /* us */
2782};
2783
2784static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
2785 .type = PHY_TYPE_USB3,
2786 .nlanes = 1,
2787
2788 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
2789 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2790 .tx_tbl = qmp_v3_usb3_tx_tbl,
2791 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2792 .rx_tbl = qmp_v3_usb3_rx_tbl,
2793 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2794 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
2795 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2796 .clk_list = qmp_v3_phy_clk_l,
2797 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
2798 .reset_list = msm8996_usb3phy_reset_l,
2799 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2800 .vreg_list = qmp_phy_vreg_l,
2801 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2802 .regs = qmp_v3_usb3phy_regs_layout,
2803
2804 .start_ctrl = SERDES_START | PCS_START,
2805 .pwrdn_ctrl = SW_PWRDN,
2806
2807 .has_pwrdn_delay = true,
2808 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
2809 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
2810
2811 .has_phy_dp_com_ctrl = true,
2812 .is_dual_lane_phy = true,
2813};
2814
2815static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
2816 .type = PHY_TYPE_USB3,
2817 .nlanes = 1,
2818
2819 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
2820 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2821 .tx_tbl = qmp_v3_usb3_tx_tbl,
2822 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2823 .rx_tbl = qmp_v3_usb3_rx_tbl,
2824 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2825 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
2826 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2827 .clk_list = qmp_v3_phy_clk_l,
2828 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
2829 .reset_list = sc7180_usb3phy_reset_l,
2830 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
2831 .vreg_list = qmp_phy_vreg_l,
2832 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2833 .regs = qmp_v3_usb3phy_regs_layout,
2834
2835 .start_ctrl = SERDES_START | PCS_START,
2836 .pwrdn_ctrl = SW_PWRDN,
2837
2838 .has_pwrdn_delay = true,
2839 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
2840 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
2841
2842 .has_phy_dp_com_ctrl = true,
2843 .is_dual_lane_phy = true,
2844};
2845
2846static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
2847 .type = PHY_TYPE_DP,
2848 .nlanes = 1,
2849
2850 .serdes_tbl = qmp_v3_dp_serdes_tbl,
2851 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
2852 .tx_tbl = qmp_v3_dp_tx_tbl,
2853 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
2854
2855 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
2856 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
2857 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
2858 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
2859 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
2860 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
2861 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
2862 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
2863
2864 .clk_list = qmp_v3_phy_clk_l,
2865 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
2866 .reset_list = sc7180_usb3phy_reset_l,
2867 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
2868 .vreg_list = qmp_phy_vreg_l,
2869 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2870 .regs = qmp_v3_usb3phy_regs_layout,
2871
2872 .has_phy_dp_com_ctrl = true,
2873 .is_dual_lane_phy = true,
2874};
2875
2876static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
2877 .usb_cfg = &sc7180_usb3phy_cfg,
2878 .dp_cfg = &sc7180_dpphy_cfg,
2879};
2880
2881static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
2882 .type = PHY_TYPE_USB3,
2883 .nlanes = 1,
2884
2885 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
2886 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
2887 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
2888 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
2889 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
2890 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
2891 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
2892 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
2893 .clk_list = qmp_v3_phy_clk_l,
2894 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
2895 .reset_list = msm8996_usb3phy_reset_l,
2896 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2897 .vreg_list = qmp_phy_vreg_l,
2898 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2899 .regs = qmp_v3_usb3phy_regs_layout,
2900
2901 .start_ctrl = SERDES_START | PCS_START,
2902 .pwrdn_ctrl = SW_PWRDN,
2903
2904 .has_pwrdn_delay = true,
2905 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
2906 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
2907};
2908
2909static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
2910 .type = PHY_TYPE_UFS,
2911 .nlanes = 2,
2912
2913 .serdes_tbl = sdm845_ufsphy_serdes_tbl,
2914 .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
2915 .tx_tbl = sdm845_ufsphy_tx_tbl,
2916 .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
2917 .rx_tbl = sdm845_ufsphy_rx_tbl,
2918 .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
2919 .pcs_tbl = sdm845_ufsphy_pcs_tbl,
2920 .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
2921 .clk_list = sdm845_ufs_phy_clk_l,
2922 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2923 .vreg_list = qmp_phy_vreg_l,
2924 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2925 .regs = sdm845_ufsphy_regs_layout,
2926
2927 .start_ctrl = SERDES_START,
2928 .pwrdn_ctrl = SW_PWRDN,
2929
2930 .is_dual_lane_phy = true,
2931 .no_pcs_sw_reset = true,
2932};
2933
2934static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
2935 .type = PHY_TYPE_PCIE,
2936 .nlanes = 1,
2937
2938 .serdes_tbl = msm8998_pcie_serdes_tbl,
2939 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
2940 .tx_tbl = msm8998_pcie_tx_tbl,
2941 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
2942 .rx_tbl = msm8998_pcie_rx_tbl,
2943 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
2944 .pcs_tbl = msm8998_pcie_pcs_tbl,
2945 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
2946 .clk_list = msm8996_phy_clk_l,
2947 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2948 .reset_list = ipq8074_pciephy_reset_l,
2949 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2950 .vreg_list = qmp_phy_vreg_l,
2951 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2952 .regs = pciephy_regs_layout,
2953
2954 .start_ctrl = SERDES_START | PCS_START,
2955 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2956};
2957
2958static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
2959 .type = PHY_TYPE_USB3,
2960 .nlanes = 1,
2961
2962 .serdes_tbl = msm8998_usb3_serdes_tbl,
2963 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
2964 .tx_tbl = msm8998_usb3_tx_tbl,
2965 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
2966 .rx_tbl = msm8998_usb3_rx_tbl,
2967 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
2968 .pcs_tbl = msm8998_usb3_pcs_tbl,
2969 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
2970 .clk_list = msm8996_phy_clk_l,
2971 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
2972 .reset_list = msm8996_usb3phy_reset_l,
2973 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2974 .vreg_list = qmp_phy_vreg_l,
2975 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2976 .regs = qmp_v3_usb3phy_regs_layout,
2977
2978 .start_ctrl = SERDES_START | PCS_START,
2979 .pwrdn_ctrl = SW_PWRDN,
2980
2981 .is_dual_lane_phy = true,
2982};
2983
2984static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
2985 .type = PHY_TYPE_UFS,
2986 .nlanes = 2,
2987
2988 .serdes_tbl = sm8150_ufsphy_serdes_tbl,
2989 .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
2990 .tx_tbl = sm8150_ufsphy_tx_tbl,
2991 .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
2992 .rx_tbl = sm8150_ufsphy_rx_tbl,
2993 .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
2994 .pcs_tbl = sm8150_ufsphy_pcs_tbl,
2995 .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
2996 .clk_list = sdm845_ufs_phy_clk_l,
2997 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2998 .vreg_list = qmp_phy_vreg_l,
2999 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3000 .regs = sm8150_ufsphy_regs_layout,
3001
3002 .start_ctrl = SERDES_START,
3003 .pwrdn_ctrl = SW_PWRDN,
3004
3005 .is_dual_lane_phy = true,
3006};
3007
3008static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
3009 .type = PHY_TYPE_USB3,
3010 .nlanes = 1,
3011
3012 .serdes_tbl = sm8150_usb3_serdes_tbl,
3013 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3014 .tx_tbl = sm8150_usb3_tx_tbl,
3015 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
3016 .rx_tbl = sm8150_usb3_rx_tbl,
3017 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
3018 .pcs_tbl = sm8150_usb3_pcs_tbl,
3019 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
3020 .clk_list = qmp_v4_phy_clk_l,
3021 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3022 .reset_list = msm8996_usb3phy_reset_l,
3023 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3024 .vreg_list = qmp_phy_vreg_l,
3025 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3026 .regs = qmp_v4_usb3phy_regs_layout,
3027
3028 .start_ctrl = SERDES_START | PCS_START,
3029 .pwrdn_ctrl = SW_PWRDN,
3030
3031 .has_pwrdn_delay = true,
3032 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3033 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3034
3035 .has_phy_dp_com_ctrl = true,
3036 .is_dual_lane_phy = true,
3037};
3038
3039static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
3040 .type = PHY_TYPE_USB3,
3041 .nlanes = 1,
3042
3043 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3044 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3045 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
3046 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
3047 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
3048 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
3049 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
3050 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
3051 .clk_list = qmp_v4_phy_clk_l,
3052 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3053 .reset_list = msm8996_usb3phy_reset_l,
3054 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3055 .vreg_list = qmp_phy_vreg_l,
3056 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3057 .regs = qmp_v4_usb3_uniphy_regs_layout,
3058
3059 .start_ctrl = SERDES_START | PCS_START,
3060 .pwrdn_ctrl = SW_PWRDN,
3061
3062 .has_pwrdn_delay = true,
3063 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3064 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3065};
3066
3067static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
3068 .type = PHY_TYPE_USB3,
3069 .nlanes = 1,
3070
3071 .serdes_tbl = sm8150_usb3_serdes_tbl,
3072 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3073 .tx_tbl = sm8250_usb3_tx_tbl,
3074 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
3075 .rx_tbl = sm8250_usb3_rx_tbl,
3076 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
3077 .pcs_tbl = sm8250_usb3_pcs_tbl,
3078 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
3079 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
3080 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3081 .reset_list = msm8996_usb3phy_reset_l,
3082 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3083 .vreg_list = qmp_phy_vreg_l,
3084 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3085 .regs = qmp_v4_usb3phy_regs_layout,
3086
3087 .start_ctrl = SERDES_START | PCS_START,
3088 .pwrdn_ctrl = SW_PWRDN,
3089
3090 .has_pwrdn_delay = true,
3091 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3092 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3093
3094 .has_phy_dp_com_ctrl = true,
3095 .is_dual_lane_phy = true,
3096};
3097
3098static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
3099 .type = PHY_TYPE_USB3,
3100 .nlanes = 1,
3101
3102 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3103 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3104 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
3105 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
3106 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
3107 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
3108 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3109 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3110 .clk_list = qmp_v4_phy_clk_l,
3111 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3112 .reset_list = msm8996_usb3phy_reset_l,
3113 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3114 .vreg_list = qmp_phy_vreg_l,
3115 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3116 .regs = qmp_v4_usb3_uniphy_regs_layout,
3117
3118 .start_ctrl = SERDES_START | PCS_START,
3119 .pwrdn_ctrl = SW_PWRDN,
3120
3121 .has_pwrdn_delay = true,
3122 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3123 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3124};
3125
3126static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
3127 .type = PHY_TYPE_USB3,
3128 .nlanes = 1,
3129
3130 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3131 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3132 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
3133 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
3134 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
3135 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
3136 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
3137 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3138 .clk_list = qmp_v4_sdx55_usbphy_clk_l,
3139 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
3140 .reset_list = msm8996_usb3phy_reset_l,
3141 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3142 .vreg_list = qmp_phy_vreg_l,
3143 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3144 .regs = qmp_v4_usb3_uniphy_regs_layout,
3145
3146 .start_ctrl = SERDES_START | PCS_START,
3147 .pwrdn_ctrl = SW_PWRDN,
3148
3149 .has_pwrdn_delay = true,
3150 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3151 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3152};
3153
3154static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
3155 .type = PHY_TYPE_UFS,
3156 .nlanes = 2,
3157
3158 .serdes_tbl = sm8350_ufsphy_serdes_tbl,
3159 .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
3160 .tx_tbl = sm8350_ufsphy_tx_tbl,
3161 .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
3162 .rx_tbl = sm8350_ufsphy_rx_tbl,
3163 .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
3164 .pcs_tbl = sm8350_ufsphy_pcs_tbl,
3165 .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
3166 .clk_list = sdm845_ufs_phy_clk_l,
3167 .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3168 .vreg_list = qmp_phy_vreg_l,
3169 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3170 .regs = sm8150_ufsphy_regs_layout,
3171
3172 .start_ctrl = SERDES_START,
3173 .pwrdn_ctrl = SW_PWRDN,
3174
3175 .is_dual_lane_phy = true,
3176};
3177
3178static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
3179 .type = PHY_TYPE_USB3,
3180 .nlanes = 1,
3181
3182 .serdes_tbl = sm8150_usb3_serdes_tbl,
3183 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3184 .tx_tbl = sm8350_usb3_tx_tbl,
3185 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
3186 .rx_tbl = sm8350_usb3_rx_tbl,
3187 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
3188 .pcs_tbl = sm8350_usb3_pcs_tbl,
3189 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
3190 .clk_list = qmp_v4_sm8250_usbphy_clk_l,
3191 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3192 .reset_list = msm8996_usb3phy_reset_l,
3193 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3194 .vreg_list = qmp_phy_vreg_l,
3195 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3196 .regs = qmp_v4_usb3phy_regs_layout,
3197
3198 .start_ctrl = SERDES_START | PCS_START,
3199 .pwrdn_ctrl = SW_PWRDN,
3200
3201 .has_pwrdn_delay = true,
3202 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3203 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3204
3205 .has_phy_dp_com_ctrl = true,
3206 .is_dual_lane_phy = true,
3207};
3208
3209static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
3210 .type = PHY_TYPE_USB3,
3211 .nlanes = 1,
3212
3213 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
3214 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3215 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
3216 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
3217 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
3218 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
3219 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
3220 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
3221 .clk_list = qmp_v4_phy_clk_l,
3222 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
3223 .reset_list = msm8996_usb3phy_reset_l,
3224 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3225 .vreg_list = qmp_phy_vreg_l,
3226 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3227 .regs = sm8350_usb3_uniphy_regs_layout,
3228
3229 .start_ctrl = SERDES_START | PCS_START,
3230 .pwrdn_ctrl = SW_PWRDN,
3231
3232 .has_pwrdn_delay = true,
3233 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
3234 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
3235};
3236
3237static void qcom_qmp_phy_configure_lane(void __iomem *base,
3238 const unsigned int *regs,
3239 const struct qmp_phy_init_tbl tbl[],
3240 int num,
3241 u8 lane_mask)
3242{
3243 int i;
3244 const struct qmp_phy_init_tbl *t = tbl;
3245
3246 if (!t)
3247 return;
3248
3249 for (i = 0; i < num; i++, t++) {
3250 if (!(t->lane_mask & lane_mask))
3251 continue;
3252
3253 if (t->in_layout)
3254 writel(t->val, base + regs[t->offset]);
3255 else
3256 writel(t->val, base + t->offset);
3257 }
3258}
3259
3260static void qcom_qmp_phy_configure(void __iomem *base,
3261 const unsigned int *regs,
3262 const struct qmp_phy_init_tbl tbl[],
3263 int num)
3264{
3265 qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
3266}
3267
3268static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
3269{
3270 struct qcom_qmp *qmp = qphy->qmp;
3271 const struct qmp_phy_cfg *cfg = qphy->cfg;
3272 void __iomem *serdes = qphy->serdes;
3273 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3274 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
3275 int serdes_tbl_num = cfg->serdes_tbl_num;
3276 int ret;
3277
3278 qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
3279 if (cfg->serdes_tbl_sec)
3280 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
3281 cfg->serdes_tbl_num_sec);
3282
3283 if (cfg->type == PHY_TYPE_DP) {
3284 switch (dp_opts->link_rate) {
3285 case 1620:
3286 qcom_qmp_phy_configure(serdes, cfg->regs,
3287 cfg->serdes_tbl_rbr,
3288 cfg->serdes_tbl_rbr_num);
3289 break;
3290 case 2700:
3291 qcom_qmp_phy_configure(serdes, cfg->regs,
3292 cfg->serdes_tbl_hbr,
3293 cfg->serdes_tbl_hbr_num);
3294 break;
3295 case 5400:
3296 qcom_qmp_phy_configure(serdes, cfg->regs,
3297 cfg->serdes_tbl_hbr2,
3298 cfg->serdes_tbl_hbr2_num);
3299 break;
3300 case 8100:
3301 qcom_qmp_phy_configure(serdes, cfg->regs,
3302 cfg->serdes_tbl_hbr3,
3303 cfg->serdes_tbl_hbr3_num);
3304 break;
3305 default:
3306 /* Other link rates aren't supported */
3307 return -EINVAL;
3308 }
3309 }
3310
3311
3312 if (cfg->has_phy_com_ctrl) {
3313 void __iomem *status;
3314 unsigned int mask, val;
3315
3316 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
3317 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
3318 SERDES_START | PCS_START);
3319
3320 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
3321 mask = cfg->mask_com_pcs_ready;
3322
3323 ret = readl_poll_timeout(status, val, (val & mask), 10,
3324 PHY_INIT_COMPLETE_TIMEOUT);
3325 if (ret) {
3326 dev_err(qmp->dev,
3327 "phy common block init timed-out\n");
3328 return ret;
3329 }
3330 }
3331
3332 return 0;
3333}
3334
3335static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
3336{
3337 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
3338 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
3339 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3340
3341 /* Turn on BIAS current for PHY/PLL */
3342 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
3343 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
3344 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
3345
3346 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3347
3348 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
3349 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
3350 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
3351 DP_PHY_PD_CTL_DP_CLAMP_EN,
3352 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3353
3354 writel(QSERDES_V3_COM_BIAS_EN |
3355 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
3356 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
3357 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
3358 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
3359
3360 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
3361 writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
3362 writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
3363 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
3364 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
3365 writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
3366 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
3367 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
3368 writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
3369 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
3370 qphy->dp_aux_cfg = 0;
3371
3372 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
3373 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
3374 PHY_AUX_REQ_ERR_MASK,
3375 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
3376}
3377
3378static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
3379 { 0x00, 0x0c, 0x14, 0x19 },
3380 { 0x00, 0x0b, 0x12, 0xff },
3381 { 0x00, 0x0b, 0xff, 0xff },
3382 { 0x04, 0xff, 0xff, 0xff }
3383};
3384
3385static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
3386 { 0x08, 0x0f, 0x16, 0x1f },
3387 { 0x11, 0x1e, 0x1f, 0xff },
3388 { 0x19, 0x1f, 0xff, 0xff },
3389 { 0x1f, 0xff, 0xff, 0xff }
3390};
3391
3392static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
3393{
3394 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3395 unsigned int v_level = 0, p_level = 0;
3396 u32 bias_en, drvr_en;
3397 u8 voltage_swing_cfg, pre_emphasis_cfg;
3398 int i;
3399
3400 for (i = 0; i < dp_opts->lanes; i++) {
3401 v_level = max(v_level, dp_opts->voltage[i]);
3402 p_level = max(p_level, dp_opts->pre[i]);
3403 }
3404
3405 if (dp_opts->lanes == 1) {
3406 bias_en = 0x3e;
3407 drvr_en = 0x13;
3408 } else {
3409 bias_en = 0x3f;
3410 drvr_en = 0x10;
3411 }
3412
3413 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
3414 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
3415
3416 /* TODO: Move check to config check */
3417 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
3418 return;
3419
3420 /* Enable MUX to use Cursor values from these registers */
3421 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
3422 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
3423
3424 writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL);
3425 writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
3426 writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL);
3427 writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
3428
3429 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
3430 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
3431 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
3432 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
3433}
3434
3435static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
3436{
3437 const struct phy_configure_opts_dp *dp_opts = &opts->dp;
3438 struct qmp_phy *qphy = phy_get_drvdata(phy);
3439
3440 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
3441 if (qphy->dp_opts.set_voltages) {
3442 qcom_qmp_phy_configure_dp_tx(qphy);
3443 qphy->dp_opts.set_voltages = 0;
3444 }
3445
3446 return 0;
3447}
3448
3449static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy)
3450{
3451 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
3452 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
3453 u32 val, phy_vco_div, status;
3454 unsigned long pixel_freq;
3455
3456 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
3457 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
3458
3459 /*
3460 * TODO: Assume orientation is CC1 for now and two lanes, need to
3461 * use type-c connector to understand orientation and lanes.
3462 *
3463 * Otherwise val changes to be like below if this code understood
3464 * the orientation of the type-c cable.
3465 *
3466 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
3467 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
3468 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
3469 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
3470 * if (orientation == ORIENTATION_CC2)
3471 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
3472 */
3473 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
3474 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3475
3476 writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
3477 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
3478 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
3479
3480 switch (dp_opts->link_rate) {
3481 case 1620:
3482 phy_vco_div = 0x1;
3483 pixel_freq = 1620000000UL / 2;
3484 break;
3485 case 2700:
3486 phy_vco_div = 0x1;
3487 pixel_freq = 2700000000UL / 2;
3488 break;
3489 case 5400:
3490 phy_vco_div = 0x2;
3491 pixel_freq = 5400000000UL / 4;
3492 break;
3493 case 8100:
3494 phy_vco_div = 0x0;
3495 pixel_freq = 8100000000UL / 6;
3496 break;
3497 default:
3498 /* Other link rates aren't supported */
3499 return -EINVAL;
3500 }
3501 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
3502
3503 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
3504 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
3505
3506 writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
3507 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3508 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3509 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3510 writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3511
3512 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
3513
3514 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
3515 status,
3516 ((status & BIT(0)) > 0),
3517 500,
3518 10000))
3519 return -ETIMEDOUT;
3520
3521 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3522
3523 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
3524 status,
3525 ((status & BIT(1)) > 0),
3526 500,
3527 10000))
3528 return -ETIMEDOUT;
3529
3530 writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3531 udelay(2000);
3532 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
3533
3534 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
3535 status,
3536 ((status & BIT(1)) > 0),
3537 500,
3538 10000);
3539}
3540
3541/*
3542 * We need to calibrate the aux setting here as many times
3543 * as the caller tries
3544 */
3545static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
3546{
3547 struct qmp_phy *qphy = phy_get_drvdata(phy);
3548 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
3549 u8 val;
3550
3551 qphy->dp_aux_cfg++;
3552 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
3553 val = cfg1_settings[qphy->dp_aux_cfg];
3554
3555 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
3556
3557 return 0;
3558}
3559
3560static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
3561{
3562 struct qcom_qmp *qmp = qphy->qmp;
3563 const struct qmp_phy_cfg *cfg = qphy->cfg;
3564 void __iomem *serdes = qphy->serdes;
3565 void __iomem *pcs = qphy->pcs;
3566 void __iomem *dp_com = qmp->dp_com;
3567 int ret, i;
3568
3569 mutex_lock(&qmp->phy_mutex);
3570 if (qmp->init_count++) {
3571 mutex_unlock(&qmp->phy_mutex);
3572 return 0;
3573 }
3574
3575 /* turn on regulator supplies */
3576 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
3577 if (ret) {
3578 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
3579 goto err_reg_enable;
3580 }
3581
3582 for (i = 0; i < cfg->num_resets; i++) {
3583 ret = reset_control_assert(qmp->resets[i]);
3584 if (ret) {
3585 dev_err(qmp->dev, "%s reset assert failed\n",
3586 cfg->reset_list[i]);
3587 goto err_rst_assert;
3588 }
3589 }
3590
3591 for (i = cfg->num_resets - 1; i >= 0; i--) {
3592 ret = reset_control_deassert(qmp->resets[i]);
3593 if (ret) {
3594 dev_err(qmp->dev, "%s reset deassert failed\n",
3595 qphy->cfg->reset_list[i]);
3596 goto err_rst;
3597 }
3598 }
3599
3600 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
3601 if (ret) {
3602 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
3603 goto err_rst;
3604 }
3605
3606 if (cfg->has_phy_dp_com_ctrl) {
3607 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
3608 SW_PWRDN);
3609 /* override hardware control for reset of qmp phy */
3610 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3611 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
3612 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
3613
3614 /* Default type-c orientation, i.e CC1 */
3615 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
3616
3617 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
3618 USB3_MODE | DP_MODE);
3619
3620 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
3621 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3622 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
3623 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
3624
3625 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
3626 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
3627 }
3628
3629 if (cfg->has_phy_com_ctrl) {
3630 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
3631 SW_PWRDN);
3632 } else {
3633 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
3634 qphy_setbits(pcs,
3635 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3636 cfg->pwrdn_ctrl);
3637 else
3638 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
3639 cfg->pwrdn_ctrl);
3640 }
3641
3642 mutex_unlock(&qmp->phy_mutex);
3643
3644 return 0;
3645
3646err_rst:
3647 while (++i < cfg->num_resets)
3648 reset_control_assert(qmp->resets[i]);
3649err_rst_assert:
3650 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3651err_reg_enable:
3652 mutex_unlock(&qmp->phy_mutex);
3653
3654 return ret;
3655}
3656
3657static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
3658{
3659 struct qcom_qmp *qmp = qphy->qmp;
3660 const struct qmp_phy_cfg *cfg = qphy->cfg;
3661 void __iomem *serdes = qphy->serdes;
3662 int i = cfg->num_resets;
3663
3664 mutex_lock(&qmp->phy_mutex);
3665 if (--qmp->init_count) {
3666 mutex_unlock(&qmp->phy_mutex);
3667 return 0;
3668 }
3669
3670 reset_control_assert(qmp->ufs_reset);
3671 if (cfg->has_phy_com_ctrl) {
3672 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
3673 SERDES_START | PCS_START);
3674 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
3675 SW_RESET);
3676 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
3677 SW_PWRDN);
3678 }
3679
3680 while (--i >= 0)
3681 reset_control_assert(qmp->resets[i]);
3682
3683 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
3684
3685 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3686
3687 mutex_unlock(&qmp->phy_mutex);
3688
3689 return 0;
3690}
3691
3692static int qcom_qmp_phy_init(struct phy *phy)
3693{
3694 struct qmp_phy *qphy = phy_get_drvdata(phy);
3695 struct qcom_qmp *qmp = qphy->qmp;
3696 const struct qmp_phy_cfg *cfg = qphy->cfg;
3697 int ret;
3698 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
3699
3700 if (cfg->no_pcs_sw_reset) {
3701 /*
3702 * Get UFS reset, which is delayed until now to avoid a
3703 * circular dependency where UFS needs its PHY, but the PHY
3704 * needs this UFS reset.
3705 */
3706 if (!qmp->ufs_reset) {
3707 qmp->ufs_reset =
3708 devm_reset_control_get_exclusive(qmp->dev,
3709 "ufsphy");
3710
3711 if (IS_ERR(qmp->ufs_reset)) {
3712 ret = PTR_ERR(qmp->ufs_reset);
3713 dev_err(qmp->dev,
3714 "failed to get UFS reset: %d\n",
3715 ret);
3716
3717 qmp->ufs_reset = NULL;
3718 return ret;
3719 }
3720 }
3721
3722 ret = reset_control_assert(qmp->ufs_reset);
3723 if (ret)
3724 return ret;
3725 }
3726
3727 ret = qcom_qmp_phy_com_init(qphy);
3728 if (ret)
3729 return ret;
3730
3731 if (cfg->type == PHY_TYPE_DP)
3732 qcom_qmp_phy_dp_aux_init(qphy);
3733
3734 return 0;
3735}
3736
3737static int qcom_qmp_phy_power_on(struct phy *phy)
3738{
3739 struct qmp_phy *qphy = phy_get_drvdata(phy);
3740 struct qcom_qmp *qmp = qphy->qmp;
3741 const struct qmp_phy_cfg *cfg = qphy->cfg;
3742 void __iomem *tx = qphy->tx;
3743 void __iomem *rx = qphy->rx;
3744 void __iomem *pcs = qphy->pcs;
3745 void __iomem *pcs_misc = qphy->pcs_misc;
3746 void __iomem *status;
3747 unsigned int mask, val, ready;
3748 int ret;
3749
3750 qcom_qmp_phy_serdes_init(qphy);
3751
3752 if (cfg->has_lane_rst) {
3753 ret = reset_control_deassert(qphy->lane_rst);
3754 if (ret) {
3755 dev_err(qmp->dev, "lane%d reset deassert failed\n",
3756 qphy->index);
3757 goto err_lane_rst;
3758 }
3759 }
3760
3761 ret = clk_prepare_enable(qphy->pipe_clk);
3762 if (ret) {
3763 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
3764 goto err_clk_enable;
3765 }
3766
3767 /* Tx, Rx, and PCS configurations */
3768 qcom_qmp_phy_configure_lane(tx, cfg->regs,
3769 cfg->tx_tbl, cfg->tx_tbl_num, 1);
3770 if (cfg->tx_tbl_sec)
3771 qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
3772 cfg->tx_tbl_num_sec, 1);
3773
3774 /* Configuration for other LANE for USB-DP combo PHY */
3775 if (cfg->is_dual_lane_phy) {
3776 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
3777 cfg->tx_tbl, cfg->tx_tbl_num, 2);
3778 if (cfg->tx_tbl_sec)
3779 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
3780 cfg->tx_tbl_sec,
3781 cfg->tx_tbl_num_sec, 2);
3782 }
3783
3784 /* Configure special DP tx tunings */
3785 if (cfg->type == PHY_TYPE_DP)
3786 qcom_qmp_phy_configure_dp_tx(qphy);
3787
3788 qcom_qmp_phy_configure_lane(rx, cfg->regs,
3789 cfg->rx_tbl, cfg->rx_tbl_num, 1);
3790 if (cfg->rx_tbl_sec)
3791 qcom_qmp_phy_configure_lane(rx, cfg->regs,
3792 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
3793
3794 if (cfg->is_dual_lane_phy) {
3795 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
3796 cfg->rx_tbl, cfg->rx_tbl_num, 2);
3797 if (cfg->rx_tbl_sec)
3798 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
3799 cfg->rx_tbl_sec,
3800 cfg->rx_tbl_num_sec, 2);
3801 }
3802
3803 /* Configure link rate, swing, etc. */
3804 if (cfg->type == PHY_TYPE_DP) {
3805 qcom_qmp_phy_configure_dp_phy(qphy);
3806 } else {
3807 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
3808 if (cfg->pcs_tbl_sec)
3809 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
3810 cfg->pcs_tbl_num_sec);
3811 }
3812
3813 ret = reset_control_deassert(qmp->ufs_reset);
3814 if (ret)
3815 goto err_lane_rst;
3816
3817 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
3818 cfg->pcs_misc_tbl_num);
3819 if (cfg->pcs_misc_tbl_sec)
3820 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
3821 cfg->pcs_misc_tbl_num_sec);
3822
3823 /*
3824 * Pull out PHY from POWER DOWN state.
3825 * This is active low enable signal to power-down PHY.
3826 */
3827 if(cfg->type == PHY_TYPE_PCIE)
3828 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
3829
3830 if (cfg->has_pwrdn_delay)
3831 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
3832
3833 if (cfg->type != PHY_TYPE_DP) {
3834 /* Pull PHY out of reset state */
3835 if (!cfg->no_pcs_sw_reset)
3836 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3837 /* start SerDes and Phy-Coding-Sublayer */
3838 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3839
3840 if (cfg->type == PHY_TYPE_UFS) {
3841 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
3842 mask = PCS_READY;
3843 ready = PCS_READY;
3844 } else {
3845 status = pcs + cfg->regs[QPHY_PCS_STATUS];
3846 mask = PHYSTATUS;
3847 ready = 0;
3848 }
3849
3850 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
3851 PHY_INIT_COMPLETE_TIMEOUT);
3852 if (ret) {
3853 dev_err(qmp->dev, "phy initialization timed-out\n");
3854 goto err_pcs_ready;
3855 }
3856 }
3857 return 0;
3858
3859err_pcs_ready:
3860 clk_disable_unprepare(qphy->pipe_clk);
3861err_clk_enable:
3862 if (cfg->has_lane_rst)
3863 reset_control_assert(qphy->lane_rst);
3864err_lane_rst:
3865 return ret;
3866}
3867
3868static int qcom_qmp_phy_power_off(struct phy *phy)
3869{
3870 struct qmp_phy *qphy = phy_get_drvdata(phy);
3871 const struct qmp_phy_cfg *cfg = qphy->cfg;
3872
3873 clk_disable_unprepare(qphy->pipe_clk);
3874
3875 if (cfg->type == PHY_TYPE_DP) {
3876 /* Assert DP PHY power down */
3877 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3878 } else {
3879 /* PHY reset */
3880 if (!cfg->no_pcs_sw_reset)
3881 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3882
3883 /* stop SerDes and Phy-Coding-Sublayer */
3884 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3885
3886 /* Put PHY into POWER DOWN state: active low */
3887 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
3888 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3889 cfg->pwrdn_ctrl);
3890 } else {
3891 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
3892 cfg->pwrdn_ctrl);
3893 }
3894 }
3895
3896 return 0;
3897}
3898
3899static int qcom_qmp_phy_exit(struct phy *phy)
3900{
3901 struct qmp_phy *qphy = phy_get_drvdata(phy);
3902 const struct qmp_phy_cfg *cfg = qphy->cfg;
3903
3904 if (cfg->has_lane_rst)
3905 reset_control_assert(qphy->lane_rst);
3906
3907 qcom_qmp_phy_com_exit(qphy);
3908
3909 return 0;
3910}
3911
3912static int qcom_qmp_phy_enable(struct phy *phy)
3913{
3914 int ret;
3915
3916 ret = qcom_qmp_phy_init(phy);
3917 if (ret)
3918 return ret;
3919
3920 ret = qcom_qmp_phy_power_on(phy);
3921 if (ret)
3922 qcom_qmp_phy_exit(phy);
3923
3924 return ret;
3925}
3926
3927static int qcom_qmp_phy_disable(struct phy *phy)
3928{
3929 int ret;
3930
3931 ret = qcom_qmp_phy_power_off(phy);
3932 if (ret)
3933 return ret;
3934 return qcom_qmp_phy_exit(phy);
3935}
3936
3937static int qcom_qmp_phy_set_mode(struct phy *phy,
3938 enum phy_mode mode, int submode)
3939{
3940 struct qmp_phy *qphy = phy_get_drvdata(phy);
3941
3942 qphy->mode = mode;
3943
3944 return 0;
3945}
3946
3947static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
3948{
3949 const struct qmp_phy_cfg *cfg = qphy->cfg;
3950 void __iomem *pcs = qphy->pcs;
3951 void __iomem *pcs_misc = qphy->pcs_misc;
3952 u32 intr_mask;
3953
3954 if (qphy->mode == PHY_MODE_USB_HOST_SS ||
3955 qphy->mode == PHY_MODE_USB_DEVICE_SS)
3956 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
3957 else
3958 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
3959
3960 /* Clear any pending interrupts status */
3961 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3962 /* Writing 1 followed by 0 clears the interrupt */
3963 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3964
3965 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3966 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
3967
3968 /* Enable required PHY autonomous mode interrupts */
3969 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
3970
3971 /* Enable i/o clamp_n for autonomous mode */
3972 if (pcs_misc)
3973 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3974}
3975
3976static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
3977{
3978 const struct qmp_phy_cfg *cfg = qphy->cfg;
3979 void __iomem *pcs = qphy->pcs;
3980 void __iomem *pcs_misc = qphy->pcs_misc;
3981
3982 /* Disable i/o clamp_n on resume for normal mode */
3983 if (pcs_misc)
3984 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3985
3986 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3987 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
3988
3989 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3990 /* Writing 1 followed by 0 clears the interrupt */
3991 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3992}
3993
3994static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
3995{
3996 struct qcom_qmp *qmp = dev_get_drvdata(dev);
3997 struct qmp_phy *qphy = qmp->phys[0];
3998 const struct qmp_phy_cfg *cfg = qphy->cfg;
3999
4000 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
4001
4002 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
4003 if (cfg->type != PHY_TYPE_USB3)
4004 return 0;
4005
4006 if (!qmp->init_count) {
4007 dev_vdbg(dev, "PHY not initialized, bailing out\n");
4008 return 0;
4009 }
4010
4011 qcom_qmp_phy_enable_autonomous_mode(qphy);
4012
4013 clk_disable_unprepare(qphy->pipe_clk);
4014 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4015
4016 return 0;
4017}
4018
4019static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
4020{
4021 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4022 struct qmp_phy *qphy = qmp->phys[0];
4023 const struct qmp_phy_cfg *cfg = qphy->cfg;
4024 int ret = 0;
4025
4026 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
4027
4028 /* Supported only for USB3 PHY and luckily USB3 is the first phy */
4029 if (cfg->type != PHY_TYPE_USB3)
4030 return 0;
4031
4032 if (!qmp->init_count) {
4033 dev_vdbg(dev, "PHY not initialized, bailing out\n");
4034 return 0;
4035 }
4036
4037 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
4038 if (ret) {
4039 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
4040 return ret;
4041 }
4042
4043 ret = clk_prepare_enable(qphy->pipe_clk);
4044 if (ret) {
4045 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
4046 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4047 return ret;
4048 }
4049
4050 qcom_qmp_phy_disable_autonomous_mode(qphy);
4051
4052 return 0;
4053}
4054
4055static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
4056{
4057 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4058 int num = cfg->num_vregs;
4059 int i;
4060
4061 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
4062 if (!qmp->vregs)
4063 return -ENOMEM;
4064
4065 for (i = 0; i < num; i++)
4066 qmp->vregs[i].supply = cfg->vreg_list[i];
4067
4068 return devm_regulator_bulk_get(dev, num, qmp->vregs);
4069}
4070
4071static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
4072{
4073 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4074 int i;
4075
4076 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
4077 sizeof(*qmp->resets), GFP_KERNEL);
4078 if (!qmp->resets)
4079 return -ENOMEM;
4080
4081 for (i = 0; i < cfg->num_resets; i++) {
4082 struct reset_control *rst;
4083 const char *name = cfg->reset_list[i];
4084
4085 rst = devm_reset_control_get(dev, name);
4086 if (IS_ERR(rst)) {
4087 dev_err(dev, "failed to get %s reset\n", name);
4088 return PTR_ERR(rst);
4089 }
4090 qmp->resets[i] = rst;
4091 }
4092
4093 return 0;
4094}
4095
4096static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
4097{
4098 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4099 int num = cfg->num_clks;
4100 int i;
4101
4102 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
4103 if (!qmp->clks)
4104 return -ENOMEM;
4105
4106 for (i = 0; i < num; i++)
4107 qmp->clks[i].id = cfg->clk_list[i];
4108
4109 return devm_clk_bulk_get(dev, num, qmp->clks);
4110}
4111
4112static void phy_clk_release_provider(void *res)
4113{
4114 of_clk_del_provider(res);
4115}
4116
4117/*
4118 * Register a fixed rate pipe clock.
4119 *
4120 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
4121 * controls it. The <s>_pipe_clk coming out of the GCC is requested
4122 * by the PHY driver for its operations.
4123 * We register the <s>_pipe_clksrc here. The gcc driver takes care
4124 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
4125 * Below picture shows this relationship.
4126 *
4127 * +---------------+
4128 * | PHY block |<<---------------------------------------+
4129 * | | |
4130 * | +-------+ | +-----+ |
4131 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4132 * clk | +-------+ | +-----+
4133 * +---------------+
4134 */
4135static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
4136{
4137 struct clk_fixed_rate *fixed;
4138 struct clk_init_data init = { };
4139 int ret;
4140
4141 ret = of_property_read_string(np, "clock-output-names", &init.name);
4142 if (ret) {
4143 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
4144 return ret;
4145 }
4146
4147 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
4148 if (!fixed)
4149 return -ENOMEM;
4150
4151 init.ops = &clk_fixed_rate_ops;
4152
4153 /* controllers using QMP phys use 125MHz pipe clock interface */
4154 fixed->fixed_rate = 125000000;
4155 fixed->hw.init = &init;
4156
4157 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
4158 if (ret)
4159 return ret;
4160
4161 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
4162 if (ret)
4163 return ret;
4164
4165 /*
4166 * Roll a devm action because the clock provider is the child node, but
4167 * the child node is not actually a device.
4168 */
4169 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
4170 if (ret)
4171 phy_clk_release_provider(np);
4172
4173 return ret;
4174}
4175
4176/*
4177 * Display Port PLL driver block diagram for branch clocks
4178 *
4179 * +------------------------------+
4180 * | DP_VCO_CLK |
4181 * | |
4182 * | +-------------------+ |
4183 * | | (DP PLL/VCO) | |
4184 * | +---------+---------+ |
4185 * | v |
4186 * | +----------+-----------+ |
4187 * | | hsclk_divsel_clk_src | |
4188 * | +----------+-----------+ |
4189 * +------------------------------+
4190 * |
4191 * +---------<---------v------------>----------+
4192 * | |
4193 * +--------v----------------+ |
4194 * | dp_phy_pll_link_clk | |
4195 * | link_clk | |
4196 * +--------+----------------+ |
4197 * | |
4198 * | |
4199 * v v
4200 * Input to DISPCC block |
4201 * for link clk, crypto clk |
4202 * and interface clock |
4203 * |
4204 * |
4205 * +--------<------------+-----------------+---<---+
4206 * | | |
4207 * +----v---------+ +--------v-----+ +--------v------+
4208 * | vco_divided | | vco_divided | | vco_divided |
4209 * | _clk_src | | _clk_src | | _clk_src |
4210 * | | | | | |
4211 * |divsel_six | | divsel_two | | divsel_four |
4212 * +-------+------+ +-----+--------+ +--------+------+
4213 * | | |
4214 * v---->----------v-------------<------v
4215 * |
4216 * +----------+-----------------+
4217 * | dp_phy_pll_vco_div_clk |
4218 * +---------+------------------+
4219 * |
4220 * v
4221 * Input to DISPCC block
4222 * for DP pixel clock
4223 *
4224 */
4225static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
4226 struct clk_rate_request *req)
4227{
4228 switch (req->rate) {
4229 case 1620000000UL / 2:
4230 case 2700000000UL / 2:
4231 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
4232 return 0;
4233 default:
4234 return -EINVAL;
4235 }
4236}
4237
4238static unsigned long
4239qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
4240{
4241 const struct qmp_phy_dp_clks *dp_clks;
4242 const struct qmp_phy *qphy;
4243 const struct phy_configure_opts_dp *dp_opts;
4244
4245 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
4246 qphy = dp_clks->qphy;
4247 dp_opts = &qphy->dp_opts;
4248
4249 switch (dp_opts->link_rate) {
4250 case 1620:
4251 return 1620000000UL / 2;
4252 case 2700:
4253 return 2700000000UL / 2;
4254 case 5400:
4255 return 5400000000UL / 4;
4256 case 8100:
4257 return 8100000000UL / 6;
4258 default:
4259 return 0;
4260 }
4261}
4262
4263static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
4264 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
4265 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
4266};
4267
4268static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
4269 struct clk_rate_request *req)
4270{
4271 switch (req->rate) {
4272 case 162000000:
4273 case 270000000:
4274 case 540000000:
4275 case 810000000:
4276 return 0;
4277 default:
4278 return -EINVAL;
4279 }
4280}
4281
4282static unsigned long
4283qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
4284{
4285 const struct qmp_phy_dp_clks *dp_clks;
4286 const struct qmp_phy *qphy;
4287 const struct phy_configure_opts_dp *dp_opts;
4288
4289 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
4290 qphy = dp_clks->qphy;
4291 dp_opts = &qphy->dp_opts;
4292
4293 switch (dp_opts->link_rate) {
4294 case 1620:
4295 case 2700:
4296 case 5400:
4297 case 8100:
4298 return dp_opts->link_rate * 100000;
4299 default:
4300 return 0;
4301 }
4302}
4303
4304static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
4305 .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
4306 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
4307};
4308
4309static struct clk_hw *
4310qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
4311{
4312 struct qmp_phy_dp_clks *dp_clks = data;
4313 unsigned int idx = clkspec->args[0];
4314
4315 if (idx >= 2) {
4316 pr_err("%s: invalid index %u\n", __func__, idx);
4317 return ERR_PTR(-EINVAL);
4318 }
4319
4320 if (idx == 0)
4321 return &dp_clks->dp_link_hw;
4322
4323 return &dp_clks->dp_pixel_hw;
4324}
4325
4326static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
4327 struct device_node *np)
4328{
4329 struct clk_init_data init = { };
4330 struct qmp_phy_dp_clks *dp_clks;
4331 int ret;
4332
4333 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
4334 if (!dp_clks)
4335 return -ENOMEM;
4336
4337 dp_clks->qphy = qphy;
4338 qphy->dp_clks = dp_clks;
4339
4340 init.ops = &qcom_qmp_dp_link_clk_ops;
4341 init.name = "qmp_dp_phy_pll_link_clk";
4342 dp_clks->dp_link_hw.init = &init;
4343 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
4344 if (ret)
4345 return ret;
4346
4347 init.ops = &qcom_qmp_dp_pixel_clk_ops;
4348 init.name = "qmp_dp_phy_pll_vco_div_clk";
4349 dp_clks->dp_pixel_hw.init = &init;
4350 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
4351 if (ret)
4352 return ret;
4353
4354 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
4355 if (ret)
4356 return ret;
4357
4358 /*
4359 * Roll a devm action because the clock provider is the child node, but
4360 * the child node is not actually a device.
4361 */
4362 ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
4363 if (ret)
4364 phy_clk_release_provider(np);
4365
4366 return ret;
4367}
4368
4369static const struct phy_ops qcom_qmp_phy_gen_ops = {
4370 .init = qcom_qmp_phy_enable,
4371 .exit = qcom_qmp_phy_disable,
4372 .set_mode = qcom_qmp_phy_set_mode,
4373 .owner = THIS_MODULE,
4374};
4375
4376static const struct phy_ops qcom_qmp_phy_dp_ops = {
4377 .init = qcom_qmp_phy_init,
4378 .configure = qcom_qmp_dp_phy_configure,
4379 .power_on = qcom_qmp_phy_power_on,
4380 .calibrate = qcom_qmp_dp_phy_calibrate,
4381 .power_off = qcom_qmp_phy_power_off,
4382 .exit = qcom_qmp_phy_exit,
4383 .set_mode = qcom_qmp_phy_set_mode,
4384 .owner = THIS_MODULE,
4385};
4386
4387static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
4388 .power_on = qcom_qmp_phy_enable,
4389 .power_off = qcom_qmp_phy_disable,
4390 .set_mode = qcom_qmp_phy_set_mode,
4391 .owner = THIS_MODULE,
4392};
4393
4394static
4395int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
4396 void __iomem *serdes, const struct qmp_phy_cfg *cfg)
4397{
4398 struct qcom_qmp *qmp = dev_get_drvdata(dev);
4399 struct phy *generic_phy;
4400 struct qmp_phy *qphy;
4401 const struct phy_ops *ops;
4402 char prop_name[MAX_PROP_NAME];
4403 int ret;
4404
4405 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
4406 if (!qphy)
4407 return -ENOMEM;
4408
4409 qphy->cfg = cfg;
4410 qphy->serdes = serdes;
4411 /*
4412 * Get memory resources for each phy lane:
4413 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
4414 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
4415 * For single lane PHYs: pcs_misc (optional) -> 3.
4416 */
4417 qphy->tx = of_iomap(np, 0);
4418 if (!qphy->tx)
4419 return -ENOMEM;
4420
4421 qphy->rx = of_iomap(np, 1);
4422 if (!qphy->rx)
4423 return -ENOMEM;
4424
4425 qphy->pcs = of_iomap(np, 2);
4426 if (!qphy->pcs)
4427 return -ENOMEM;
4428
4429 /*
4430 * If this is a dual-lane PHY, then there should be registers for the
4431 * second lane. Some old device trees did not specify this, so fall
4432 * back to old legacy behavior of assuming they can be reached at an
4433 * offset from the first lane.
4434 */
4435 if (cfg->is_dual_lane_phy) {
4436 qphy->tx2 = of_iomap(np, 3);
4437 qphy->rx2 = of_iomap(np, 4);
4438 if (!qphy->tx2 || !qphy->rx2) {
4439 dev_warn(dev,
4440 "Underspecified device tree, falling back to legacy register regions\n");
4441
4442 /* In the old version, pcs_misc is at index 3. */
4443 qphy->pcs_misc = qphy->tx2;
4444 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
4445 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
4446
4447 } else {
4448 qphy->pcs_misc = of_iomap(np, 5);
4449 }
4450
4451 } else {
4452 qphy->pcs_misc = of_iomap(np, 3);
4453 }
4454
4455 if (!qphy->pcs_misc)
4456 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
4457
4458 /*
4459 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
4460 * based phys, so they essentially have pipe clock. So,
4461 * we return error in case phy is USB3 or PIPE type.
4462 * Otherwise, we initialize pipe clock to NULL for
4463 * all phys that don't need this.
4464 */
4465 snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
4466 qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
4467 if (IS_ERR(qphy->pipe_clk)) {
4468 if (cfg->type == PHY_TYPE_PCIE ||
4469 cfg->type == PHY_TYPE_USB3) {
4470 ret = PTR_ERR(qphy->pipe_clk);
4471 if (ret != -EPROBE_DEFER)
4472 dev_err(dev,
4473 "failed to get lane%d pipe_clk, %d\n",
4474 id, ret);
4475 return ret;
4476 }
4477 qphy->pipe_clk = NULL;
4478 }
4479
4480 /* Get lane reset, if any */
4481 if (cfg->has_lane_rst) {
4482 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
4483 qphy->lane_rst = of_reset_control_get(np, prop_name);
4484 if (IS_ERR(qphy->lane_rst)) {
4485 dev_err(dev, "failed to get lane%d reset\n", id);
4486 return PTR_ERR(qphy->lane_rst);
4487 }
4488 }
4489
4490 if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
4491 ops = &qcom_qmp_pcie_ufs_ops;
4492 else if (cfg->type == PHY_TYPE_DP)
4493 ops = &qcom_qmp_phy_dp_ops;
4494 else
4495 ops = &qcom_qmp_phy_gen_ops;
4496
4497 generic_phy = devm_phy_create(dev, np, ops);
4498 if (IS_ERR(generic_phy)) {
4499 ret = PTR_ERR(generic_phy);
4500 dev_err(dev, "failed to create qphy %d\n", ret);
4501 return ret;
4502 }
4503
4504 qphy->phy = generic_phy;
4505 qphy->index = id;
4506 qphy->qmp = qmp;
4507 qmp->phys[id] = qphy;
4508 phy_set_drvdata(generic_phy, qphy);
4509
4510 return 0;
4511}
4512
4513static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
4514 {
4515 .compatible = "qcom,ipq8074-qmp-usb3-phy",
4516 .data = &ipq8074_usb3phy_cfg,
4517 }, {
4518 .compatible = "qcom,msm8996-qmp-pcie-phy",
4519 .data = &msm8996_pciephy_cfg,
4520 }, {
4521 .compatible = "qcom,msm8996-qmp-ufs-phy",
4522 .data = &msm8996_ufs_cfg,
4523 }, {
4524 .compatible = "qcom,msm8996-qmp-usb3-phy",
4525 .data = &msm8996_usb3phy_cfg,
4526 }, {
4527 .compatible = "qcom,msm8998-qmp-pcie-phy",
4528 .data = &msm8998_pciephy_cfg,
4529 }, {
4530 .compatible = "qcom,msm8998-qmp-ufs-phy",
4531 .data = &sdm845_ufsphy_cfg,
4532 }, {
4533 .compatible = "qcom,ipq8074-qmp-pcie-phy",
4534 .data = &ipq8074_pciephy_cfg,
4535 }, {
4536 .compatible = "qcom,sc7180-qmp-usb3-phy",
4537 .data = &sc7180_usb3phy_cfg,
4538 }, {
4539 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
4540 /* It's a combo phy */
4541 }, {
4542 .compatible = "qcom,sc8180x-qmp-ufs-phy",
4543 .data = &sm8150_ufsphy_cfg,
4544 }, {
4545 .compatible = "qcom,sc8180x-qmp-usb3-phy",
4546 .data = &sm8150_usb3phy_cfg,
4547 }, {
4548 .compatible = "qcom,sdm845-qhp-pcie-phy",
4549 .data = &sdm845_qhp_pciephy_cfg,
4550 }, {
4551 .compatible = "qcom,sdm845-qmp-pcie-phy",
4552 .data = &sdm845_qmp_pciephy_cfg,
4553 }, {
4554 .compatible = "qcom,sdm845-qmp-usb3-phy",
4555 .data = &qmp_v3_usb3phy_cfg,
4556 }, {
4557 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
4558 .data = &qmp_v3_usb3_uniphy_cfg,
4559 }, {
4560 .compatible = "qcom,sdm845-qmp-ufs-phy",
4561 .data = &sdm845_ufsphy_cfg,
4562 }, {
4563 .compatible = "qcom,msm8998-qmp-usb3-phy",
4564 .data = &msm8998_usb3phy_cfg,
4565 }, {
4566 .compatible = "qcom,sm8150-qmp-ufs-phy",
4567 .data = &sm8150_ufsphy_cfg,
4568 }, {
4569 .compatible = "qcom,sm8250-qmp-ufs-phy",
4570 .data = &sm8150_ufsphy_cfg,
4571 }, {
4572 .compatible = "qcom,sm8150-qmp-usb3-phy",
4573 .data = &sm8150_usb3phy_cfg,
4574 }, {
4575 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
4576 .data = &sm8150_usb3_uniphy_cfg,
4577 }, {
4578 .compatible = "qcom,sm8250-qmp-usb3-phy",
4579 .data = &sm8250_usb3phy_cfg,
4580 }, {
4581 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
4582 .data = &sm8250_usb3_uniphy_cfg,
4583 }, {
4584 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
4585 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
4586 }, {
4587 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
4588 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
4589 }, {
4590 .compatible = "qcom,sm8350-qmp-ufs-phy",
4591 .data = &sm8350_ufsphy_cfg,
4592 }, {
4593 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
4594 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
4595 }, {
4596 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
4597 .data = &sdx55_usb3_uniphy_cfg,
4598 }, {
4599 .compatible = "qcom,sm8350-qmp-usb3-phy",
4600 .data = &sm8350_usb3phy_cfg,
4601 }, {
4602 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
4603 .data = &sm8350_usb3_uniphy_cfg,
4604 },
4605 { },
4606};
4607MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
4608
4609static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
4610 {
4611 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
4612 .data = &sc7180_usb3dpphy_cfg,
4613 },
4614 { }
4615};
4616
4617static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
4618 SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
4619 qcom_qmp_phy_runtime_resume, NULL)
4620};
4621
4622static int qcom_qmp_phy_probe(struct platform_device *pdev)
4623{
4624 struct qcom_qmp *qmp;
4625 struct device *dev = &pdev->dev;
4626 struct device_node *child;
4627 struct phy_provider *phy_provider;
4628 void __iomem *serdes;
4629 void __iomem *usb_serdes;
4630 void __iomem *dp_serdes = NULL;
4631 const struct qmp_phy_combo_cfg *combo_cfg = NULL;
4632 const struct qmp_phy_cfg *cfg = NULL;
4633 const struct qmp_phy_cfg *usb_cfg = NULL;
4634 const struct qmp_phy_cfg *dp_cfg = NULL;
4635 int num, id, expected_phys;
4636 int ret;
4637
4638 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
4639 if (!qmp)
4640 return -ENOMEM;
4641
4642 qmp->dev = dev;
4643 dev_set_drvdata(dev, qmp);
4644
4645 /* Get the specific init parameters of QMP phy */
4646 cfg = of_device_get_match_data(dev);
4647 if (!cfg) {
4648 const struct of_device_id *match;
4649
4650 match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
4651 if (!match)
4652 return -EINVAL;
4653
4654 combo_cfg = match->data;
4655 if (!combo_cfg)
4656 return -EINVAL;
4657
4658 usb_cfg = combo_cfg->usb_cfg;
4659 cfg = usb_cfg; /* Setup clks and regulators */
4660 }
4661
4662 /* per PHY serdes; usually located at base address */
4663 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
4664 if (IS_ERR(serdes))
4665 return PTR_ERR(serdes);
4666
4667 /* per PHY dp_com; if PHY has dp_com control block */
4668 if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
4669 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
4670 if (IS_ERR(qmp->dp_com))
4671 return PTR_ERR(qmp->dp_com);
4672 }
4673
4674 if (combo_cfg) {
4675 /* Only two serdes for combo PHY */
4676 dp_serdes = devm_platform_ioremap_resource(pdev, 2);
4677 if (IS_ERR(dp_serdes))
4678 return PTR_ERR(dp_serdes);
4679
4680 dp_cfg = combo_cfg->dp_cfg;
4681 expected_phys = 2;
4682 } else {
4683 expected_phys = cfg->nlanes;
4684 }
4685
4686 mutex_init(&qmp->phy_mutex);
4687
4688 ret = qcom_qmp_phy_clk_init(dev, cfg);
4689 if (ret)
4690 return ret;
4691
4692 ret = qcom_qmp_phy_reset_init(dev, cfg);
4693 if (ret)
4694 return ret;
4695
4696 ret = qcom_qmp_phy_vreg_init(dev, cfg);
4697 if (ret) {
4698 if (ret != -EPROBE_DEFER)
4699 dev_err(dev, "failed to get regulator supplies: %d\n",
4700 ret);
4701 return ret;
4702 }
4703
4704 num = of_get_available_child_count(dev->of_node);
4705 /* do we have a rogue child node ? */
4706 if (num > expected_phys)
4707 return -EINVAL;
4708
4709 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
4710 if (!qmp->phys)
4711 return -ENOMEM;
4712
4713 pm_runtime_set_active(dev);
4714 pm_runtime_enable(dev);
4715 /*
4716 * Prevent runtime pm from being ON by default. Users can enable
4717 * it using power/control in sysfs.
4718 */
4719 pm_runtime_forbid(dev);
4720
4721 id = 0;
4722 for_each_available_child_of_node(dev->of_node, child) {
4723 if (of_node_name_eq(child, "dp-phy")) {
4724 cfg = dp_cfg;
4725 serdes = dp_serdes;
4726 } else if (of_node_name_eq(child, "usb3-phy")) {
4727 cfg = usb_cfg;
4728 serdes = usb_serdes;
4729 }
4730
4731 /* Create per-lane phy */
4732 ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
4733 if (ret) {
4734 dev_err(dev, "failed to create lane%d phy, %d\n",
4735 id, ret);
4736 goto err_node_put;
4737 }
4738
4739 /*
4740 * Register the pipe clock provided by phy.
4741 * See function description to see details of this pipe clock.
4742 */
4743 if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
4744 ret = phy_pipe_clk_register(qmp, child);
4745 if (ret) {
4746 dev_err(qmp->dev,
4747 "failed to register pipe clock source\n");
4748 goto err_node_put;
4749 }
4750 } else if (cfg->type == PHY_TYPE_DP) {
4751 ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
4752 if (ret) {
4753 dev_err(qmp->dev,
4754 "failed to register DP clock source\n");
4755 goto err_node_put;
4756 }
4757 }
4758 id++;
4759 }
4760
4761 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
4762 if (!IS_ERR(phy_provider))
4763 dev_info(dev, "Registered Qcom-QMP phy\n");
4764 else
4765 pm_runtime_disable(dev);
4766
4767 return PTR_ERR_OR_ZERO(phy_provider);
4768
4769err_node_put:
4770 pm_runtime_disable(dev);
4771 of_node_put(child);
4772 return ret;
4773}
4774
4775static struct platform_driver qcom_qmp_phy_driver = {
4776 .probe = qcom_qmp_phy_probe,
4777 .driver = {
4778 .name = "qcom-qmp-phy",
4779 .pm = &qcom_qmp_phy_pm_ops,
4780 .of_match_table = qcom_qmp_phy_of_match_table,
4781 },
4782};
4783
4784module_platform_driver(qcom_qmp_phy_driver);
4785
4786MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
4787MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
4788MODULE_LICENSE("GPL v2");