Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_OBJECT_H__
29#define __AMDGPU_OBJECT_H__
30
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33#ifdef CONFIG_MMU_NOTIFIER
34#include <linux/mmu_notifier.h>
35#endif
36
37#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
38#define AMDGPU_BO_MAX_PLACEMENTS 3
39
40struct amdgpu_bo_param {
41 unsigned long size;
42 int byte_align;
43 u32 domain;
44 u32 preferred_domain;
45 u64 flags;
46 enum ttm_bo_type type;
47 bool no_wait_gpu;
48 struct dma_resv *resv;
49};
50
51/* bo virtual addresses in a vm */
52struct amdgpu_bo_va_mapping {
53 struct amdgpu_bo_va *bo_va;
54 struct list_head list;
55 struct rb_node rb;
56 uint64_t start;
57 uint64_t last;
58 uint64_t __subtree_last;
59 uint64_t offset;
60 uint64_t flags;
61};
62
63/* User space allocated BO in a VM */
64struct amdgpu_bo_va {
65 struct amdgpu_vm_bo_base base;
66
67 /* protected by bo being reserved */
68 unsigned ref_count;
69
70 /* all other members protected by the VM PD being reserved */
71 struct dma_fence *last_pt_update;
72
73 /* mappings for this bo_va */
74 struct list_head invalids;
75 struct list_head valids;
76
77 /* If the mappings are cleared or filled */
78 bool cleared;
79
80 bool is_xgmi;
81};
82
83struct amdgpu_bo {
84 /* Protected by tbo.reserved */
85 u32 preferred_domains;
86 u32 allowed_domains;
87 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
88 struct ttm_placement placement;
89 struct ttm_buffer_object tbo;
90 struct ttm_bo_kmap_obj kmap;
91 u64 flags;
92 u64 tiling_flags;
93 u64 metadata_flags;
94 void *metadata;
95 u32 metadata_size;
96 unsigned prime_shared_count;
97 /* per VM structure for page tables and with virtual addresses */
98 struct amdgpu_vm_bo_base *vm_bo;
99 /* Constant after initialization */
100 struct amdgpu_bo *parent;
101 struct amdgpu_bo *shadow;
102
103 struct amdgpu_mn *mn;
104
105
106#ifdef CONFIG_MMU_NOTIFIER
107 struct mmu_interval_notifier notifier;
108#endif
109
110 struct list_head shadow_list;
111
112 struct kgd_mem *kfd_bo;
113};
114
115static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
116{
117 return container_of(tbo, struct amdgpu_bo, tbo);
118}
119
120/**
121 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
122 * @mem_type: ttm memory type
123 *
124 * Returns corresponding domain of the ttm mem_type
125 */
126static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
127{
128 switch (mem_type) {
129 case TTM_PL_VRAM:
130 return AMDGPU_GEM_DOMAIN_VRAM;
131 case TTM_PL_TT:
132 return AMDGPU_GEM_DOMAIN_GTT;
133 case TTM_PL_SYSTEM:
134 return AMDGPU_GEM_DOMAIN_CPU;
135 case AMDGPU_PL_GDS:
136 return AMDGPU_GEM_DOMAIN_GDS;
137 case AMDGPU_PL_GWS:
138 return AMDGPU_GEM_DOMAIN_GWS;
139 case AMDGPU_PL_OA:
140 return AMDGPU_GEM_DOMAIN_OA;
141 default:
142 break;
143 }
144 return 0;
145}
146
147/**
148 * amdgpu_bo_reserve - reserve bo
149 * @bo: bo structure
150 * @no_intr: don't return -ERESTARTSYS on pending signal
151 *
152 * Returns:
153 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
154 * a signal. Release all buffer reservations and return to user-space.
155 */
156static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
157{
158 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
159 int r;
160
161 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
162 if (unlikely(r != 0)) {
163 if (r != -ERESTARTSYS)
164 dev_err(adev->dev, "%p reserve failed\n", bo);
165 return r;
166 }
167 return 0;
168}
169
170static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
171{
172 ttm_bo_unreserve(&bo->tbo);
173}
174
175static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
176{
177 return bo->tbo.base.size;
178}
179
180static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
181{
182 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
183}
184
185static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
186{
187 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
188}
189
190/**
191 * amdgpu_bo_mmap_offset - return mmap offset of bo
192 * @bo: amdgpu object for which we query the offset
193 *
194 * Returns mmap offset of the object.
195 */
196static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
197{
198 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
199}
200
201/**
202 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
203 */
204static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
205{
206 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
207 unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
208 struct drm_mm_node *node = bo->tbo.mem.mm_node;
209 unsigned long pages_left;
210
211 if (bo->tbo.mem.mem_type != TTM_PL_VRAM)
212 return false;
213
214 for (pages_left = bo->tbo.mem.num_pages; pages_left;
215 pages_left -= node->size, node++)
216 if (node->start < fpfn)
217 return true;
218
219 return false;
220}
221
222/**
223 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
224 */
225static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
226{
227 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
228}
229
230/**
231 * amdgpu_bo_encrypted - test if the BO is encrypted
232 * @bo: pointer to a buffer object
233 *
234 * Return true if the buffer object is encrypted, false otherwise.
235 */
236static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
237{
238 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
239}
240
241bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
242void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
243
244int amdgpu_bo_create(struct amdgpu_device *adev,
245 struct amdgpu_bo_param *bp,
246 struct amdgpu_bo **bo_ptr);
247int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
248 unsigned long size, int align,
249 u32 domain, struct amdgpu_bo **bo_ptr,
250 u64 *gpu_addr, void **cpu_addr);
251int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
252 unsigned long size, int align,
253 u32 domain, struct amdgpu_bo **bo_ptr,
254 u64 *gpu_addr, void **cpu_addr);
255int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
256 uint64_t offset, uint64_t size, uint32_t domain,
257 struct amdgpu_bo **bo_ptr, void **cpu_addr);
258void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
259 void **cpu_addr);
260int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
261void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
262void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
263struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
264void amdgpu_bo_unref(struct amdgpu_bo **bo);
265int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
266int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
267 u64 min_offset, u64 max_offset);
268void amdgpu_bo_unpin(struct amdgpu_bo *bo);
269int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
270int amdgpu_bo_init(struct amdgpu_device *adev);
271void amdgpu_bo_fini(struct amdgpu_device *adev);
272int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
273 struct vm_area_struct *vma);
274int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
275void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
276int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
277 uint32_t metadata_size, uint64_t flags);
278int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
279 size_t buffer_size, uint32_t *metadata_size,
280 uint64_t *flags);
281void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
282 bool evict,
283 struct ttm_resource *new_mem);
284void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
285vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
286void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
287 bool shared);
288int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
289 enum amdgpu_sync_mode sync_mode, void *owner,
290 bool intr);
291int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
292u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
293u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
294int amdgpu_bo_validate(struct amdgpu_bo *bo);
295int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
296 struct dma_fence **fence);
297uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
298 uint32_t domain);
299
300/*
301 * sub allocation
302 */
303
304static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
305{
306 return sa_bo->manager->gpu_addr + sa_bo->soffset;
307}
308
309static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
310{
311 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
312}
313
314int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
315 struct amdgpu_sa_manager *sa_manager,
316 unsigned size, u32 align, u32 domain);
317void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
318 struct amdgpu_sa_manager *sa_manager);
319int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
320 struct amdgpu_sa_manager *sa_manager);
321int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
322 struct amdgpu_sa_bo **sa_bo,
323 unsigned size, unsigned align);
324void amdgpu_sa_bo_free(struct amdgpu_device *adev,
325 struct amdgpu_sa_bo **sa_bo,
326 struct dma_fence *fence);
327#if defined(CONFIG_DEBUG_FS)
328void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
329 struct seq_file *m);
330u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
331#endif
332int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
333
334bool amdgpu_bo_support_uswc(u64 bo_flags);
335
336
337#endif