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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
4 */
5#ifndef _ASM_POWERPC_BARRIER_H
6#define _ASM_POWERPC_BARRIER_H
7
8#include <asm/asm-const.h>
9
10#ifndef __ASSEMBLY__
11#include <asm/ppc-opcode.h>
12#endif
13
14/*
15 * Memory barrier.
16 * The sync instruction guarantees that all memory accesses initiated
17 * by this processor have been performed (with respect to all other
18 * mechanisms that access memory). The eieio instruction is a barrier
19 * providing an ordering (separately) for (a) cacheable stores and (b)
20 * loads and stores to non-cacheable memory (e.g. I/O devices).
21 *
22 * mb() prevents loads and stores being reordered across this point.
23 * rmb() prevents loads being reordered across this point.
24 * wmb() prevents stores being reordered across this point.
25 *
26 * *mb() variants without smp_ prefix must order all types of memory
27 * operations with one another. sync is the only instruction sufficient
28 * to do this.
29 *
30 * For the smp_ barriers, ordering is for cacheable memory operations
31 * only. We have to use the sync instruction for smp_mb(), since lwsync
32 * doesn't order loads with respect to previous stores. Lwsync can be
33 * used for smp_rmb() and smp_wmb().
34 *
35 * However, on CPUs that don't support lwsync, lwsync actually maps to a
36 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
37 */
38#define mb() __asm__ __volatile__ ("sync" : : : "memory")
39#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
40#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
41
42/* The sub-arch has lwsync */
43#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC)
44# define SMPWMB LWSYNC
45#else
46# define SMPWMB eieio
47#endif
48
49#define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
50#define dma_rmb() __lwsync()
51#define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
52
53#define __smp_lwsync() __lwsync()
54
55#define __smp_mb() mb()
56#define __smp_rmb() __lwsync()
57#define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
58
59/*
60 * This is a barrier which prevents following instructions from being
61 * started until the value of the argument x is known. For example, if
62 * x is a variable loaded from memory, this prevents following
63 * instructions from being executed until the load has been performed.
64 */
65#define data_barrier(x) \
66 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
67
68#define __smp_store_release(p, v) \
69do { \
70 compiletime_assert_atomic_type(*p); \
71 __smp_lwsync(); \
72 WRITE_ONCE(*p, v); \
73} while (0)
74
75#define __smp_load_acquire(p) \
76({ \
77 typeof(*p) ___p1 = READ_ONCE(*p); \
78 compiletime_assert_atomic_type(*p); \
79 __smp_lwsync(); \
80 ___p1; \
81})
82
83#ifdef CONFIG_PPC64
84#define smp_cond_load_relaxed(ptr, cond_expr) ({ \
85 typeof(ptr) __PTR = (ptr); \
86 __unqual_scalar_typeof(*ptr) VAL; \
87 VAL = READ_ONCE(*__PTR); \
88 if (unlikely(!(cond_expr))) { \
89 spin_begin(); \
90 do { \
91 VAL = READ_ONCE(*__PTR); \
92 } while (!(cond_expr)); \
93 spin_end(); \
94 } \
95 (typeof(*ptr))VAL; \
96})
97#endif
98
99#ifdef CONFIG_PPC_BOOK3S_64
100#define NOSPEC_BARRIER_SLOT nop
101#elif defined(CONFIG_PPC_FSL_BOOK3E)
102#define NOSPEC_BARRIER_SLOT nop; nop
103#endif
104
105#ifdef CONFIG_PPC_BARRIER_NOSPEC
106/*
107 * Prevent execution of subsequent instructions until preceding branches have
108 * been fully resolved and are no longer executing speculatively.
109 */
110#define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
111
112// This also acts as a compiler barrier due to the memory clobber.
113#define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
114
115#else /* !CONFIG_PPC_BARRIER_NOSPEC */
116#define barrier_nospec_asm
117#define barrier_nospec()
118#endif /* CONFIG_PPC_BARRIER_NOSPEC */
119
120/*
121 * pmem_wmb() ensures that all stores for which the modification
122 * are written to persistent storage by preceding dcbfps/dcbstps
123 * instructions have updated persistent storage before any data
124 * access or data transfer caused by subsequent instructions is
125 * initiated.
126 */
127#define pmem_wmb() __asm__ __volatile__(PPC_PHWSYNC ::: "memory")
128
129#include <asm-generic/barrier.h>
130
131#endif /* _ASM_POWERPC_BARRIER_H */