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1/*
2 * Virtio GPU Device
3 *
4 * Copyright Red Hat, Inc. 2013-2014
5 *
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
9 *
10 * This header is BSD licensed so anyone can use the definitions
11 * to implement compatible drivers/servers:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of IBM nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 */
37
38#ifndef VIRTIO_GPU_HW_H
39#define VIRTIO_GPU_HW_H
40
41#include <linux/types.h>
42
43/*
44 * VIRTIO_GPU_CMD_CTX_*
45 * VIRTIO_GPU_CMD_*_3D
46 */
47#define VIRTIO_GPU_F_VIRGL 0
48
49/*
50 * VIRTIO_GPU_CMD_GET_EDID
51 */
52#define VIRTIO_GPU_F_EDID 1
53/*
54 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
55 */
56#define VIRTIO_GPU_F_RESOURCE_UUID 2
57
58/*
59 * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
60 */
61#define VIRTIO_GPU_F_RESOURCE_BLOB 3
62
63enum virtio_gpu_ctrl_type {
64 VIRTIO_GPU_UNDEFINED = 0,
65
66 /* 2d commands */
67 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
68 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
69 VIRTIO_GPU_CMD_RESOURCE_UNREF,
70 VIRTIO_GPU_CMD_SET_SCANOUT,
71 VIRTIO_GPU_CMD_RESOURCE_FLUSH,
72 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
73 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
74 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
75 VIRTIO_GPU_CMD_GET_CAPSET_INFO,
76 VIRTIO_GPU_CMD_GET_CAPSET,
77 VIRTIO_GPU_CMD_GET_EDID,
78 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
79 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
80 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
81
82 /* 3d commands */
83 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
84 VIRTIO_GPU_CMD_CTX_DESTROY,
85 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
86 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
87 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
88 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
89 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
90 VIRTIO_GPU_CMD_SUBMIT_3D,
91 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
92 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
93
94 /* cursor commands */
95 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
96 VIRTIO_GPU_CMD_MOVE_CURSOR,
97
98 /* success responses */
99 VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
100 VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
101 VIRTIO_GPU_RESP_OK_CAPSET_INFO,
102 VIRTIO_GPU_RESP_OK_CAPSET,
103 VIRTIO_GPU_RESP_OK_EDID,
104 VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
105 VIRTIO_GPU_RESP_OK_MAP_INFO,
106
107 /* error responses */
108 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
109 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
110 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
111 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
112 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
113 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
114};
115
116enum virtio_gpu_shm_id {
117 VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
118 /*
119 * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
120 * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
121 */
122 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
123};
124
125#define VIRTIO_GPU_FLAG_FENCE (1 << 0)
126
127struct virtio_gpu_ctrl_hdr {
128 __le32 type;
129 __le32 flags;
130 __le64 fence_id;
131 __le32 ctx_id;
132 __le32 padding;
133};
134
135/* data passed in the cursor vq */
136
137struct virtio_gpu_cursor_pos {
138 __le32 scanout_id;
139 __le32 x;
140 __le32 y;
141 __le32 padding;
142};
143
144/* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
145struct virtio_gpu_update_cursor {
146 struct virtio_gpu_ctrl_hdr hdr;
147 struct virtio_gpu_cursor_pos pos; /* update & move */
148 __le32 resource_id; /* update only */
149 __le32 hot_x; /* update only */
150 __le32 hot_y; /* update only */
151 __le32 padding;
152};
153
154/* data passed in the control vq, 2d related */
155
156struct virtio_gpu_rect {
157 __le32 x;
158 __le32 y;
159 __le32 width;
160 __le32 height;
161};
162
163/* VIRTIO_GPU_CMD_RESOURCE_UNREF */
164struct virtio_gpu_resource_unref {
165 struct virtio_gpu_ctrl_hdr hdr;
166 __le32 resource_id;
167 __le32 padding;
168};
169
170/* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
171struct virtio_gpu_resource_create_2d {
172 struct virtio_gpu_ctrl_hdr hdr;
173 __le32 resource_id;
174 __le32 format;
175 __le32 width;
176 __le32 height;
177};
178
179/* VIRTIO_GPU_CMD_SET_SCANOUT */
180struct virtio_gpu_set_scanout {
181 struct virtio_gpu_ctrl_hdr hdr;
182 struct virtio_gpu_rect r;
183 __le32 scanout_id;
184 __le32 resource_id;
185};
186
187/* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
188struct virtio_gpu_resource_flush {
189 struct virtio_gpu_ctrl_hdr hdr;
190 struct virtio_gpu_rect r;
191 __le32 resource_id;
192 __le32 padding;
193};
194
195/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
196struct virtio_gpu_transfer_to_host_2d {
197 struct virtio_gpu_ctrl_hdr hdr;
198 struct virtio_gpu_rect r;
199 __le64 offset;
200 __le32 resource_id;
201 __le32 padding;
202};
203
204struct virtio_gpu_mem_entry {
205 __le64 addr;
206 __le32 length;
207 __le32 padding;
208};
209
210/* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
211struct virtio_gpu_resource_attach_backing {
212 struct virtio_gpu_ctrl_hdr hdr;
213 __le32 resource_id;
214 __le32 nr_entries;
215};
216
217/* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
218struct virtio_gpu_resource_detach_backing {
219 struct virtio_gpu_ctrl_hdr hdr;
220 __le32 resource_id;
221 __le32 padding;
222};
223
224/* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
225#define VIRTIO_GPU_MAX_SCANOUTS 16
226struct virtio_gpu_resp_display_info {
227 struct virtio_gpu_ctrl_hdr hdr;
228 struct virtio_gpu_display_one {
229 struct virtio_gpu_rect r;
230 __le32 enabled;
231 __le32 flags;
232 } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
233};
234
235/* data passed in the control vq, 3d related */
236
237struct virtio_gpu_box {
238 __le32 x, y, z;
239 __le32 w, h, d;
240};
241
242/* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
243struct virtio_gpu_transfer_host_3d {
244 struct virtio_gpu_ctrl_hdr hdr;
245 struct virtio_gpu_box box;
246 __le64 offset;
247 __le32 resource_id;
248 __le32 level;
249 __le32 stride;
250 __le32 layer_stride;
251};
252
253/* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
254#define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
255struct virtio_gpu_resource_create_3d {
256 struct virtio_gpu_ctrl_hdr hdr;
257 __le32 resource_id;
258 __le32 target;
259 __le32 format;
260 __le32 bind;
261 __le32 width;
262 __le32 height;
263 __le32 depth;
264 __le32 array_size;
265 __le32 last_level;
266 __le32 nr_samples;
267 __le32 flags;
268 __le32 padding;
269};
270
271/* VIRTIO_GPU_CMD_CTX_CREATE */
272struct virtio_gpu_ctx_create {
273 struct virtio_gpu_ctrl_hdr hdr;
274 __le32 nlen;
275 __le32 padding;
276 char debug_name[64];
277};
278
279/* VIRTIO_GPU_CMD_CTX_DESTROY */
280struct virtio_gpu_ctx_destroy {
281 struct virtio_gpu_ctrl_hdr hdr;
282};
283
284/* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
285struct virtio_gpu_ctx_resource {
286 struct virtio_gpu_ctrl_hdr hdr;
287 __le32 resource_id;
288 __le32 padding;
289};
290
291/* VIRTIO_GPU_CMD_SUBMIT_3D */
292struct virtio_gpu_cmd_submit {
293 struct virtio_gpu_ctrl_hdr hdr;
294 __le32 size;
295 __le32 padding;
296};
297
298#define VIRTIO_GPU_CAPSET_VIRGL 1
299#define VIRTIO_GPU_CAPSET_VIRGL2 2
300
301/* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
302struct virtio_gpu_get_capset_info {
303 struct virtio_gpu_ctrl_hdr hdr;
304 __le32 capset_index;
305 __le32 padding;
306};
307
308/* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
309struct virtio_gpu_resp_capset_info {
310 struct virtio_gpu_ctrl_hdr hdr;
311 __le32 capset_id;
312 __le32 capset_max_version;
313 __le32 capset_max_size;
314 __le32 padding;
315};
316
317/* VIRTIO_GPU_CMD_GET_CAPSET */
318struct virtio_gpu_get_capset {
319 struct virtio_gpu_ctrl_hdr hdr;
320 __le32 capset_id;
321 __le32 capset_version;
322};
323
324/* VIRTIO_GPU_RESP_OK_CAPSET */
325struct virtio_gpu_resp_capset {
326 struct virtio_gpu_ctrl_hdr hdr;
327 __u8 capset_data[];
328};
329
330/* VIRTIO_GPU_CMD_GET_EDID */
331struct virtio_gpu_cmd_get_edid {
332 struct virtio_gpu_ctrl_hdr hdr;
333 __le32 scanout;
334 __le32 padding;
335};
336
337/* VIRTIO_GPU_RESP_OK_EDID */
338struct virtio_gpu_resp_edid {
339 struct virtio_gpu_ctrl_hdr hdr;
340 __le32 size;
341 __le32 padding;
342 __u8 edid[1024];
343};
344
345#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
346
347struct virtio_gpu_config {
348 __le32 events_read;
349 __le32 events_clear;
350 __le32 num_scanouts;
351 __le32 num_capsets;
352};
353
354/* simple formats for fbcon/X use */
355enum virtio_gpu_formats {
356 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1,
357 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2,
358 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3,
359 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4,
360
361 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67,
362 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68,
363
364 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121,
365 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134,
366};
367
368/* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
369struct virtio_gpu_resource_assign_uuid {
370 struct virtio_gpu_ctrl_hdr hdr;
371 __le32 resource_id;
372 __le32 padding;
373};
374
375/* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
376struct virtio_gpu_resp_resource_uuid {
377 struct virtio_gpu_ctrl_hdr hdr;
378 __u8 uuid[16];
379};
380
381/* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
382struct virtio_gpu_resource_create_blob {
383 struct virtio_gpu_ctrl_hdr hdr;
384 __le32 resource_id;
385#define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001
386#define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002
387#define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003
388
389#define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001
390#define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002
391#define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
392 /* zero is invalid blob mem */
393 __le32 blob_mem;
394 __le32 blob_flags;
395 __le32 nr_entries;
396 __le64 blob_id;
397 __le64 size;
398 /*
399 * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
400 */
401};
402
403/* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
404struct virtio_gpu_set_scanout_blob {
405 struct virtio_gpu_ctrl_hdr hdr;
406 struct virtio_gpu_rect r;
407 __le32 scanout_id;
408 __le32 resource_id;
409 __le32 width;
410 __le32 height;
411 __le32 format;
412 __le32 padding;
413 __le32 strides[4];
414 __le32 offsets[4];
415};
416
417/* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
418struct virtio_gpu_resource_map_blob {
419 struct virtio_gpu_ctrl_hdr hdr;
420 __le32 resource_id;
421 __le32 padding;
422 __le64 offset;
423};
424
425/* VIRTIO_GPU_RESP_OK_MAP_INFO */
426#define VIRTIO_GPU_MAP_CACHE_MASK 0x0f
427#define VIRTIO_GPU_MAP_CACHE_NONE 0x00
428#define VIRTIO_GPU_MAP_CACHE_CACHED 0x01
429#define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
430#define VIRTIO_GPU_MAP_CACHE_WC 0x03
431struct virtio_gpu_resp_map_info {
432 struct virtio_gpu_ctrl_hdr hdr;
433 __u32 map_info;
434 __u32 padding;
435};
436
437/* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
438struct virtio_gpu_resource_unmap_blob {
439 struct virtio_gpu_ctrl_hdr hdr;
440 __le32 resource_id;
441 __le32 padding;
442};
443
444#endif