tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __SMU11_DRIVER_IF_VANGOGH_H__
24#define __SMU11_DRIVER_IF_VANGOGH_H__
25
26// *** IMPORTANT ***
27// SMU TEAM: Always increment the interface version if
28// any structure is changed in this file
29#define SMU13_DRIVER_IF_VERSION 2
30
31typedef struct {
32 int32_t value;
33 uint32_t numFractionalBits;
34} FloatInIntFormat_t;
35
36typedef enum {
37 DSPCLK_DCFCLK = 0,
38 DSPCLK_DISPCLK,
39 DSPCLK_PIXCLK,
40 DSPCLK_PHYCLK,
41 DSPCLK_COUNT,
42} DSPCLK_e;
43
44typedef struct {
45 uint16_t Freq; // in MHz
46 uint16_t Vid; // min voltage in SVI2 VID
47} DisplayClockTable_t;
48
49typedef struct {
50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MinMclk;
53 uint16_t MaxMclk;
54
55 uint8_t WmSetting;
56 uint8_t WmType; // Used for normal pstate change or memory retraining
57 uint8_t Padding[2];
58} WatermarkRowGeneric_t;
59
60#define NUM_WM_RANGES 4
61#define WM_PSTATE_CHG 0
62#define WM_RETRAINING 1
63
64typedef enum {
65 WM_SOCCLK = 0,
66 WM_DCFCLK,
67 WM_COUNT,
68} WM_CLOCK_e;
69
70typedef struct {
71 // Watermarks
72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
73
74 uint32_t MmHubPadding[7]; // SMU internal use
75} Watermarks_t;
76
77typedef enum {
78 CUSTOM_DPM_SETTING_GFXCLK,
79 CUSTOM_DPM_SETTING_CCLK,
80 CUSTOM_DPM_SETTING_FCLK_CCX,
81 CUSTOM_DPM_SETTING_FCLK_GFX,
82 CUSTOM_DPM_SETTING_FCLK_STALLS,
83 CUSTOM_DPM_SETTING_LCLK,
84 CUSTOM_DPM_SETTING_COUNT,
85} CUSTOM_DPM_SETTING_e;
86
87typedef struct {
88 uint8_t ActiveHystLimit;
89 uint8_t IdleHystLimit;
90 uint8_t FPS;
91 uint8_t MinActiveFreqType;
92 FloatInIntFormat_t MinActiveFreq;
93 FloatInIntFormat_t PD_Data_limit;
94 FloatInIntFormat_t PD_Data_time_constant;
95 FloatInIntFormat_t PD_Data_error_coeff;
96 FloatInIntFormat_t PD_Data_error_rate_coeff;
97} DpmActivityMonitorCoeffExt_t;
98
99typedef struct {
100 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
101} CustomDpmSettings_t;
102
103#define NUM_DCFCLK_DPM_LEVELS 7
104#define NUM_DISPCLK_DPM_LEVELS 7
105#define NUM_DPPCLK_DPM_LEVELS 7
106#define NUM_SOCCLK_DPM_LEVELS 7
107#define NUM_ISPICLK_DPM_LEVELS 7
108#define NUM_ISPXCLK_DPM_LEVELS 7
109#define NUM_VCN_DPM_LEVELS 5
110#define NUM_FCLK_DPM_LEVELS 4
111#define NUM_SOC_VOLTAGE_LEVELS 8
112
113typedef struct {
114 uint32_t fclk;
115 uint32_t memclk;
116 uint32_t voltage;
117} df_pstate_t;
118
119typedef struct {
120 uint32_t vclk;
121 uint32_t dclk;
122} vcn_clk_t;
123
124//Freq in MHz
125//Voltage in milli volts with 2 fractional bits
126
127typedef struct {
128 uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
129 uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
130 uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
131 uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
132 uint32_t IspiClocks[NUM_ISPICLK_DPM_LEVELS];
133 uint32_t IspxClocks[NUM_ISPXCLK_DPM_LEVELS];
134 vcn_clk_t VcnClocks[NUM_VCN_DPM_LEVELS];
135
136 uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
137
138 df_pstate_t DfPstateTable[NUM_FCLK_DPM_LEVELS];
139
140 uint32_t MinGfxClk;
141 uint32_t MaxGfxClk;
142
143 uint8_t NumDfPstatesEnabled;
144 uint8_t NumDpmLevelsEnabled;
145 uint8_t NumDcfclkLevelsEnabled;
146 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk
147 uint8_t NumSocClkLevelsEnabled;
148
149 uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk
150 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
151 uint8_t spare[2];
152} DpmClocks_t;
153
154
155// Throttler Status Bitmask
156#define THROTTLER_STATUS_BIT_SPL 0
157#define THROTTLER_STATUS_BIT_FPPT 1
158#define THROTTLER_STATUS_BIT_SPPT 2
159#define THROTTLER_STATUS_BIT_SPPT_APU 3
160#define THROTTLER_STATUS_BIT_THM_CORE 4
161#define THROTTLER_STATUS_BIT_THM_GFX 5
162#define THROTTLER_STATUS_BIT_THM_SOC 6
163#define THROTTLER_STATUS_BIT_TDC_VDD 7
164#define THROTTLER_STATUS_BIT_TDC_SOC 8
165#define THROTTLER_STATUS_BIT_TDC_GFX 9
166#define THROTTLER_STATUS_BIT_TDC_CVIP 10
167
168typedef struct {
169 uint16_t GfxclkFrequency; //[MHz]
170 uint16_t SocclkFrequency; //[MHz]
171 uint16_t VclkFrequency; //[MHz]
172 uint16_t DclkFrequency; //[MHz]
173 uint16_t MemclkFrequency; //[MHz]
174 uint16_t spare;
175
176 uint16_t GfxActivity; //[centi]
177 uint16_t UvdActivity; //[centi]
178
179 uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
180 uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
181 uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
182 uint16_t CurrentSocketPower; //[mW]
183
184 //3rd party tools in Windows need info in the case of APUs
185 uint16_t CoreFrequency[8]; //[MHz]
186 uint16_t CorePower[8]; //[mW]
187 uint16_t CoreTemperature[8]; //[centi-Celsius]
188 uint16_t L3Frequency[2]; //[MHz]
189 uint16_t L3Temperature[2]; //[centi-Celsius]
190
191 uint16_t GfxTemperature; //[centi-Celsius]
192 uint16_t SocTemperature; //[centi-Celsius]
193 uint16_t EdgeTemperature;
194 uint16_t ThrottlerStatus;
195} SmuMetrics_t;
196
197
198// Workload bits
199#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
200#define WORKLOAD_PPLIB_VIDEO_BIT 2
201#define WORKLOAD_PPLIB_VR_BIT 3
202#define WORKLOAD_PPLIB_COMPUTE_BIT 4
203#define WORKLOAD_PPLIB_CUSTOM_BIT 5
204#define WORKLOAD_PPLIB_COUNT 6
205
206#define TABLE_BIOS_IF 0 // Called by BIOS
207#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
208#define TABLE_CUSTOM_DPM 2 // Called by Driver
209#define TABLE_SPARE1 3
210#define TABLE_DPMCLOCKS 4 // Called by Driver
211#define TABLE_SPARE2 5 // Called by Tools
212#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
213#define TABLE_SMU_METRICS 7 // Called by Driver
214#define TABLE_COUNT 8
215
216//ISP tile definitions
217typedef enum {
218 TILE_ISPX = 0, // ISPX
219 TILE_ISPM, // ISPM
220 TILE_ISPC, // ISPCORE
221 TILE_ISPPRE, // ISPPRE
222 TILE_ISPPOST, // ISPPOST
223 TILE_MAX
224} TILE_NUM_e;
225
226// Tile Selection (Based on arguments)
227#define TILE_SEL_ISPX (1<<(TILE_ISPX))
228#define TILE_SEL_ISPM (1<<(TILE_ISPM))
229#define TILE_SEL_ISPC (1<<(TILE_ISPC))
230#define TILE_SEL_ISPPRE (1<<(TILE_ISPPRE))
231#define TILE_SEL_ISPPOST (1<<(TILE_ISPPOST))
232
233// Mask for ISP tiles in PGFSM PWR Status Registers
234//Bit[1:0] maps to ISPX, (ISPX)
235//Bit[3:2] maps to ISPM, (ISPM)
236//Bit[5:4] maps to ISPCORE, (ISPCORE)
237//Bit[7:6] maps to ISPPRE, (ISPPRE)
238//Bit[9:8] maps to POST, (ISPPOST
239#define TILE_ISPX_MASK ((1<<0) | (1<<1))
240#define TILE_ISPM_MASK ((1<<2) | (1<<3))
241#define TILE_ISPC_MASK ((1<<4) | (1<<5))
242#define TILE_ISPPRE_MASK ((1<<6) | (1<<7))
243#define TILE_ISPPOST_MASK ((1<<8) | (1<<9))
244
245#endif