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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright 2009 Freescale Semiconductor, Inc.
4 *
5 * provides masks and opcode images for use by code generation, emulation
6 * and for instructions that older assemblers might not know about
7 */
8#ifndef _ASM_POWERPC_PPC_OPCODE_H
9#define _ASM_POWERPC_PPC_OPCODE_H
10
11#include <asm/asm-const.h>
12
13#define __REG_R0 0
14#define __REG_R1 1
15#define __REG_R2 2
16#define __REG_R3 3
17#define __REG_R4 4
18#define __REG_R5 5
19#define __REG_R6 6
20#define __REG_R7 7
21#define __REG_R8 8
22#define __REG_R9 9
23#define __REG_R10 10
24#define __REG_R11 11
25#define __REG_R12 12
26#define __REG_R13 13
27#define __REG_R14 14
28#define __REG_R15 15
29#define __REG_R16 16
30#define __REG_R17 17
31#define __REG_R18 18
32#define __REG_R19 19
33#define __REG_R20 20
34#define __REG_R21 21
35#define __REG_R22 22
36#define __REG_R23 23
37#define __REG_R24 24
38#define __REG_R25 25
39#define __REG_R26 26
40#define __REG_R27 27
41#define __REG_R28 28
42#define __REG_R29 29
43#define __REG_R30 30
44#define __REG_R31 31
45
46#define __REGA0_0 0
47#define __REGA0_R1 1
48#define __REGA0_R2 2
49#define __REGA0_R3 3
50#define __REGA0_R4 4
51#define __REGA0_R5 5
52#define __REGA0_R6 6
53#define __REGA0_R7 7
54#define __REGA0_R8 8
55#define __REGA0_R9 9
56#define __REGA0_R10 10
57#define __REGA0_R11 11
58#define __REGA0_R12 12
59#define __REGA0_R13 13
60#define __REGA0_R14 14
61#define __REGA0_R15 15
62#define __REGA0_R16 16
63#define __REGA0_R17 17
64#define __REGA0_R18 18
65#define __REGA0_R19 19
66#define __REGA0_R20 20
67#define __REGA0_R21 21
68#define __REGA0_R22 22
69#define __REGA0_R23 23
70#define __REGA0_R24 24
71#define __REGA0_R25 25
72#define __REGA0_R26 26
73#define __REGA0_R27 27
74#define __REGA0_R28 28
75#define __REGA0_R29 29
76#define __REGA0_R30 30
77#define __REGA0_R31 31
78
79#define IMM_L(i) ((uintptr_t)(i) & 0xffff)
80#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
81#define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
82#define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
83#define IMM_D1(i) IMM_L(i)
84
85/*
86 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
87 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
88 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
89 */
90#define IMM_H(i) ((uintptr_t)(i)>>16)
91#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
92 (((uintptr_t)(i) & 0x8000) >> 15))
93
94
95/* opcode and xopcode for instructions */
96#define OP_TRAP 3
97#define OP_TRAP_64 2
98
99#define OP_31_XOP_TRAP 4
100#define OP_31_XOP_LDX 21
101#define OP_31_XOP_LWZX 23
102#define OP_31_XOP_LDUX 53
103#define OP_31_XOP_DCBST 54
104#define OP_31_XOP_LWZUX 55
105#define OP_31_XOP_TRAP_64 68
106#define OP_31_XOP_DCBF 86
107#define OP_31_XOP_LBZX 87
108#define OP_31_XOP_STDX 149
109#define OP_31_XOP_STWX 151
110#define OP_31_XOP_STDUX 181
111#define OP_31_XOP_STWUX 183
112#define OP_31_XOP_STBX 215
113#define OP_31_XOP_LBZUX 119
114#define OP_31_XOP_STBUX 247
115#define OP_31_XOP_LHZX 279
116#define OP_31_XOP_LHZUX 311
117#define OP_31_XOP_MSGSNDP 142
118#define OP_31_XOP_MSGCLRP 174
119#define OP_31_XOP_TLBIE 306
120#define OP_31_XOP_MFSPR 339
121#define OP_31_XOP_LWAX 341
122#define OP_31_XOP_LHAX 343
123#define OP_31_XOP_LWAUX 373
124#define OP_31_XOP_LHAUX 375
125#define OP_31_XOP_STHX 407
126#define OP_31_XOP_STHUX 439
127#define OP_31_XOP_MTSPR 467
128#define OP_31_XOP_DCBI 470
129#define OP_31_XOP_LDBRX 532
130#define OP_31_XOP_LWBRX 534
131#define OP_31_XOP_TLBSYNC 566
132#define OP_31_XOP_STDBRX 660
133#define OP_31_XOP_STWBRX 662
134#define OP_31_XOP_STFSX 663
135#define OP_31_XOP_STFSUX 695
136#define OP_31_XOP_STFDX 727
137#define OP_31_XOP_STFDUX 759
138#define OP_31_XOP_LHBRX 790
139#define OP_31_XOP_LFIWAX 855
140#define OP_31_XOP_LFIWZX 887
141#define OP_31_XOP_STHBRX 918
142#define OP_31_XOP_STFIWX 983
143
144/* VSX Scalar Load Instructions */
145#define OP_31_XOP_LXSDX 588
146#define OP_31_XOP_LXSSPX 524
147#define OP_31_XOP_LXSIWAX 76
148#define OP_31_XOP_LXSIWZX 12
149
150/* VSX Scalar Store Instructions */
151#define OP_31_XOP_STXSDX 716
152#define OP_31_XOP_STXSSPX 652
153#define OP_31_XOP_STXSIWX 140
154
155/* VSX Vector Load Instructions */
156#define OP_31_XOP_LXVD2X 844
157#define OP_31_XOP_LXVW4X 780
158
159/* VSX Vector Load and Splat Instruction */
160#define OP_31_XOP_LXVDSX 332
161
162/* VSX Vector Store Instructions */
163#define OP_31_XOP_STXVD2X 972
164#define OP_31_XOP_STXVW4X 908
165
166#define OP_31_XOP_LFSX 535
167#define OP_31_XOP_LFSUX 567
168#define OP_31_XOP_LFDX 599
169#define OP_31_XOP_LFDUX 631
170
171/* VMX Vector Load Instructions */
172#define OP_31_XOP_LVX 103
173
174/* VMX Vector Store Instructions */
175#define OP_31_XOP_STVX 231
176
177/* Prefixed Instructions */
178#define OP_PREFIX 1
179
180#define OP_31 31
181#define OP_LWZ 32
182#define OP_STFS 52
183#define OP_STFSU 53
184#define OP_STFD 54
185#define OP_STFDU 55
186#define OP_LD 58
187#define OP_LWZU 33
188#define OP_LBZ 34
189#define OP_LBZU 35
190#define OP_STW 36
191#define OP_STWU 37
192#define OP_STD 62
193#define OP_STB 38
194#define OP_STBU 39
195#define OP_LHZ 40
196#define OP_LHZU 41
197#define OP_LHA 42
198#define OP_LHAU 43
199#define OP_STH 44
200#define OP_STHU 45
201#define OP_LMW 46
202#define OP_STMW 47
203#define OP_LFS 48
204#define OP_LFSU 49
205#define OP_LFD 50
206#define OP_LFDU 51
207#define OP_STFS 52
208#define OP_STFSU 53
209#define OP_STFD 54
210#define OP_STFDU 55
211#define OP_LQ 56
212
213/* sorted alphabetically */
214#define PPC_INST_BCCTR_FLUSH 0x4c400420
215#define PPC_INST_COPY 0x7c20060c
216#define PPC_INST_DCBA 0x7c0005ec
217#define PPC_INST_DCBA_MASK 0xfc0007fe
218#define PPC_INST_ISEL 0x7c00001e
219#define PPC_INST_ISEL_MASK 0xfc00003e
220#define PPC_INST_LSWI 0x7c0004aa
221#define PPC_INST_LSWX 0x7c00042a
222#define PPC_INST_LWSYNC 0x7c2004ac
223#define PPC_INST_SYNC 0x7c0004ac
224#define PPC_INST_SYNC_MASK 0xfc0007fe
225#define PPC_INST_ISYNC 0x4c00012c
226#define PPC_INST_MCRXR 0x7c000400
227#define PPC_INST_MCRXR_MASK 0xfc0007fe
228#define PPC_INST_MFSPR_PVR 0x7c1f42a6
229#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
230#define PPC_INST_MTMSRD 0x7c000164
231#define PPC_INST_NOP 0x60000000
232#define PPC_INST_POPCNTB 0x7c0000f4
233#define PPC_INST_POPCNTB_MASK 0xfc0007fe
234#define PPC_INST_RFEBB 0x4c000124
235#define PPC_INST_RFID 0x4c000024
236#define PPC_INST_MFSPR_DSCR 0x7c1102a6
237#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
238#define PPC_INST_MTSPR_DSCR 0x7c1103a6
239#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
240#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
241#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
242#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
243#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
244#define PPC_INST_SC 0x44000002
245#define PPC_INST_STRING 0x7c00042a
246#define PPC_INST_STRING_MASK 0xfc0007fe
247#define PPC_INST_STRING_GEN_MASK 0xfc00067e
248#define PPC_INST_STSWI 0x7c0005aa
249#define PPC_INST_STSWX 0x7c00052a
250#define PPC_INST_TRECHKPT 0x7c0007dd
251#define PPC_INST_TRECLAIM 0x7c00075d
252#define PPC_INST_TSR 0x7c0005dd
253#define PPC_INST_LD 0xe8000000
254#define PPC_INST_STD 0xf8000000
255#define PPC_INST_MFLR 0x7c0802a6
256#define PPC_INST_MTCTR 0x7c0903a6
257#define PPC_INST_ADDI 0x38000000
258#define PPC_INST_ADDIS 0x3c000000
259#define PPC_INST_ADD 0x7c000214
260#define PPC_INST_BLR 0x4e800020
261#define PPC_INST_BCTR 0x4e800420
262#define PPC_INST_BCTRL 0x4e800421
263#define PPC_INST_DIVD 0x7c0003d2
264#define PPC_INST_RLDICR 0x78000004
265#define PPC_INST_ORI 0x60000000
266#define PPC_INST_ORIS 0x64000000
267#define PPC_INST_BRANCH 0x48000000
268#define PPC_INST_BRANCH_COND 0x40800000
269
270/* Prefixes */
271#define PPC_INST_LFS 0xc0000000
272#define PPC_INST_STFS 0xd0000000
273#define PPC_INST_LFD 0xc8000000
274#define PPC_INST_STFD 0xd8000000
275#define PPC_PREFIX_MLS 0x06000000
276#define PPC_PREFIX_8LS 0x04000000
277
278/* Prefixed instructions */
279#define PPC_INST_PLD 0xe4000000
280#define PPC_INST_PSTD 0xf4000000
281
282/* macros to insert fields into opcodes */
283#define ___PPC_RA(a) (((a) & 0x1f) << 16)
284#define ___PPC_RB(b) (((b) & 0x1f) << 11)
285#define ___PPC_RC(c) (((c) & 0x1f) << 6)
286#define ___PPC_RS(s) (((s) & 0x1f) << 21)
287#define ___PPC_RT(t) ___PPC_RS(t)
288#define ___PPC_R(r) (((r) & 0x1) << 16)
289#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
290#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
291#define __PPC_RA(a) ___PPC_RA(__REG_##a)
292#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
293#define __PPC_RB(b) ___PPC_RB(__REG_##b)
294#define __PPC_RS(s) ___PPC_RS(__REG_##s)
295#define __PPC_RT(t) ___PPC_RT(__REG_##t)
296#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
297#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
298#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
299#define __PPC_XT(s) __PPC_XS(s)
300#define __PPC_XSP(s) ((((s) & 0x1e) | (((s) >> 5) & 0x1)) << 21)
301#define __PPC_XTP(s) __PPC_XSP(s)
302#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
303#define __PPC_WC(w) (((w) & 0x3) << 21)
304#define __PPC_WS(w) (((w) & 0x1f) << 11)
305#define __PPC_SH(s) __PPC_WS(s)
306#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
307#define __PPC_MB(s) ___PPC_RC(s)
308#define __PPC_ME(s) (((s) & 0x1f) << 1)
309#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
310#define __PPC_ME64(s) __PPC_MB64(s)
311#define __PPC_BI(s) (((s) & 0x1f) << 16)
312#define __PPC_CT(t) (((t) & 0x0f) << 21)
313#define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
314#define __PPC_RC21 (0x1 << 10)
315#define __PPC_PRFX_R(r) (((r) & 0x1) << 20)
316
317/*
318 * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
319 * has high bit set, high 16 bits must be adjusted. These macros do that (stolen
320 * from binutils).
321 */
322#define PPC_LO(v) ((v) & 0xffff)
323#define PPC_HI(v) (((v) >> 16) & 0xffff)
324#define PPC_HA(v) PPC_HI((v) + 0x8000)
325
326/*
327 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
328 * larx with EH set as an illegal instruction.
329 */
330#ifdef CONFIG_PPC64
331#define __PPC_EH(eh) (((eh) & 0x1) << 0)
332#else
333#define __PPC_EH(eh) 0
334#endif
335
336/* Base instruction encoding */
337#define PPC_RAW_CP_ABORT (0x7c00068c)
338#define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b))
339#define PPC_RAW_DARN(t, l) (0x7c0005e6 | ___PPC_RT(t) | (((l) & 0x3) << 16))
340#define PPC_RAW_DCBAL(a, b) (0x7c2005ec | __PPC_RA(a) | __PPC_RB(b))
341#define PPC_RAW_DCBZL(a, b) (0x7c2007ec | __PPC_RA(a) | __PPC_RB(b))
342#define PPC_RAW_LQARX(t, a, b, eh) (0x7c000228 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
343#define PPC_RAW_LDARX(t, a, b, eh) (0x7c0000a8 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
344#define PPC_RAW_LWARX(t, a, b, eh) (0x7c000028 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
345#define PPC_RAW_PHWSYNC (0x7c8004ac)
346#define PPC_RAW_PLWSYNC (0x7ca004ac)
347#define PPC_RAW_STQCX(t, a, b) (0x7c00016d | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
348#define PPC_RAW_MADDHD(t, a, b, c) (0x10000030 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
349#define PPC_RAW_MADDHDU(t, a, b, c) (0x10000031 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
350#define PPC_RAW_MADDLD(t, a, b, c) (0x10000033 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
351#define PPC_RAW_MSGSND(b) (0x7c00019c | ___PPC_RB(b))
352#define PPC_RAW_MSGSYNC (0x7c0006ec)
353#define PPC_RAW_MSGCLR(b) (0x7c0001dc | ___PPC_RB(b))
354#define PPC_RAW_MSGSNDP(b) (0x7c00011c | ___PPC_RB(b))
355#define PPC_RAW_MSGCLRP(b) (0x7c00015c | ___PPC_RB(b))
356#define PPC_RAW_PASTE(a, b) (0x7c20070d | ___PPC_RA(a) | ___PPC_RB(b))
357#define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s))
358#define PPC_RAW_POPCNTD(a, s) (0x7c0003f4 | __PPC_RA(a) | __PPC_RS(s))
359#define PPC_RAW_POPCNTW(a, s) (0x7c0002f4 | __PPC_RA(a) | __PPC_RS(s))
360#define PPC_RAW_RFCI (0x4c000066)
361#define PPC_RAW_RFDI (0x4c00004e)
362#define PPC_RAW_RFMCI (0x4c00004c)
363#define PPC_RAW_TLBILX(t, a, b) (0x7c000024 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
364#define PPC_RAW_WAIT(w) (0x7c00007c | __PPC_WC(w))
365#define PPC_RAW_TLBIE(lp, a) (0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
366#define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
367 (0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
368#define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
369 (0x7c000224 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
370#define PPC_RAW_TLBSRX_DOT(a, b) (0x7c0006a5 | __PPC_RA0(a) | __PPC_RB(b))
371#define PPC_RAW_TLBIVAX(a, b) (0x7c000624 | __PPC_RA0(a) | __PPC_RB(b))
372#define PPC_RAW_ERATWE(s, a, w) (0x7c0001a6 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
373#define PPC_RAW_ERATRE(s, a, w) (0x7c000166 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
374#define PPC_RAW_ERATILX(t, a, b) (0x7c000066 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
375#define PPC_RAW_ERATIVAX(s, a, b) (0x7c000666 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
376#define PPC_RAW_ERATSX(t, a, w) (0x7c000126 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
377#define PPC_RAW_ERATSX_DOT(t, a, w) (0x7c000127 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
378#define PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | __PPC_RT(t) | __PPC_RB(b))
379#define __PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | ___PPC_RT(t) | ___PPC_RB(b))
380#define PPC_RAW_ICBT(c, a, b) (0x7c00002c | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
381#define PPC_RAW_LBZCIX(t, a, b) (0x7c0006aa | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
382#define PPC_RAW_STBCIX(s, a, b) (0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
383#define PPC_RAW_DCBFPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
384#define PPC_RAW_DCBSTPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
385/*
386 * Define what the VSX XX1 form instructions will look like, then add
387 * the 128 bit load store instructions based on that.
388 */
389#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
390#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
391#define PPC_RAW_STXVD2X(s, a, b) (0x7c000798 | VSX_XX1((s), a, b))
392#define PPC_RAW_LXVD2X(s, a, b) (0x7c000698 | VSX_XX1((s), a, b))
393#define PPC_RAW_MFVRD(a, t) (0x7c000066 | VSX_XX1((t) + 32, a, R0))
394#define PPC_RAW_MTVRD(t, a) (0x7c000166 | VSX_XX1((t) + 32, a, R0))
395#define PPC_RAW_VPMSUMW(t, a, b) (0x10000488 | VSX_XX3((t), a, b))
396#define PPC_RAW_VPMSUMD(t, a, b) (0x100004c8 | VSX_XX3((t), a, b))
397#define PPC_RAW_XXLOR(t, a, b) (0xf0000490 | VSX_XX3((t), a, b))
398#define PPC_RAW_XXSWAPD(t, a) (0xf0000250 | VSX_XX3((t), a, a))
399#define PPC_RAW_XVCPSGNDP(t, a, b) ((0xf0000780 | VSX_XX3((t), (a), (b))))
400#define PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc) \
401 ((0x1000002d | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
402#define PPC_RAW_LXVP(xtp, a, i) (0x18000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_DQ(i))
403#define PPC_RAW_STXVP(xsp, a, i) (0x18000001 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_DQ(i))
404#define PPC_RAW_LXVPX(xtp, a, b) (0x7c00029a | __PPC_XTP(xtp) | ___PPC_RA(a) | ___PPC_RB(b))
405#define PPC_RAW_STXVPX(xsp, a, b) (0x7c00039a | __PPC_XSP(xsp) | ___PPC_RA(a) | ___PPC_RB(b))
406#define PPC_RAW_PLXVP(xtp, i, a, pr) \
407 ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) << 32 | (0xe8000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_D1(i)))
408#define PPC_RAW_PSTXVP(xsp, i, a, pr) \
409 ((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) << 32 | (0xf8000000 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_D1(i)))
410#define PPC_RAW_NAP (0x4c000364)
411#define PPC_RAW_SLEEP (0x4c0003a4)
412#define PPC_RAW_WINKLE (0x4c0003e4)
413#define PPC_RAW_STOP (0x4c0002e4)
414#define PPC_RAW_CLRBHRB (0x7c00035c)
415#define PPC_RAW_MFBHRBE(r, n) (0x7c00025c | __PPC_RT(r) | (((n) & 0x3ff) << 11))
416#define PPC_RAW_TRECHKPT (PPC_INST_TRECHKPT)
417#define PPC_RAW_TRECLAIM(r) (PPC_INST_TRECLAIM | __PPC_RA(r))
418#define PPC_RAW_TABORT(r) (0x7c00071d | __PPC_RA(r))
419#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
420#define PPC_RAW_MTTMR(tmr, r) (0x7c0003dc | TMRN(tmr) | ___PPC_RS(r))
421#define PPC_RAW_MFTMR(tmr, r) (0x7c0002dc | TMRN(tmr) | ___PPC_RT(r))
422#define PPC_RAW_ICSWX(s, a, b) (0x7c00032d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
423#define PPC_RAW_ICSWEPX(s, a, b) (0x7c00076d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
424#define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21))
425#define PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb) \
426 (0x100000c7 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
427#define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
428 (0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
429#define PPC_RAW_LD(r, base, i) (PPC_INST_LD | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
430#define PPC_RAW_LWZ(r, base, i) (0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
431#define PPC_RAW_LWZX(t, a, b) (0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
432#define PPC_RAW_STD(r, base, i) (PPC_INST_STD | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
433#define PPC_RAW_STDCX(s, a, b) (0x7c0001ad | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
434#define PPC_RAW_LFSX(t, a, b) (0x7c00042e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
435#define PPC_RAW_STFSX(s, a, b) (0x7c00052e | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
436#define PPC_RAW_LFDX(t, a, b) (0x7c0004ae | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
437#define PPC_RAW_STFDX(s, a, b) (0x7c0005ae | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
438#define PPC_RAW_LVX(t, a, b) (0x7c0000ce | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
439#define PPC_RAW_STVX(s, a, b) (0x7c0001ce | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
440#define PPC_RAW_ADD(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
441#define PPC_RAW_ADD_DOT(t, a, b) (PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
442#define PPC_RAW_ADDC(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
443#define PPC_RAW_ADDC_DOT(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
444#define PPC_RAW_NOP() (PPC_INST_NOP)
445#define PPC_RAW_BLR() (PPC_INST_BLR)
446#define PPC_RAW_BLRL() (0x4e800021)
447#define PPC_RAW_MTLR(r) (0x7c0803a6 | ___PPC_RT(r))
448#define PPC_RAW_BCTR() (PPC_INST_BCTR)
449#define PPC_RAW_MTCTR(r) (PPC_INST_MTCTR | ___PPC_RT(r))
450#define PPC_RAW_ADDI(d, a, i) (PPC_INST_ADDI | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
451#define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i)
452#define PPC_RAW_ADDIS(d, a, i) (PPC_INST_ADDIS | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
453#define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i)
454#define PPC_RAW_STDX(r, base, b) (0x7c00012a | ___PPC_RS(r) | ___PPC_RA(base) | ___PPC_RB(b))
455#define PPC_RAW_STDU(r, base, i) (0xf8000001 | ___PPC_RS(r) | ___PPC_RA(base) | ((i) & 0xfffc))
456#define PPC_RAW_STW(r, base, i) (0x90000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
457#define PPC_RAW_STWU(r, base, i) (0x94000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
458#define PPC_RAW_STH(r, base, i) (0xb0000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
459#define PPC_RAW_STB(r, base, i) (0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
460#define PPC_RAW_LBZ(r, base, i) (0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
461#define PPC_RAW_LDX(r, base, b) (0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
462#define PPC_RAW_LHZ(r, base, i) (0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
463#define PPC_RAW_LHBRX(r, base, b) (0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
464#define PPC_RAW_LDBRX(r, base, b) (0x7c000428 | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
465#define PPC_RAW_STWCX(s, a, b) (0x7c00012d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
466#define PPC_RAW_CMPWI(a, i) (0x2c000000 | ___PPC_RA(a) | IMM_L(i))
467#define PPC_RAW_CMPDI(a, i) (0x2c200000 | ___PPC_RA(a) | IMM_L(i))
468#define PPC_RAW_CMPW(a, b) (0x7c000000 | ___PPC_RA(a) | ___PPC_RB(b))
469#define PPC_RAW_CMPD(a, b) (0x7c200000 | ___PPC_RA(a) | ___PPC_RB(b))
470#define PPC_RAW_CMPLWI(a, i) (0x28000000 | ___PPC_RA(a) | IMM_L(i))
471#define PPC_RAW_CMPLDI(a, i) (0x28200000 | ___PPC_RA(a) | IMM_L(i))
472#define PPC_RAW_CMPLW(a, b) (0x7c000040 | ___PPC_RA(a) | ___PPC_RB(b))
473#define PPC_RAW_CMPLD(a, b) (0x7c200040 | ___PPC_RA(a) | ___PPC_RB(b))
474#define PPC_RAW_SUB(d, a, b) (0x7c000050 | ___PPC_RT(d) | ___PPC_RB(a) | ___PPC_RA(b))
475#define PPC_RAW_MULD(d, a, b) (0x7c0001d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
476#define PPC_RAW_MULW(d, a, b) (0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
477#define PPC_RAW_MULHWU(d, a, b) (0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
478#define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
479#define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
480#define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
481#define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
482#define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
483#define PPC_RAW_DIVDEU(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
484#define PPC_RAW_DIVDEU_DOT(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
485#define PPC_RAW_AND(d, a, b) (0x7c000038 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
486#define PPC_RAW_ANDI(d, a, i) (0x70000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
487#define PPC_RAW_AND_DOT(d, a, b) (0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
488#define PPC_RAW_OR(d, a, b) (0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
489#define PPC_RAW_MR(d, a) PPC_RAW_OR(d, a, a)
490#define PPC_RAW_ORI(d, a, i) (PPC_INST_ORI | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
491#define PPC_RAW_ORIS(d, a, i) (PPC_INST_ORIS | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
492#define PPC_RAW_XOR(d, a, b) (0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
493#define PPC_RAW_XORI(d, a, i) (0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
494#define PPC_RAW_XORIS(d, a, i) (0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
495#define PPC_RAW_EXTSW(d, a) (0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
496#define PPC_RAW_SLW(d, a, s) (0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
497#define PPC_RAW_SLD(d, a, s) (0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
498#define PPC_RAW_SRW(d, a, s) (0x7c000430 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
499#define PPC_RAW_SRAW(d, a, s) (0x7c000630 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
500#define PPC_RAW_SRAWI(d, a, i) (0x7c000670 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i))
501#define PPC_RAW_SRD(d, a, s) (0x7c000436 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
502#define PPC_RAW_SRAD(d, a, s) (0x7c000634 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
503#define PPC_RAW_SRADI(d, a, i) (0x7c000674 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i))
504#define PPC_RAW_RLWINM(d, a, i, mb, me) (0x54000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
505#define PPC_RAW_RLWINM_DOT(d, a, i, mb, me) \
506 (0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
507#define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
508#define PPC_RAW_RLDICL(d, a, i, mb) (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb))
509#define PPC_RAW_RLDICR(d, a, i, me) (PPC_INST_RLDICR | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me))
510
511/* slwi = rlwinm Rx, Ry, n, 0, 31-n */
512#define PPC_RAW_SLWI(d, a, i) PPC_RAW_RLWINM(d, a, i, 0, 31-(i))
513/* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
514#define PPC_RAW_SRWI(d, a, i) PPC_RAW_RLWINM(d, a, 32-(i), i, 31)
515/* sldi = rldicr Rx, Ry, n, 63-n */
516#define PPC_RAW_SLDI(d, a, i) PPC_RAW_RLDICR(d, a, i, 63-(i))
517/* sldi = rldicl Rx, Ry, 64-n, n */
518#define PPC_RAW_SRDI(d, a, i) PPC_RAW_RLDICL(d, a, 64-(i), i)
519
520#define PPC_RAW_NEG(d, a) (0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a))
521
522#define PPC_RAW_MFSPR(d, spr) (0x7c0002a6 | ___PPC_RT(d) | __PPC_SPR(spr))
523
524/* Deal with instructions that older assemblers aren't aware of */
525#define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
526#define PPC_CP_ABORT stringify_in_c(.long PPC_RAW_CP_ABORT)
527#define PPC_COPY(a, b) stringify_in_c(.long PPC_RAW_COPY(a, b))
528#define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l))
529#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b))
530#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b))
531#define PPC_DIVDE(t, a, b) stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
532#define PPC_DIVDEU(t, a, b) stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
533#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
534#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh))
535#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LWARX(t, a, b, eh))
536#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
537#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
538#define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
539#define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDLD(t, a, b, c))
540#define PPC_MSGSND(b) stringify_in_c(.long PPC_RAW_MSGSND(b))
541#define PPC_MSGSYNC stringify_in_c(.long PPC_RAW_MSGSYNC)
542#define PPC_MSGCLR(b) stringify_in_c(.long PPC_RAW_MSGCLR(b))
543#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_RAW_MSGSNDP(b))
544#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_RAW_MSGCLRP(b))
545#define PPC_PASTE(a, b) stringify_in_c(.long PPC_RAW_PASTE(a, b))
546#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_RAW_POPCNTB(a, s))
547#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_RAW_POPCNTD(a, s))
548#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_RAW_POPCNTW(a, s))
549#define PPC_RFCI stringify_in_c(.long PPC_RAW_RFCI)
550#define PPC_RFDI stringify_in_c(.long PPC_RAW_RFDI)
551#define PPC_RFMCI stringify_in_c(.long PPC_RAW_RFMCI)
552#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_RAW_TLBILX(t, a, b))
553#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
554#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
555#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
556#define PPC_WAIT(w) stringify_in_c(.long PPC_RAW_WAIT(w))
557#define PPC_TLBIE(lp, a) stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
558#define PPC_TLBIE_5(rb, rs, ric, prs, r) \
559 stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
560#define PPC_TLBIEL(rb,rs,ric,prs,r) \
561 stringify_in_c(.long PPC_RAW_TLBIEL(rb, rs, ric, prs, r))
562#define PPC_TLBSRX_DOT(a, b) stringify_in_c(.long PPC_RAW_TLBSRX_DOT(a, b))
563#define PPC_TLBIVAX(a, b) stringify_in_c(.long PPC_RAW_TLBIVAX(a, b))
564
565#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_RAW_ERATWE(s, a, w))
566#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_RAW_ERATRE(a, a, w))
567#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_RAW_ERATILX(t, a, b))
568#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_RAW_ERATIVAX(s, a, b))
569#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX(t, a, w))
570#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX_DOT(t, a, w))
571#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_RAW_SLBFEE_DOT(t, b))
572#define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long __PPC_RAW_SLBFEE_DOT(t, b))
573#define PPC_ICBT(c, a, b) stringify_in_c(.long PPC_RAW_ICBT(c, a, b))
574/* PASemi instructions */
575#define LBZCIX(t, a, b) stringify_in_c(.long PPC_RAW_LBZCIX(t, a, b))
576#define STBCIX(s, a, b) stringify_in_c(.long PPC_RAW_STBCIX(s, a, b))
577#define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_RAW_DCBFPS(a, b))
578#define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_RAW_DCBSTPS(a, b))
579#define PPC_PHWSYNC stringify_in_c(.long PPC_RAW_PHWSYNC)
580#define PPC_PLWSYNC stringify_in_c(.long PPC_RAW_PLWSYNC)
581#define STXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_STXVD2X(s, a, b))
582#define LXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_LXVD2X(s, a, b))
583#define MFVRD(a, t) stringify_in_c(.long PPC_RAW_MFVRD(a, t))
584#define MTVRD(t, a) stringify_in_c(.long PPC_RAW_MTVRD(t, a))
585#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMW(t, a, b))
586#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMD(t, a, b))
587#define XXLOR(t, a, b) stringify_in_c(.long PPC_RAW_XXLOR(t, a, b))
588#define XXSWAPD(t, a) stringify_in_c(.long PPC_RAW_XXSWAPD(t, a))
589#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_RAW_XVCPSGNDP(t, a, b)))
590
591#define VPERMXOR(vrt, vra, vrb, vrc) \
592 stringify_in_c(.long (PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc)))
593
594#define PPC_NAP stringify_in_c(.long PPC_RAW_NAP)
595#define PPC_SLEEP stringify_in_c(.long PPC_RAW_SLEEP)
596#define PPC_WINKLE stringify_in_c(.long PPC_RAW_WINKLE)
597
598#define PPC_STOP stringify_in_c(.long PPC_RAW_STOP)
599
600/* BHRB instructions */
601#define PPC_CLRBHRB stringify_in_c(.long PPC_RAW_CLRBHRB)
602#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_RAW_MFBHRBE(r, n))
603
604/* Transactional memory instructions */
605#define TRECHKPT stringify_in_c(.long PPC_RAW_TRECHKPT)
606#define TRECLAIM(r) stringify_in_c(.long PPC_RAW_TRECLAIM(r))
607#define TABORT(r) stringify_in_c(.long PPC_RAW_TABORT(r))
608
609/* book3e thread control instructions */
610#define MTTMR(tmr, r) stringify_in_c(.long PPC_RAW_MTTMR(tmr, r))
611#define MFTMR(tmr, r) stringify_in_c(.long PPC_RAW_MFTMR(tmr, r))
612
613/* Coprocessor instructions */
614#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWX(s, a, b))
615#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWEPX(s, a, b))
616
617#define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH))
618
619/*
620 * These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
621 * implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
622 * mode (on HPT these would also invalidate various SLBEs which may not be
623 * desired).
624 */
625#define PPC_ISA_3_0_INVALIDATE_ERAT PPC_SLBIA(7)
626#define PPC_RADIX_INVALIDATE_ERAT_USER PPC_SLBIA(3)
627#define PPC_RADIX_INVALIDATE_ERAT_GUEST PPC_SLBIA(6)
628
629#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb))
630
631#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb))
632
633#endif /* _ASM_POWERPC_PPC_OPCODE_H */