tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1&l4_wkup { /* 0x44c00000 */
2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
5 clock-names = "fck";
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
16
17 segment@0 { /* 0x44c00000 */
18 compatible = "simple-pm-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
22 <0x00000800 0x00000800 0x000800>, /* ap 1 */
23 <0x00001000 0x00001000 0x000400>, /* ap 2 */
24 <0x00001400 0x00001400 0x000400>; /* ap 3 */
25 };
26
27 segment@100000 { /* 0x44d00000 */
28 compatible = "simple-pm-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
32 <0x00004000 0x00104000 0x001000>, /* ap 5 */
33 <0x00080000 0x00180000 0x002000>, /* ap 6 */
34 <0x00082000 0x00182000 0x001000>; /* ap 7 */
35
36 target-module@0 { /* 0x44d00000, ap 4 28.0 */
37 compatible = "ti,sysc-omap4", "ti,sysc";
38 reg = <0x0 0x4>;
39 reg-names = "rev";
40 clocks = <&l4_wkup_aon_clkctrl AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL 0>;
41 clock-names = "fck";
42 #address-cells = <1>;
43 #size-cells = <1>;
44 ranges = <0x00000000 0x00000000 0x4000>,
45 <0x00080000 0x00080000 0x2000>;
46
47 wkup_m3: cpu@0 {
48 compatible = "ti,am3352-wkup-m3";
49 reg = <0x00000000 0x4000>,
50 <0x00080000 0x2000>;
51 reg-names = "umem", "dmem";
52 resets = <&prm_wkup 3>;
53 reset-names = "rstctrl";
54 ti,pm-firmware = "am335x-pm-firmware.elf";
55 };
56 };
57 };
58
59 segment@200000 { /* 0x44e00000 */
60 compatible = "simple-pm-bus";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
64 <0x00002000 0x00202000 0x001000>, /* ap 9 */
65 <0x00003000 0x00203000 0x001000>, /* ap 10 */
66 <0x00004000 0x00204000 0x001000>, /* ap 11 */
67 <0x00005000 0x00205000 0x001000>, /* ap 12 */
68 <0x00006000 0x00206000 0x001000>, /* ap 13 */
69 <0x00007000 0x00207000 0x001000>, /* ap 14 */
70 <0x00008000 0x00208000 0x001000>, /* ap 15 */
71 <0x00009000 0x00209000 0x001000>, /* ap 16 */
72 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
73 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
74 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
75 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
76 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
77 <0x00010000 0x00210000 0x010000>, /* ap 22 */
78 <0x00020000 0x00220000 0x010000>, /* ap 23 */
79 <0x00030000 0x00230000 0x001000>, /* ap 24 */
80 <0x00031000 0x00231000 0x001000>, /* ap 25 */
81 <0x00032000 0x00232000 0x001000>, /* ap 26 */
82 <0x00033000 0x00233000 0x001000>, /* ap 27 */
83 <0x00034000 0x00234000 0x001000>, /* ap 28 */
84 <0x00035000 0x00235000 0x001000>, /* ap 29 */
85 <0x00036000 0x00236000 0x001000>, /* ap 30 */
86 <0x00037000 0x00237000 0x001000>, /* ap 31 */
87 <0x00038000 0x00238000 0x001000>, /* ap 32 */
88 <0x00039000 0x00239000 0x001000>, /* ap 33 */
89 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */
90 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */
91 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */
92 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */
93 <0x00040000 0x00240000 0x040000>, /* ap 38 */
94 <0x00080000 0x00280000 0x001000>; /* ap 39 */
95
96 target-module@0 { /* 0x44e00000, ap 8 58.0 */
97 compatible = "ti,sysc-omap4", "ti,sysc";
98 reg = <0 0x4>;
99 reg-names = "rev";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0x0 0x0 0x2000>;
103
104 prcm: prcm@0 {
105 compatible = "ti,am3-prcm", "simple-bus";
106 reg = <0 0x2000>;
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges = <0 0 0x2000>;
110
111 prcm_clocks: clocks {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 };
115
116 prcm_clockdomains: clockdomains {
117 };
118 };
119 };
120
121 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
122 compatible = "ti,sysc";
123 status = "disabled";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 ranges = <0x0 0x3000 0x1000>;
127 };
128
129 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
130 compatible = "ti,sysc";
131 status = "disabled";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges = <0x0 0x5000 0x1000>;
135 };
136
137 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
138 compatible = "ti,sysc-omap2", "ti,sysc";
139 reg = <0x7000 0x4>,
140 <0x7010 0x4>,
141 <0x7114 0x4>;
142 reg-names = "rev", "sysc", "syss";
143 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
144 SYSC_OMAP2_SOFTRESET |
145 SYSC_OMAP2_AUTOIDLE)>;
146 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
147 <SYSC_IDLE_NO>,
148 <SYSC_IDLE_SMART>,
149 <SYSC_IDLE_SMART_WKUP>;
150 ti,syss-mask = <1>;
151 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
152 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
153 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
154 clock-names = "fck", "dbclk";
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges = <0x0 0x7000 0x1000>;
158
159 gpio0: gpio@0 {
160 compatible = "ti,omap4-gpio";
161 gpio-ranges = <&am33xx_pinmux 0 82 8>,
162 <&am33xx_pinmux 8 52 4>,
163 <&am33xx_pinmux 12 94 4>,
164 <&am33xx_pinmux 16 71 2>,
165 <&am33xx_pinmux 18 135 1>,
166 <&am33xx_pinmux 19 108 2>,
167 <&am33xx_pinmux 21 73 1>,
168 <&am33xx_pinmux 22 8 2>,
169 <&am33xx_pinmux 26 10 2>,
170 <&am33xx_pinmux 28 74 1>,
171 <&am33xx_pinmux 29 81 1>,
172 <&am33xx_pinmux 30 28 2>;
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
176 #interrupt-cells = <2>;
177 reg = <0x0 0x1000>;
178 interrupts = <96>;
179 };
180 };
181
182 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
183 compatible = "ti,sysc-omap2", "ti,sysc";
184 reg = <0x9050 0x4>,
185 <0x9054 0x4>,
186 <0x9058 0x4>;
187 reg-names = "rev", "sysc", "syss";
188 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
189 SYSC_OMAP2_SOFTRESET |
190 SYSC_OMAP2_AUTOIDLE)>;
191 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
192 <SYSC_IDLE_NO>,
193 <SYSC_IDLE_SMART>,
194 <SYSC_IDLE_SMART_WKUP>;
195 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
196 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
197 clock-names = "fck";
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges = <0x0 0x9000 0x1000>;
201
202 uart0: serial@0 {
203 compatible = "ti,am3352-uart", "ti,omap3-uart";
204 clock-frequency = <48000000>;
205 reg = <0x0 0x1000>;
206 interrupts = <72>;
207 status = "disabled";
208 dmas = <&edma 26 0>, <&edma 27 0>;
209 dma-names = "tx", "rx";
210 };
211 };
212
213 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
214 compatible = "ti,sysc-omap2", "ti,sysc";
215 reg = <0xb000 0x8>,
216 <0xb010 0x8>,
217 <0xb090 0x8>;
218 reg-names = "rev", "sysc", "syss";
219 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
220 SYSC_OMAP2_ENAWAKEUP |
221 SYSC_OMAP2_SOFTRESET |
222 SYSC_OMAP2_AUTOIDLE)>;
223 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
224 <SYSC_IDLE_NO>,
225 <SYSC_IDLE_SMART>,
226 <SYSC_IDLE_SMART_WKUP>;
227 ti,syss-mask = <1>;
228 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
229 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
230 clock-names = "fck";
231 #address-cells = <1>;
232 #size-cells = <1>;
233 ranges = <0x0 0xb000 0x1000>;
234
235 i2c0: i2c@0 {
236 compatible = "ti,omap4-i2c";
237 #address-cells = <1>;
238 #size-cells = <0>;
239 reg = <0x0 0x1000>;
240 interrupts = <70>;
241 status = "disabled";
242 };
243 };
244
245 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
246 compatible = "ti,sysc-omap4", "ti,sysc";
247 reg = <0xd000 0x4>,
248 <0xd010 0x4>;
249 reg-names = "rev", "sysc";
250 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
251 <SYSC_IDLE_NO>,
252 <SYSC_IDLE_SMART>,
253 <SYSC_IDLE_SMART_WKUP>;
254 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
255 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
256 clock-names = "fck";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 ranges = <0x00000000 0x0000d000 0x00001000>,
260 <0x00001000 0x0000e000 0x00001000>;
261
262 tscadc: tscadc@0 {
263 compatible = "ti,am3359-tscadc";
264 reg = <0x0 0x1000>;
265 interrupts = <16>;
266 status = "disabled";
267 dmas = <&edma 53 0>, <&edma 57 0>;
268 dma-names = "fifo0", "fifo1";
269
270 tsc {
271 compatible = "ti,am3359-tsc";
272 };
273 am335x_adc: adc {
274 #io-channel-cells = <1>;
275 compatible = "ti,am3359-adc";
276 };
277 };
278 };
279
280 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
281 compatible = "ti,sysc-omap4", "ti,sysc";
282 reg = <0x10000 0x4>;
283 reg-names = "rev";
284 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_CONTROL_CLKCTRL 0>;
285 clock-names = "fck";
286 ti,no-idle;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges = <0x00000000 0x00010000 0x00010000>,
290 <0x00010000 0x00020000 0x00010000>;
291
292 scm: scm@0 {
293 compatible = "ti,am3-scm", "simple-bus";
294 reg = <0x0 0x2000>;
295 #address-cells = <1>;
296 #size-cells = <1>;
297 #pinctrl-cells = <1>;
298 ranges = <0 0 0x2000>;
299
300 am33xx_pinmux: pinmux@800 {
301 compatible = "pinctrl-single";
302 reg = <0x800 0x238>;
303 #pinctrl-cells = <2>;
304 pinctrl-single,register-width = <32>;
305 pinctrl-single,function-mask = <0x7f>;
306 };
307
308 scm_conf: scm_conf@0 {
309 compatible = "syscon", "simple-bus";
310 reg = <0x0 0x800>;
311 #address-cells = <1>;
312 #size-cells = <1>;
313 ranges = <0 0 0x800>;
314
315 phy_gmii_sel: phy-gmii-sel {
316 compatible = "ti,am3352-phy-gmii-sel";
317 reg = <0x650 0x4>;
318 #phy-cells = <2>;
319 };
320
321 scm_clocks: clocks {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 };
325 };
326
327 usb_ctrl_mod: control@620 {
328 compatible = "ti,am335x-usb-ctrl-module";
329 reg = <0x620 0x10>,
330 <0x648 0x4>;
331 reg-names = "phy_ctrl", "wakeup";
332 };
333
334 wkup_m3_ipc: wkup_m3_ipc@1324 {
335 compatible = "ti,am3352-wkup-m3-ipc";
336 reg = <0x1324 0x24>;
337 interrupts = <78>;
338 ti,rproc = <&wkup_m3>;
339 mboxes = <&mailbox &mbox_wkupm3>;
340 };
341
342 edma_xbar: dma-router@f90 {
343 compatible = "ti,am335x-edma-crossbar";
344 reg = <0xf90 0x40>;
345 #dma-cells = <3>;
346 dma-requests = <32>;
347 dma-masters = <&edma>;
348 };
349
350 scm_clockdomains: clockdomains {
351 };
352 };
353 };
354
355 timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
356 compatible = "ti,sysc-omap2-timer", "ti,sysc";
357 reg = <0x31000 0x4>,
358 <0x31010 0x4>,
359 <0x31014 0x4>;
360 reg-names = "rev", "sysc", "syss";
361 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
362 SYSC_OMAP2_SOFTRESET |
363 SYSC_OMAP2_AUTOIDLE)>;
364 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
365 <SYSC_IDLE_NO>,
366 <SYSC_IDLE_SMART>;
367 ti,syss-mask = <1>;
368 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
369 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
370 clock-names = "fck";
371 #address-cells = <1>;
372 #size-cells = <1>;
373 ranges = <0x0 0x31000 0x1000>;
374
375 timer1: timer@0 {
376 compatible = "ti,am335x-timer-1ms";
377 reg = <0x0 0x400>;
378 interrupts = <67>;
379 ti,timer-alwon;
380 clocks = <&timer1_fck>;
381 clock-names = "fck";
382 };
383 };
384
385 target-module@33000 { /* 0x44e33000, ap 27 18.0 */
386 compatible = "ti,sysc";
387 status = "disabled";
388 #address-cells = <1>;
389 #size-cells = <1>;
390 ranges = <0x0 0x33000 0x1000>;
391 };
392
393 target-module@35000 { /* 0x44e35000, ap 29 50.0 */
394 compatible = "ti,sysc-omap2", "ti,sysc";
395 reg = <0x35000 0x4>,
396 <0x35010 0x4>,
397 <0x35014 0x4>;
398 reg-names = "rev", "sysc", "syss";
399 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
400 SYSC_OMAP2_SOFTRESET)>;
401 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
402 <SYSC_IDLE_NO>,
403 <SYSC_IDLE_SMART>,
404 <SYSC_IDLE_SMART_WKUP>;
405 ti,syss-mask = <1>;
406 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
407 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
408 clock-names = "fck";
409 #address-cells = <1>;
410 #size-cells = <1>;
411 ranges = <0x0 0x35000 0x1000>;
412
413 wdt2: wdt@0 {
414 compatible = "ti,omap3-wdt";
415 reg = <0x0 0x1000>;
416 interrupts = <91>;
417 };
418 };
419
420 target-module@37000 { /* 0x44e37000, ap 31 08.0 */
421 compatible = "ti,sysc";
422 status = "disabled";
423 #address-cells = <1>;
424 #size-cells = <1>;
425 ranges = <0x0 0x37000 0x1000>;
426 };
427
428 target-module@39000 { /* 0x44e39000, ap 33 02.0 */
429 compatible = "ti,sysc";
430 status = "disabled";
431 #address-cells = <1>;
432 #size-cells = <1>;
433 ranges = <0x0 0x39000 0x1000>;
434 };
435
436 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
437 compatible = "ti,sysc-omap4-simple", "ti,sysc";
438 reg = <0x3e074 0x4>,
439 <0x3e078 0x4>;
440 reg-names = "rev", "sysc";
441 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
442 <SYSC_IDLE_NO>,
443 <SYSC_IDLE_SMART>,
444 <SYSC_IDLE_SMART_WKUP>;
445 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
446 power-domains = <&prm_rtc>;
447 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
448 clock-names = "fck";
449 #address-cells = <1>;
450 #size-cells = <1>;
451 ranges = <0x0 0x3e000 0x1000>;
452
453 rtc: rtc@0 {
454 compatible = "ti,am3352-rtc", "ti,da830-rtc";
455 reg = <0x0 0x1000>;
456 interrupts = <75
457 76>;
458 };
459 };
460
461 target-module@40000 { /* 0x44e40000, ap 38 68.0 */
462 compatible = "ti,sysc";
463 status = "disabled";
464 #address-cells = <1>;
465 #size-cells = <1>;
466 ranges = <0x0 0x40000 0x40000>;
467 };
468 };
469};
470
471&l4_fw { /* 0x47c00000 */
472 compatible = "ti,am33xx-l4-fw", "simple-bus";
473 reg = <0x47c00000 0x800>,
474 <0x47c00800 0x800>,
475 <0x47c01000 0x400>;
476 reg-names = "ap", "la", "ia0";
477 #address-cells = <1>;
478 #size-cells = <1>;
479 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */
480
481 segment@0 { /* 0x47c00000 */
482 compatible = "simple-bus";
483 #address-cells = <1>;
484 #size-cells = <1>;
485 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
486 <0x00000800 0x00000800 0x000800>, /* ap 1 */
487 <0x00001000 0x00001000 0x000400>, /* ap 2 */
488 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */
489 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */
490 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */
491 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */
492 <0x00010000 0x00010000 0x001000>, /* ap 7 */
493 <0x00011000 0x00011000 0x001000>, /* ap 8 */
494 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */
495 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */
496 <0x00024000 0x00024000 0x001000>, /* ap 11 */
497 <0x00025000 0x00025000 0x001000>, /* ap 12 */
498 <0x00026000 0x00026000 0x001000>, /* ap 13 */
499 <0x00027000 0x00027000 0x001000>, /* ap 14 */
500 <0x00030000 0x00030000 0x001000>, /* ap 15 */
501 <0x00031000 0x00031000 0x001000>, /* ap 16 */
502 <0x00038000 0x00038000 0x001000>, /* ap 17 */
503 <0x00039000 0x00039000 0x001000>, /* ap 18 */
504 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */
505 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */
506 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
507 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */
508 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
509 <0x00040000 0x00040000 0x001000>, /* ap 24 */
510 <0x00046000 0x00046000 0x001000>, /* ap 25 */
511 <0x00047000 0x00047000 0x001000>, /* ap 26 */
512 <0x00044000 0x00044000 0x001000>, /* ap 27 */
513 <0x00045000 0x00045000 0x001000>, /* ap 28 */
514 <0x00028000 0x00028000 0x001000>, /* ap 29 */
515 <0x00029000 0x00029000 0x001000>, /* ap 30 */
516 <0x00032000 0x00032000 0x001000>, /* ap 31 */
517 <0x00033000 0x00033000 0x001000>, /* ap 32 */
518 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */
519 <0x00041000 0x00041000 0x001000>, /* ap 34 */
520 <0x00042000 0x00042000 0x001000>, /* ap 35 */
521 <0x00043000 0x00043000 0x001000>, /* ap 36 */
522 <0x00014000 0x00014000 0x001000>, /* ap 37 */
523 <0x00015000 0x00015000 0x001000>; /* ap 38 */
524
525 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */
526 compatible = "ti,sysc";
527 status = "disabled";
528 #address-cells = <1>;
529 #size-cells = <1>;
530 ranges = <0x0 0xc000 0x1000>;
531 };
532
533 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */
534 compatible = "ti,sysc";
535 status = "disabled";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 ranges = <0x0 0xe000 0x1000>;
539 };
540
541 target-module@10000 { /* 0x47c10000, ap 7 20.0 */
542 compatible = "ti,sysc";
543 status = "disabled";
544 #address-cells = <1>;
545 #size-cells = <1>;
546 ranges = <0x0 0x10000 0x1000>;
547 };
548
549 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */
550 compatible = "ti,sysc";
551 status = "disabled";
552 #address-cells = <1>;
553 #size-cells = <1>;
554 ranges = <0x0 0x14000 0x1000>;
555 };
556
557 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */
558 compatible = "ti,sysc";
559 status = "disabled";
560 #address-cells = <1>;
561 #size-cells = <1>;
562 ranges = <0x0 0x1a000 0x1000>;
563 };
564
565 target-module@24000 { /* 0x47c24000, ap 11 28.0 */
566 compatible = "ti,sysc";
567 status = "disabled";
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges = <0x0 0x24000 0x1000>;
571 };
572
573 target-module@26000 { /* 0x47c26000, ap 13 30.0 */
574 compatible = "ti,sysc";
575 status = "disabled";
576 #address-cells = <1>;
577 #size-cells = <1>;
578 ranges = <0x0 0x26000 0x1000>;
579 };
580
581 target-module@28000 { /* 0x47c28000, ap 29 40.0 */
582 compatible = "ti,sysc";
583 status = "disabled";
584 #address-cells = <1>;
585 #size-cells = <1>;
586 ranges = <0x0 0x28000 0x1000>;
587 };
588
589 target-module@30000 { /* 0x47c30000, ap 15 14.0 */
590 compatible = "ti,sysc";
591 status = "disabled";
592 #address-cells = <1>;
593 #size-cells = <1>;
594 ranges = <0x0 0x30000 0x1000>;
595 };
596
597 target-module@32000 { /* 0x47c32000, ap 31 06.0 */
598 compatible = "ti,sysc";
599 status = "disabled";
600 #address-cells = <1>;
601 #size-cells = <1>;
602 ranges = <0x0 0x32000 0x1000>;
603 };
604
605 target-module@38000 { /* 0x47c38000, ap 17 18.0 */
606 compatible = "ti,sysc";
607 status = "disabled";
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges = <0x0 0x38000 0x1000>;
611 };
612
613 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */
614 compatible = "ti,sysc";
615 status = "disabled";
616 #address-cells = <1>;
617 #size-cells = <1>;
618 ranges = <0x0 0x3a000 0x1000>;
619 };
620
621 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */
622 compatible = "ti,sysc";
623 status = "disabled";
624 #address-cells = <1>;
625 #size-cells = <1>;
626 ranges = <0x0 0x3c000 0x1000>;
627 };
628
629 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */
630 compatible = "ti,sysc";
631 status = "disabled";
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges = <0x0 0x3e000 0x1000>;
635 };
636
637 target-module@40000 { /* 0x47c40000, ap 24 02.0 */
638 compatible = "ti,sysc";
639 status = "disabled";
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0x0 0x40000 0x1000>;
643 };
644
645 target-module@42000 { /* 0x47c42000, ap 35 34.0 */
646 compatible = "ti,sysc";
647 status = "disabled";
648 #address-cells = <1>;
649 #size-cells = <1>;
650 ranges = <0x0 0x42000 0x1000>;
651 };
652
653 target-module@44000 { /* 0x47c44000, ap 27 24.0 */
654 compatible = "ti,sysc";
655 status = "disabled";
656 #address-cells = <1>;
657 #size-cells = <1>;
658 ranges = <0x0 0x44000 0x1000>;
659 };
660
661 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
662 compatible = "ti,sysc";
663 status = "disabled";
664 #address-cells = <1>;
665 #size-cells = <1>;
666 ranges = <0x0 0x46000 0x1000>;
667 };
668 };
669};
670
671&l4_fast { /* 0x4a000000 */
672 compatible = "ti,am33xx-l4-fast", "simple-pm-bus";
673 power-domains = <&prm_per>;
674 clocks = <&l4hs_clkctrl AM3_L4HS_L4_HS_CLKCTRL 0>;
675 clock-names = "fck";
676 reg = <0x4a000000 0x800>,
677 <0x4a000800 0x800>,
678 <0x4a001000 0x400>;
679 reg-names = "ap", "la", "ia0";
680 #address-cells = <1>;
681 #size-cells = <1>;
682 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
683
684 segment@0 { /* 0x4a000000 */
685 compatible = "simple-pm-bus";
686 #address-cells = <1>;
687 #size-cells = <1>;
688 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
689 <0x00000800 0x00000800 0x000800>, /* ap 1 */
690 <0x00001000 0x00001000 0x000400>, /* ap 2 */
691 <0x00100000 0x00100000 0x008000>, /* ap 3 */
692 <0x00108000 0x00108000 0x001000>, /* ap 4 */
693 <0x00180000 0x00180000 0x020000>, /* ap 5 */
694 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */
695 <0x00200000 0x00200000 0x080000>, /* ap 7 */
696 <0x00280000 0x00280000 0x001000>, /* ap 8 */
697 <0x00300000 0x00300000 0x080000>, /* ap 9 */
698 <0x00380000 0x00380000 0x001000>; /* ap 10 */
699
700 target-module@100000 { /* 0x4a100000, ap 3 08.0 */
701 compatible = "ti,sysc-omap4-simple", "ti,sysc";
702 reg = <0x101200 0x4>,
703 <0x101208 0x4>,
704 <0x101204 0x4>;
705 reg-names = "rev", "sysc", "syss";
706 ti,sysc-mask = <0>;
707 ti,sysc-midle = <SYSC_IDLE_FORCE>,
708 <SYSC_IDLE_NO>;
709 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
710 <SYSC_IDLE_NO>;
711 ti,syss-mask = <1>;
712 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
713 clock-names = "fck";
714 #address-cells = <1>;
715 #size-cells = <1>;
716 ranges = <0x0 0x100000 0x8000>;
717
718 mac: ethernet@0 {
719 compatible = "ti,am335x-cpsw","ti,cpsw";
720 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
721 clock-names = "fck", "cpts";
722 cpdma_channels = <8>;
723 ale_entries = <1024>;
724 bd_ram_size = <0x2000>;
725 mac_control = <0x20>;
726 slaves = <2>;
727 active_slave = <0>;
728 cpts_clock_mult = <0x80000000>;
729 cpts_clock_shift = <29>;
730 reg = <0x0 0x800
731 0x1200 0x100>;
732 #address-cells = <1>;
733 #size-cells = <1>;
734 /*
735 * c0_rx_thresh_pend
736 * c0_rx_pend
737 * c0_tx_pend
738 * c0_misc_pend
739 */
740 interrupts = <40 41 42 43>;
741 ranges = <0 0 0x8000>;
742 syscon = <&scm_conf>;
743 status = "disabled";
744
745 davinci_mdio: mdio@1000 {
746 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
747 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
748 clock-names = "fck";
749 #address-cells = <1>;
750 #size-cells = <0>;
751 bus_freq = <1000000>;
752 reg = <0x1000 0x100>;
753 status = "disabled";
754 };
755
756 cpsw_emac0: slave@200 {
757 /* Filled in by U-Boot */
758 mac-address = [ 00 00 00 00 00 00 ];
759 phys = <&phy_gmii_sel 1 1>;
760 };
761
762 cpsw_emac1: slave@300 {
763 /* Filled in by U-Boot */
764 mac-address = [ 00 00 00 00 00 00 ];
765 phys = <&phy_gmii_sel 2 1>;
766 };
767 };
768 };
769
770 target-module@180000 { /* 0x4a180000, ap 5 10.0 */
771 compatible = "ti,sysc";
772 status = "disabled";
773 #address-cells = <1>;
774 #size-cells = <1>;
775 ranges = <0x0 0x180000 0x20000>;
776 };
777
778 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
779 compatible = "ti,sysc";
780 status = "disabled";
781 #address-cells = <1>;
782 #size-cells = <1>;
783 ranges = <0x0 0x200000 0x80000>;
784 };
785
786 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
787 compatible = "ti,sysc-pruss", "ti,sysc";
788 reg = <0x326000 0x4>,
789 <0x326004 0x4>;
790 reg-names = "rev", "sysc";
791 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
792 SYSC_PRUSS_SUB_MWAIT)>;
793 ti,sysc-midle = <SYSC_IDLE_FORCE>,
794 <SYSC_IDLE_NO>,
795 <SYSC_IDLE_SMART>;
796 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
797 <SYSC_IDLE_NO>,
798 <SYSC_IDLE_SMART>;
799 clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
800 clock-names = "fck";
801 resets = <&prm_per 1>;
802 reset-names = "rstctrl";
803 #address-cells = <1>;
804 #size-cells = <1>;
805 ranges = <0x0 0x300000 0x80000>;
806 status = "disabled";
807 };
808 };
809};
810
811&l4_mpuss { /* 0x4b140000 */
812 compatible = "ti,am33xx-l4-mpuss", "simple-bus";
813 reg = <0x4b144400 0x100>,
814 <0x4b144800 0x400>;
815 reg-names = "la", "ap";
816 #address-cells = <1>;
817 #size-cells = <1>;
818 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */
819
820 segment@0 { /* 0x4b140000 */
821 compatible = "simple-bus";
822 #address-cells = <1>;
823 #size-cells = <1>;
824 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
825 <0x00001000 0x00001000 0x001000>, /* ap 1 */
826 <0x00002000 0x00002000 0x001000>, /* ap 2 */
827 <0x00004000 0x00004000 0x000400>, /* ap 3 */
828 <0x00005000 0x00005000 0x000400>, /* ap 4 */
829 <0x00000000 0x00000000 0x001000>, /* ap 5 */
830 <0x00003000 0x00003000 0x001000>, /* ap 6 */
831 <0x00000800 0x00000800 0x000800>; /* ap 7 */
832
833 target-module@0 { /* 0x4b140000, ap 5 02.2 */
834 compatible = "ti,sysc";
835 status = "disabled";
836 #address-cells = <1>;
837 #size-cells = <1>;
838 ranges = <0x00000000 0x00000000 0x00001000>,
839 <0x00001000 0x00001000 0x00001000>,
840 <0x00002000 0x00002000 0x00001000>;
841 };
842
843 target-module@3000 { /* 0x4b143000, ap 6 04.0 */
844 compatible = "ti,sysc";
845 status = "disabled";
846 #address-cells = <1>;
847 #size-cells = <1>;
848 ranges = <0x0 0x3000 0x1000>;
849 };
850 };
851};
852
853&l4_per { /* 0x48000000 */
854 compatible = "ti,am33xx-l4-per", "simple-pm-bus";
855 power-domains = <&prm_per>;
856 clocks = <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
857 clock-names = "fck";
858 reg = <0x48000000 0x800>,
859 <0x48000800 0x800>,
860 <0x48001000 0x400>,
861 <0x48001400 0x400>,
862 <0x48001800 0x400>,
863 <0x48001c00 0x400>;
864 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
865 #address-cells = <1>;
866 #size-cells = <1>;
867 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
868 <0x00100000 0x48100000 0x100000>, /* segment 1 */
869 <0x00200000 0x48200000 0x100000>, /* segment 2 */
870 <0x00300000 0x48300000 0x100000>, /* segment 3 */
871 <0x46000000 0x46000000 0x400000>, /* l3 data port */
872 <0x46400000 0x46400000 0x400000>; /* l3 data port */
873
874 segment@0 { /* 0x48000000 */
875 compatible = "simple-pm-bus";
876 #address-cells = <1>;
877 #size-cells = <1>;
878 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
879 <0x00000800 0x00000800 0x000800>, /* ap 1 */
880 <0x00001000 0x00001000 0x000400>, /* ap 2 */
881 <0x00001400 0x00001400 0x000400>, /* ap 3 */
882 <0x00001800 0x00001800 0x000400>, /* ap 4 */
883 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
884 <0x00008000 0x00008000 0x001000>, /* ap 6 */
885 <0x00009000 0x00009000 0x001000>, /* ap 7 */
886 <0x00016000 0x00016000 0x001000>, /* ap 8 */
887 <0x00017000 0x00017000 0x001000>, /* ap 9 */
888 <0x00022000 0x00022000 0x001000>, /* ap 10 */
889 <0x00023000 0x00023000 0x001000>, /* ap 11 */
890 <0x00024000 0x00024000 0x001000>, /* ap 12 */
891 <0x00025000 0x00025000 0x001000>, /* ap 13 */
892 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */
893 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */
894 <0x00038000 0x00038000 0x002000>, /* ap 16 */
895 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */
896 <0x00014000 0x00014000 0x001000>, /* ap 18 */
897 <0x00015000 0x00015000 0x001000>, /* ap 19 */
898 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */
899 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
900 <0x00040000 0x00040000 0x001000>, /* ap 22 */
901 <0x00041000 0x00041000 0x001000>, /* ap 23 */
902 <0x00042000 0x00042000 0x001000>, /* ap 24 */
903 <0x00043000 0x00043000 0x001000>, /* ap 25 */
904 <0x00044000 0x00044000 0x001000>, /* ap 26 */
905 <0x00045000 0x00045000 0x001000>, /* ap 27 */
906 <0x00046000 0x00046000 0x001000>, /* ap 28 */
907 <0x00047000 0x00047000 0x001000>, /* ap 29 */
908 <0x00048000 0x00048000 0x001000>, /* ap 30 */
909 <0x00049000 0x00049000 0x001000>, /* ap 31 */
910 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */
911 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */
912 <0x00050000 0x00050000 0x002000>, /* ap 34 */
913 <0x00052000 0x00052000 0x001000>, /* ap 35 */
914 <0x00060000 0x00060000 0x001000>, /* ap 36 */
915 <0x00061000 0x00061000 0x001000>, /* ap 37 */
916 <0x00080000 0x00080000 0x010000>, /* ap 38 */
917 <0x00090000 0x00090000 0x001000>, /* ap 39 */
918 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */
919 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */
920 <0x00030000 0x00030000 0x001000>, /* ap 77 */
921 <0x00031000 0x00031000 0x001000>, /* ap 78 */
922 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */
923 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */
924 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */
925 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */
926 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */
927 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */
928 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */
929 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */
930 <0x46000000 0x46000000 0x400000>, /* l3 data port */
931 <0x46400000 0x46400000 0x400000>; /* l3 data port */
932
933 target-module@8000 { /* 0x48008000, ap 6 10.0 */
934 compatible = "ti,sysc";
935 status = "disabled";
936 #address-cells = <1>;
937 #size-cells = <1>;
938 ranges = <0x0 0x8000 0x1000>;
939 };
940
941 target-module@14000 { /* 0x48014000, ap 18 58.0 */
942 compatible = "ti,sysc";
943 status = "disabled";
944 #address-cells = <1>;
945 #size-cells = <1>;
946 ranges = <0x0 0x14000 0x1000>;
947 };
948
949 target-module@16000 { /* 0x48016000, ap 8 3c.0 */
950 compatible = "ti,sysc";
951 status = "disabled";
952 #address-cells = <1>;
953 #size-cells = <1>;
954 ranges = <0x0 0x16000 0x1000>;
955 };
956
957 target-module@22000 { /* 0x48022000, ap 10 12.0 */
958 compatible = "ti,sysc-omap2", "ti,sysc";
959 reg = <0x22050 0x4>,
960 <0x22054 0x4>,
961 <0x22058 0x4>;
962 reg-names = "rev", "sysc", "syss";
963 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
964 SYSC_OMAP2_SOFTRESET |
965 SYSC_OMAP2_AUTOIDLE)>;
966 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
967 <SYSC_IDLE_NO>,
968 <SYSC_IDLE_SMART>,
969 <SYSC_IDLE_SMART_WKUP>;
970 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
971 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
972 clock-names = "fck";
973 #address-cells = <1>;
974 #size-cells = <1>;
975 ranges = <0x0 0x22000 0x1000>;
976
977 uart1: serial@0 {
978 compatible = "ti,am3352-uart", "ti,omap3-uart";
979 clock-frequency = <48000000>;
980 reg = <0x0 0x1000>;
981 interrupts = <73>;
982 status = "disabled";
983 dmas = <&edma 28 0>, <&edma 29 0>;
984 dma-names = "tx", "rx";
985 };
986 };
987
988 target-module@24000 { /* 0x48024000, ap 12 14.0 */
989 compatible = "ti,sysc-omap2", "ti,sysc";
990 reg = <0x24050 0x4>,
991 <0x24054 0x4>,
992 <0x24058 0x4>;
993 reg-names = "rev", "sysc", "syss";
994 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
995 SYSC_OMAP2_SOFTRESET |
996 SYSC_OMAP2_AUTOIDLE)>;
997 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
998 <SYSC_IDLE_NO>,
999 <SYSC_IDLE_SMART>,
1000 <SYSC_IDLE_SMART_WKUP>;
1001 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1002 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
1003 clock-names = "fck";
1004 #address-cells = <1>;
1005 #size-cells = <1>;
1006 ranges = <0x0 0x24000 0x1000>;
1007
1008 uart2: serial@0 {
1009 compatible = "ti,am3352-uart", "ti,omap3-uart";
1010 clock-frequency = <48000000>;
1011 reg = <0x0 0x1000>;
1012 interrupts = <74>;
1013 status = "disabled";
1014 dmas = <&edma 30 0>, <&edma 31 0>;
1015 dma-names = "tx", "rx";
1016 };
1017 };
1018
1019 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
1020 compatible = "ti,sysc-omap2", "ti,sysc";
1021 reg = <0x2a000 0x8>,
1022 <0x2a010 0x8>,
1023 <0x2a090 0x8>;
1024 reg-names = "rev", "sysc", "syss";
1025 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1026 SYSC_OMAP2_ENAWAKEUP |
1027 SYSC_OMAP2_SOFTRESET |
1028 SYSC_OMAP2_AUTOIDLE)>;
1029 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1030 <SYSC_IDLE_NO>,
1031 <SYSC_IDLE_SMART>,
1032 <SYSC_IDLE_SMART_WKUP>;
1033 ti,syss-mask = <1>;
1034 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1035 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
1036 clock-names = "fck";
1037 #address-cells = <1>;
1038 #size-cells = <1>;
1039 ranges = <0x0 0x2a000 0x1000>;
1040
1041 i2c1: i2c@0 {
1042 compatible = "ti,omap4-i2c";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 reg = <0x0 0x1000>;
1046 interrupts = <71>;
1047 status = "disabled";
1048 };
1049 };
1050
1051 target-module@30000 { /* 0x48030000, ap 77 08.0 */
1052 compatible = "ti,sysc-omap2", "ti,sysc";
1053 reg = <0x30000 0x4>,
1054 <0x30110 0x4>,
1055 <0x30114 0x4>;
1056 reg-names = "rev", "sysc", "syss";
1057 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1058 SYSC_OMAP2_SOFTRESET |
1059 SYSC_OMAP2_AUTOIDLE)>;
1060 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1061 <SYSC_IDLE_NO>,
1062 <SYSC_IDLE_SMART>;
1063 ti,syss-mask = <1>;
1064 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1065 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
1066 clock-names = "fck";
1067 #address-cells = <1>;
1068 #size-cells = <1>;
1069 ranges = <0x0 0x30000 0x1000>;
1070
1071 spi0: spi@0 {
1072 compatible = "ti,omap4-mcspi";
1073 #address-cells = <1>;
1074 #size-cells = <0>;
1075 reg = <0x0 0x400>;
1076 interrupts = <65>;
1077 ti,spi-num-cs = <2>;
1078 dmas = <&edma 16 0
1079 &edma 17 0
1080 &edma 18 0
1081 &edma 19 0>;
1082 dma-names = "tx0", "rx0", "tx1", "rx1";
1083 status = "disabled";
1084 };
1085 };
1086
1087 target-module@38000 { /* 0x48038000, ap 16 02.0 */
1088 compatible = "ti,sysc-omap4-simple", "ti,sysc";
1089 reg = <0x38000 0x4>,
1090 <0x38004 0x4>;
1091 reg-names = "rev", "sysc";
1092 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1093 <SYSC_IDLE_NO>,
1094 <SYSC_IDLE_SMART>;
1095 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1096 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
1097 clock-names = "fck";
1098 #address-cells = <1>;
1099 #size-cells = <1>;
1100 ranges = <0x0 0x38000 0x2000>,
1101 <0x46000000 0x46000000 0x400000>;
1102
1103 mcasp0: mcasp@0 {
1104 compatible = "ti,am33xx-mcasp-audio";
1105 reg = <0x0 0x2000>,
1106 <0x46000000 0x400000>;
1107 reg-names = "mpu", "dat";
1108 interrupts = <80>, <81>;
1109 interrupt-names = "tx", "rx";
1110 status = "disabled";
1111 dmas = <&edma 8 2>,
1112 <&edma 9 2>;
1113 dma-names = "tx", "rx";
1114 };
1115 };
1116
1117 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
1118 compatible = "ti,sysc-omap4-simple", "ti,sysc";
1119 reg = <0x3c000 0x4>,
1120 <0x3c004 0x4>;
1121 reg-names = "rev", "sysc";
1122 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1123 <SYSC_IDLE_NO>,
1124 <SYSC_IDLE_SMART>;
1125 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1126 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
1127 clock-names = "fck";
1128 #address-cells = <1>;
1129 #size-cells = <1>;
1130 ranges = <0x0 0x3c000 0x2000>,
1131 <0x46400000 0x46400000 0x400000>;
1132
1133 mcasp1: mcasp@0 {
1134 compatible = "ti,am33xx-mcasp-audio";
1135 reg = <0x0 0x2000>,
1136 <0x46400000 0x400000>;
1137 reg-names = "mpu", "dat";
1138 interrupts = <82>, <83>;
1139 interrupt-names = "tx", "rx";
1140 status = "disabled";
1141 dmas = <&edma 10 2>,
1142 <&edma 11 2>;
1143 dma-names = "tx", "rx";
1144 };
1145 };
1146
1147 timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
1148 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1149 reg = <0x40000 0x4>,
1150 <0x40010 0x4>,
1151 <0x40014 0x4>;
1152 reg-names = "rev", "sysc", "syss";
1153 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1154 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1155 <SYSC_IDLE_NO>,
1156 <SYSC_IDLE_SMART>,
1157 <SYSC_IDLE_SMART_WKUP>;
1158 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1159 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
1160 clock-names = "fck";
1161 #address-cells = <1>;
1162 #size-cells = <1>;
1163 ranges = <0x0 0x40000 0x1000>;
1164
1165 timer2: timer@0 {
1166 compatible = "ti,am335x-timer";
1167 reg = <0x0 0x400>;
1168 interrupts = <68>;
1169 clocks = <&timer2_fck>;
1170 clock-names = "fck";
1171 };
1172 };
1173
1174 target-module@42000 { /* 0x48042000, ap 24 1c.0 */
1175 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1176 reg = <0x42000 0x4>,
1177 <0x42010 0x4>,
1178 <0x42014 0x4>;
1179 reg-names = "rev", "sysc", "syss";
1180 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1181 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1182 <SYSC_IDLE_NO>,
1183 <SYSC_IDLE_SMART>,
1184 <SYSC_IDLE_SMART_WKUP>;
1185 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1186 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
1187 clock-names = "fck";
1188 #address-cells = <1>;
1189 #size-cells = <1>;
1190 ranges = <0x0 0x42000 0x1000>;
1191
1192 timer3: timer@0 {
1193 compatible = "ti,am335x-timer";
1194 reg = <0x0 0x400>;
1195 interrupts = <69>;
1196 };
1197 };
1198
1199 target-module@44000 { /* 0x48044000, ap 26 26.0 */
1200 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1201 reg = <0x44000 0x4>,
1202 <0x44010 0x4>,
1203 <0x44014 0x4>;
1204 reg-names = "rev", "sysc", "syss";
1205 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1206 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1207 <SYSC_IDLE_NO>,
1208 <SYSC_IDLE_SMART>,
1209 <SYSC_IDLE_SMART_WKUP>;
1210 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1211 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
1212 clock-names = "fck";
1213 #address-cells = <1>;
1214 #size-cells = <1>;
1215 ranges = <0x0 0x44000 0x1000>;
1216
1217 timer4: timer@0 {
1218 compatible = "ti,am335x-timer";
1219 reg = <0x0 0x400>;
1220 interrupts = <92>;
1221 ti,timer-pwm;
1222 };
1223 };
1224
1225 target-module@46000 { /* 0x48046000, ap 28 28.0 */
1226 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1227 reg = <0x46000 0x4>,
1228 <0x46010 0x4>,
1229 <0x46014 0x4>;
1230 reg-names = "rev", "sysc", "syss";
1231 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1232 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1233 <SYSC_IDLE_NO>,
1234 <SYSC_IDLE_SMART>,
1235 <SYSC_IDLE_SMART_WKUP>;
1236 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1237 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
1238 clock-names = "fck";
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241 ranges = <0x0 0x46000 0x1000>;
1242
1243 timer5: timer@0 {
1244 compatible = "ti,am335x-timer";
1245 reg = <0x0 0x400>;
1246 interrupts = <93>;
1247 ti,timer-pwm;
1248 };
1249 };
1250
1251 target-module@48000 { /* 0x48048000, ap 30 22.0 */
1252 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1253 reg = <0x48000 0x4>,
1254 <0x48010 0x4>,
1255 <0x48014 0x4>;
1256 reg-names = "rev", "sysc", "syss";
1257 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1258 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1259 <SYSC_IDLE_NO>,
1260 <SYSC_IDLE_SMART>,
1261 <SYSC_IDLE_SMART_WKUP>;
1262 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1263 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
1264 clock-names = "fck";
1265 #address-cells = <1>;
1266 #size-cells = <1>;
1267 ranges = <0x0 0x48000 0x1000>;
1268
1269 timer6: timer@0 {
1270 compatible = "ti,am335x-timer";
1271 reg = <0x0 0x400>;
1272 interrupts = <94>;
1273 ti,timer-pwm;
1274 };
1275 };
1276
1277 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
1278 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1279 reg = <0x4a000 0x4>,
1280 <0x4a010 0x4>,
1281 <0x4a014 0x4>;
1282 reg-names = "rev", "sysc", "syss";
1283 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1285 <SYSC_IDLE_NO>,
1286 <SYSC_IDLE_SMART>,
1287 <SYSC_IDLE_SMART_WKUP>;
1288 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1289 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
1290 clock-names = "fck";
1291 #address-cells = <1>;
1292 #size-cells = <1>;
1293 ranges = <0x0 0x4a000 0x1000>;
1294
1295 timer7: timer@0 {
1296 compatible = "ti,am335x-timer";
1297 reg = <0x0 0x400>;
1298 interrupts = <95>;
1299 ti,timer-pwm;
1300 };
1301 };
1302
1303 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
1304 compatible = "ti,sysc-omap2", "ti,sysc";
1305 reg = <0x4c000 0x4>,
1306 <0x4c010 0x4>,
1307 <0x4c114 0x4>;
1308 reg-names = "rev", "sysc", "syss";
1309 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1310 SYSC_OMAP2_SOFTRESET |
1311 SYSC_OMAP2_AUTOIDLE)>;
1312 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1313 <SYSC_IDLE_NO>,
1314 <SYSC_IDLE_SMART>,
1315 <SYSC_IDLE_SMART_WKUP>;
1316 ti,syss-mask = <1>;
1317 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1318 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
1319 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
1320 clock-names = "fck", "dbclk";
1321 #address-cells = <1>;
1322 #size-cells = <1>;
1323 ranges = <0x0 0x4c000 0x1000>;
1324
1325 gpio1: gpio@0 {
1326 compatible = "ti,omap4-gpio";
1327 gpio-ranges = <&am33xx_pinmux 0 0 8>,
1328 <&am33xx_pinmux 8 90 4>,
1329 <&am33xx_pinmux 12 12 16>,
1330 <&am33xx_pinmux 28 30 4>;
1331 gpio-controller;
1332 #gpio-cells = <2>;
1333 interrupt-controller;
1334 #interrupt-cells = <2>;
1335 reg = <0x0 0x1000>;
1336 interrupts = <98>;
1337 };
1338 };
1339
1340 target-module@50000 { /* 0x48050000, ap 34 2c.0 */
1341 compatible = "ti,sysc";
1342 status = "disabled";
1343 #address-cells = <1>;
1344 #size-cells = <1>;
1345 ranges = <0x0 0x50000 0x2000>;
1346 };
1347
1348 target-module@60000 { /* 0x48060000, ap 36 0c.0 */
1349 compatible = "ti,sysc-omap2", "ti,sysc";
1350 reg = <0x602fc 0x4>,
1351 <0x60110 0x4>,
1352 <0x60114 0x4>;
1353 reg-names = "rev", "sysc", "syss";
1354 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1355 SYSC_OMAP2_ENAWAKEUP |
1356 SYSC_OMAP2_SOFTRESET |
1357 SYSC_OMAP2_AUTOIDLE)>;
1358 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1359 <SYSC_IDLE_NO>,
1360 <SYSC_IDLE_SMART>;
1361 ti,syss-mask = <1>;
1362 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1363 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
1364 clock-names = "fck";
1365 #address-cells = <1>;
1366 #size-cells = <1>;
1367 ranges = <0x0 0x60000 0x1000>;
1368
1369 mmc1: mmc@0 {
1370 compatible = "ti,am335-sdhci";
1371 ti,needs-special-reset;
1372 dmas = <&edma_xbar 24 0 0
1373 &edma_xbar 25 0 0>;
1374 dma-names = "tx", "rx";
1375 interrupts = <64>;
1376 reg = <0x0 0x1000>;
1377 status = "disabled";
1378 };
1379 };
1380
1381 target-module@80000 { /* 0x48080000, ap 38 18.0 */
1382 compatible = "ti,sysc-omap2", "ti,sysc";
1383 reg = <0x80000 0x4>,
1384 <0x80010 0x4>,
1385 <0x80014 0x4>;
1386 reg-names = "rev", "sysc", "syss";
1387 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1388 SYSC_OMAP2_SOFTRESET |
1389 SYSC_OMAP2_AUTOIDLE)>;
1390 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1391 <SYSC_IDLE_NO>,
1392 <SYSC_IDLE_SMART>;
1393 ti,syss-mask = <1>;
1394 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1395 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
1396 clock-names = "fck";
1397 #address-cells = <1>;
1398 #size-cells = <1>;
1399 ranges = <0x0 0x80000 0x10000>;
1400
1401 elm: elm@0 {
1402 compatible = "ti,am3352-elm";
1403 reg = <0x0 0x2000>;
1404 interrupts = <4>;
1405 status = "disabled";
1406 };
1407 };
1408
1409 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
1410 compatible = "ti,sysc";
1411 status = "disabled";
1412 #address-cells = <1>;
1413 #size-cells = <1>;
1414 ranges = <0x0 0xa0000 0x10000>;
1415 };
1416
1417 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
1418 compatible = "ti,sysc-omap4", "ti,sysc";
1419 reg = <0xc8000 0x4>,
1420 <0xc8010 0x4>;
1421 reg-names = "rev", "sysc";
1422 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1423 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1424 <SYSC_IDLE_NO>,
1425 <SYSC_IDLE_SMART>;
1426 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1427 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
1428 clock-names = "fck";
1429 #address-cells = <1>;
1430 #size-cells = <1>;
1431 ranges = <0x0 0xc8000 0x1000>;
1432
1433 mailbox: mailbox@0 {
1434 compatible = "ti,omap4-mailbox";
1435 reg = <0x0 0x200>;
1436 interrupts = <77>;
1437 #mbox-cells = <1>;
1438 ti,mbox-num-users = <4>;
1439 ti,mbox-num-fifos = <8>;
1440 mbox_wkupm3: wkup_m3 {
1441 ti,mbox-send-noirq;
1442 ti,mbox-tx = <0 0 0>;
1443 ti,mbox-rx = <0 0 3>;
1444 };
1445 };
1446 };
1447
1448 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
1449 compatible = "ti,sysc-omap2", "ti,sysc";
1450 reg = <0xca000 0x4>,
1451 <0xca010 0x4>,
1452 <0xca014 0x4>;
1453 reg-names = "rev", "sysc", "syss";
1454 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1455 SYSC_OMAP2_ENAWAKEUP |
1456 SYSC_OMAP2_SOFTRESET |
1457 SYSC_OMAP2_AUTOIDLE)>;
1458 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1459 <SYSC_IDLE_NO>,
1460 <SYSC_IDLE_SMART>;
1461 ti,syss-mask = <1>;
1462 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1463 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
1464 clock-names = "fck";
1465 #address-cells = <1>;
1466 #size-cells = <1>;
1467 ranges = <0x0 0xca000 0x1000>;
1468
1469 hwspinlock: spinlock@0 {
1470 compatible = "ti,omap4-hwspinlock";
1471 reg = <0x0 0x1000>;
1472 #hwlock-cells = <1>;
1473 };
1474 };
1475
1476 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
1477 compatible = "ti,sysc";
1478 status = "disabled";
1479 #address-cells = <1>;
1480 #size-cells = <1>;
1481 ranges = <0x0 0xcc000 0x1000>;
1482 };
1483 };
1484
1485 segment@100000 { /* 0x48100000 */
1486 compatible = "simple-pm-bus";
1487 #address-cells = <1>;
1488 #size-cells = <1>;
1489 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
1490 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */
1491 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */
1492 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */
1493 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */
1494 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */
1495 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */
1496 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */
1497 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */
1498 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */
1499 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */
1500 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */
1501 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */
1502 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */
1503 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */
1504 <0x000af000 0x001af000 0x001000>, /* ap 57 */
1505 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */
1506 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */
1507 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */
1508 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */
1509 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */
1510 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */
1511 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */
1512 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */
1513 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */
1514 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */
1515 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */
1516 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */
1517 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */
1518 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */
1519
1520 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */
1521 compatible = "ti,sysc";
1522 status = "disabled";
1523 #address-cells = <1>;
1524 #size-cells = <1>;
1525 ranges = <0x0 0x8c000 0x1000>;
1526 };
1527
1528 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
1529 compatible = "ti,sysc";
1530 status = "disabled";
1531 #address-cells = <1>;
1532 #size-cells = <1>;
1533 ranges = <0x0 0x8e000 0x1000>;
1534 };
1535
1536 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
1537 compatible = "ti,sysc-omap2", "ti,sysc";
1538 reg = <0x9c000 0x8>,
1539 <0x9c010 0x8>,
1540 <0x9c090 0x8>;
1541 reg-names = "rev", "sysc", "syss";
1542 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1543 SYSC_OMAP2_ENAWAKEUP |
1544 SYSC_OMAP2_SOFTRESET |
1545 SYSC_OMAP2_AUTOIDLE)>;
1546 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1547 <SYSC_IDLE_NO>,
1548 <SYSC_IDLE_SMART>,
1549 <SYSC_IDLE_SMART_WKUP>;
1550 ti,syss-mask = <1>;
1551 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1552 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
1553 clock-names = "fck";
1554 #address-cells = <1>;
1555 #size-cells = <1>;
1556 ranges = <0x0 0x9c000 0x1000>;
1557
1558 i2c2: i2c@0 {
1559 compatible = "ti,omap4-i2c";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1562 reg = <0x0 0x1000>;
1563 interrupts = <30>;
1564 status = "disabled";
1565 };
1566 };
1567
1568 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
1569 compatible = "ti,sysc-omap2", "ti,sysc";
1570 reg = <0xa0000 0x4>,
1571 <0xa0110 0x4>,
1572 <0xa0114 0x4>;
1573 reg-names = "rev", "sysc", "syss";
1574 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1575 SYSC_OMAP2_SOFTRESET |
1576 SYSC_OMAP2_AUTOIDLE)>;
1577 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1578 <SYSC_IDLE_NO>,
1579 <SYSC_IDLE_SMART>;
1580 ti,syss-mask = <1>;
1581 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1582 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
1583 clock-names = "fck";
1584 #address-cells = <1>;
1585 #size-cells = <1>;
1586 ranges = <0x0 0xa0000 0x1000>;
1587
1588 spi1: spi@0 {
1589 compatible = "ti,omap4-mcspi";
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1592 reg = <0x0 0x400>;
1593 interrupts = <125>;
1594 ti,spi-num-cs = <2>;
1595 dmas = <&edma 42 0
1596 &edma 43 0
1597 &edma 44 0
1598 &edma 45 0>;
1599 dma-names = "tx0", "rx0", "tx1", "rx1";
1600 status = "disabled";
1601 };
1602 };
1603
1604 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */
1605 compatible = "ti,sysc";
1606 status = "disabled";
1607 #address-cells = <1>;
1608 #size-cells = <1>;
1609 ranges = <0x0 0xa2000 0x1000>;
1610 };
1611
1612 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
1613 compatible = "ti,sysc";
1614 status = "disabled";
1615 #address-cells = <1>;
1616 #size-cells = <1>;
1617 ranges = <0x0 0xa4000 0x1000>;
1618 };
1619
1620 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
1621 compatible = "ti,sysc-omap2", "ti,sysc";
1622 reg = <0xa6050 0x4>,
1623 <0xa6054 0x4>,
1624 <0xa6058 0x4>;
1625 reg-names = "rev", "sysc", "syss";
1626 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1627 SYSC_OMAP2_SOFTRESET |
1628 SYSC_OMAP2_AUTOIDLE)>;
1629 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1630 <SYSC_IDLE_NO>,
1631 <SYSC_IDLE_SMART>,
1632 <SYSC_IDLE_SMART_WKUP>;
1633 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1634 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
1635 clock-names = "fck";
1636 #address-cells = <1>;
1637 #size-cells = <1>;
1638 ranges = <0x0 0xa6000 0x1000>;
1639
1640 uart3: serial@0 {
1641 compatible = "ti,am3352-uart", "ti,omap3-uart";
1642 clock-frequency = <48000000>;
1643 reg = <0x0 0x1000>;
1644 interrupts = <44>;
1645 status = "disabled";
1646 };
1647 };
1648
1649 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
1650 compatible = "ti,sysc-omap2", "ti,sysc";
1651 reg = <0xa8050 0x4>,
1652 <0xa8054 0x4>,
1653 <0xa8058 0x4>;
1654 reg-names = "rev", "sysc", "syss";
1655 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1656 SYSC_OMAP2_SOFTRESET |
1657 SYSC_OMAP2_AUTOIDLE)>;
1658 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1659 <SYSC_IDLE_NO>,
1660 <SYSC_IDLE_SMART>,
1661 <SYSC_IDLE_SMART_WKUP>;
1662 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1663 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
1664 clock-names = "fck";
1665 #address-cells = <1>;
1666 #size-cells = <1>;
1667 ranges = <0x0 0xa8000 0x1000>;
1668
1669 uart4: serial@0 {
1670 compatible = "ti,am3352-uart", "ti,omap3-uart";
1671 clock-frequency = <48000000>;
1672 reg = <0x0 0x1000>;
1673 interrupts = <45>;
1674 status = "disabled";
1675 };
1676 };
1677
1678 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
1679 compatible = "ti,sysc-omap2", "ti,sysc";
1680 reg = <0xaa050 0x4>,
1681 <0xaa054 0x4>,
1682 <0xaa058 0x4>;
1683 reg-names = "rev", "sysc", "syss";
1684 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1685 SYSC_OMAP2_SOFTRESET |
1686 SYSC_OMAP2_AUTOIDLE)>;
1687 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1688 <SYSC_IDLE_NO>,
1689 <SYSC_IDLE_SMART>,
1690 <SYSC_IDLE_SMART_WKUP>;
1691 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1692 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
1693 clock-names = "fck";
1694 #address-cells = <1>;
1695 #size-cells = <1>;
1696 ranges = <0x0 0xaa000 0x1000>;
1697
1698 uart5: serial@0 {
1699 compatible = "ti,am3352-uart", "ti,omap3-uart";
1700 clock-frequency = <48000000>;
1701 reg = <0x0 0x1000>;
1702 interrupts = <46>;
1703 status = "disabled";
1704 };
1705 };
1706
1707 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
1708 compatible = "ti,sysc-omap2", "ti,sysc";
1709 reg = <0xac000 0x4>,
1710 <0xac010 0x4>,
1711 <0xac114 0x4>;
1712 reg-names = "rev", "sysc", "syss";
1713 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1714 SYSC_OMAP2_SOFTRESET |
1715 SYSC_OMAP2_AUTOIDLE)>;
1716 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1717 <SYSC_IDLE_NO>,
1718 <SYSC_IDLE_SMART>,
1719 <SYSC_IDLE_SMART_WKUP>;
1720 ti,syss-mask = <1>;
1721 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1722 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
1723 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
1724 clock-names = "fck", "dbclk";
1725 #address-cells = <1>;
1726 #size-cells = <1>;
1727 ranges = <0x0 0xac000 0x1000>;
1728
1729 gpio2: gpio@0 {
1730 compatible = "ti,omap4-gpio";
1731 gpio-ranges = <&am33xx_pinmux 0 34 18>,
1732 <&am33xx_pinmux 18 77 4>,
1733 <&am33xx_pinmux 22 56 10>;
1734 gpio-controller;
1735 #gpio-cells = <2>;
1736 interrupt-controller;
1737 #interrupt-cells = <2>;
1738 reg = <0x0 0x1000>;
1739 interrupts = <32>;
1740 };
1741 };
1742
1743 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
1744 compatible = "ti,sysc-omap2", "ti,sysc";
1745 reg = <0xae000 0x4>,
1746 <0xae010 0x4>,
1747 <0xae114 0x4>;
1748 reg-names = "rev", "sysc", "syss";
1749 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1750 SYSC_OMAP2_SOFTRESET |
1751 SYSC_OMAP2_AUTOIDLE)>;
1752 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1753 <SYSC_IDLE_NO>,
1754 <SYSC_IDLE_SMART>,
1755 <SYSC_IDLE_SMART_WKUP>;
1756 ti,syss-mask = <1>;
1757 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1758 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
1759 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
1760 clock-names = "fck", "dbclk";
1761 #address-cells = <1>;
1762 #size-cells = <1>;
1763 ranges = <0x0 0xae000 0x1000>;
1764
1765 gpio3: gpio@0 {
1766 compatible = "ti,omap4-gpio";
1767 gpio-ranges = <&am33xx_pinmux 0 66 5>,
1768 <&am33xx_pinmux 5 98 2>,
1769 <&am33xx_pinmux 7 75 2>,
1770 <&am33xx_pinmux 13 141 1>,
1771 <&am33xx_pinmux 14 100 8>;
1772 gpio-controller;
1773 #gpio-cells = <2>;
1774 interrupt-controller;
1775 #interrupt-cells = <2>;
1776 reg = <0x0 0x1000>;
1777 interrupts = <62>;
1778 };
1779 };
1780
1781 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
1782 compatible = "ti,sysc";
1783 status = "disabled";
1784 #address-cells = <1>;
1785 #size-cells = <1>;
1786 ranges = <0x0 0xb0000 0x10000>;
1787 };
1788
1789 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
1790 compatible = "ti,sysc-omap4", "ti,sysc";
1791 reg = <0xcc020 0x4>;
1792 reg-names = "rev";
1793 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1794 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
1795 <&dcan0_fck>;
1796 clock-names = "fck", "osc";
1797 #address-cells = <1>;
1798 #size-cells = <1>;
1799 ranges = <0x0 0xcc000 0x2000>;
1800
1801 dcan0: can@0 {
1802 compatible = "ti,am3352-d_can";
1803 reg = <0x0 0x2000>;
1804 clocks = <&dcan0_fck>;
1805 clock-names = "fck";
1806 syscon-raminit = <&scm_conf 0x644 0>;
1807 interrupts = <52>;
1808 status = "disabled";
1809 };
1810 };
1811
1812 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
1813 compatible = "ti,sysc-omap4", "ti,sysc";
1814 reg = <0xd0020 0x4>;
1815 reg-names = "rev";
1816 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1817 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
1818 <&dcan1_fck>;
1819 clock-names = "fck", "osc";
1820 #address-cells = <1>;
1821 #size-cells = <1>;
1822 ranges = <0x0 0xd0000 0x2000>;
1823
1824 dcan1: can@0 {
1825 compatible = "ti,am3352-d_can";
1826 reg = <0x0 0x2000>;
1827 clocks = <&dcan1_fck>;
1828 clock-names = "fck";
1829 syscon-raminit = <&scm_conf 0x644 1>;
1830 interrupts = <55>;
1831 status = "disabled";
1832 };
1833 };
1834
1835 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
1836 compatible = "ti,sysc-omap2", "ti,sysc";
1837 reg = <0xd82fc 0x4>,
1838 <0xd8110 0x4>,
1839 <0xd8114 0x4>;
1840 reg-names = "rev", "sysc", "syss";
1841 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1842 SYSC_OMAP2_ENAWAKEUP |
1843 SYSC_OMAP2_SOFTRESET |
1844 SYSC_OMAP2_AUTOIDLE)>;
1845 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1846 <SYSC_IDLE_NO>,
1847 <SYSC_IDLE_SMART>;
1848 ti,syss-mask = <1>;
1849 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1850 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
1851 clock-names = "fck";
1852 #address-cells = <1>;
1853 #size-cells = <1>;
1854 ranges = <0x0 0xd8000 0x1000>;
1855
1856 mmc2: mmc@0 {
1857 compatible = "ti,am335-sdhci";
1858 ti,needs-special-reset;
1859 dmas = <&edma 2 0
1860 &edma 3 0>;
1861 dma-names = "tx", "rx";
1862 interrupts = <28>;
1863 reg = <0x0 0x1000>;
1864 status = "disabled";
1865 };
1866 };
1867 };
1868
1869 segment@200000 { /* 0x48200000 */
1870 compatible = "simple-pm-bus";
1871 #address-cells = <1>;
1872 #size-cells = <1>;
1873 ranges = <0x00000000 0x00200000 0x010000>;
1874
1875 target-module@0 {
1876 compatible = "ti,sysc-omap4-simple", "ti,sysc";
1877 power-domains = <&prm_mpu>;
1878 clocks = <&mpu_clkctrl AM3_MPU_MPU_CLKCTRL 0>;
1879 clock-names = "fck";
1880 ti,no-idle;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0 0 0x10000>;
1884
1885 mpu@0 {
1886 compatible = "ti,omap3-mpu";
1887 pm-sram = <&pm_sram_code
1888 &pm_sram_data>;
1889 };
1890 };
1891 };
1892
1893 segment@300000 { /* 0x48300000 */
1894 compatible = "simple-pm-bus";
1895 #address-cells = <1>;
1896 #size-cells = <1>;
1897 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
1898 <0x00001000 0x00301000 0x001000>, /* ap 67 */
1899 <0x00002000 0x00302000 0x001000>, /* ap 68 */
1900 <0x00003000 0x00303000 0x001000>, /* ap 69 */
1901 <0x00004000 0x00304000 0x001000>, /* ap 70 */
1902 <0x00005000 0x00305000 0x001000>, /* ap 71 */
1903 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */
1904 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */
1905 <0x00018000 0x00318000 0x004000>, /* ap 74 */
1906 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */
1907 <0x00010000 0x00310000 0x002000>, /* ap 76 */
1908 <0x00012000 0x00312000 0x001000>, /* ap 93 */
1909 <0x00015000 0x00315000 0x001000>, /* ap 94 */
1910 <0x00016000 0x00316000 0x001000>, /* ap 95 */
1911 <0x00017000 0x00317000 0x001000>, /* ap 96 */
1912 <0x00013000 0x00313000 0x001000>, /* ap 97 */
1913 <0x00014000 0x00314000 0x001000>, /* ap 98 */
1914 <0x00020000 0x00320000 0x001000>, /* ap 99 */
1915 <0x00021000 0x00321000 0x001000>, /* ap 100 */
1916 <0x00022000 0x00322000 0x001000>, /* ap 101 */
1917 <0x00023000 0x00323000 0x001000>, /* ap 102 */
1918 <0x00024000 0x00324000 0x001000>, /* ap 103 */
1919 <0x00025000 0x00325000 0x001000>; /* ap 104 */
1920
1921 target-module@0 { /* 0x48300000, ap 66 48.0 */
1922 compatible = "ti,sysc-omap4", "ti,sysc";
1923 reg = <0x0 0x4>,
1924 <0x4 0x4>;
1925 reg-names = "rev", "sysc";
1926 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1927 <SYSC_IDLE_NO>,
1928 <SYSC_IDLE_SMART>,
1929 <SYSC_IDLE_SMART_WKUP>;
1930 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1931 <SYSC_IDLE_NO>,
1932 <SYSC_IDLE_SMART>,
1933 <SYSC_IDLE_SMART_WKUP>;
1934 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1935 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
1936 clock-names = "fck";
1937 #address-cells = <1>;
1938 #size-cells = <1>;
1939 ranges = <0x0 0x0 0x1000>;
1940
1941 epwmss0: epwmss@0 {
1942 compatible = "ti,am33xx-pwmss";
1943 reg = <0x0 0x10>;
1944 #address-cells = <1>;
1945 #size-cells = <1>;
1946 status = "disabled";
1947 ranges = <0 0 0x1000>;
1948
1949 ecap0: ecap@100 {
1950 compatible = "ti,am3352-ecap",
1951 "ti,am33xx-ecap";
1952 #pwm-cells = <3>;
1953 reg = <0x100 0x80>;
1954 clocks = <&l4ls_gclk>;
1955 clock-names = "fck";
1956 interrupts = <31>;
1957 interrupt-names = "ecap0";
1958 status = "disabled";
1959 };
1960
1961 eqep0: counter@180 {
1962 compatible = "ti,am3352-eqep";
1963 reg = <0x180 0x80>;
1964 clocks = <&l4ls_gclk>;
1965 clock-names = "sysclkout";
1966 interrupts = <79>;
1967 status = "disabled";
1968 };
1969
1970 ehrpwm0: pwm@200 {
1971 compatible = "ti,am3352-ehrpwm",
1972 "ti,am33xx-ehrpwm";
1973 #pwm-cells = <3>;
1974 reg = <0x200 0x80>;
1975 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
1976 clock-names = "tbclk", "fck";
1977 status = "disabled";
1978 };
1979 };
1980 };
1981
1982 target-module@2000 { /* 0x48302000, ap 68 52.0 */
1983 compatible = "ti,sysc-omap4", "ti,sysc";
1984 reg = <0x2000 0x4>,
1985 <0x2004 0x4>;
1986 reg-names = "rev", "sysc";
1987 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1988 <SYSC_IDLE_NO>,
1989 <SYSC_IDLE_SMART>,
1990 <SYSC_IDLE_SMART_WKUP>;
1991 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1992 <SYSC_IDLE_NO>,
1993 <SYSC_IDLE_SMART>,
1994 <SYSC_IDLE_SMART_WKUP>;
1995 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1996 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
1997 clock-names = "fck";
1998 #address-cells = <1>;
1999 #size-cells = <1>;
2000 ranges = <0x0 0x2000 0x1000>;
2001
2002 epwmss1: epwmss@0 {
2003 compatible = "ti,am33xx-pwmss";
2004 reg = <0x0 0x10>;
2005 #address-cells = <1>;
2006 #size-cells = <1>;
2007 status = "disabled";
2008 ranges = <0 0 0x1000>;
2009
2010 ecap1: ecap@100 {
2011 compatible = "ti,am3352-ecap",
2012 "ti,am33xx-ecap";
2013 #pwm-cells = <3>;
2014 reg = <0x100 0x80>;
2015 clocks = <&l4ls_gclk>;
2016 clock-names = "fck";
2017 interrupts = <47>;
2018 interrupt-names = "ecap1";
2019 status = "disabled";
2020 };
2021
2022 eqep1: counter@180 {
2023 compatible = "ti,am3352-eqep";
2024 reg = <0x180 0x80>;
2025 clocks = <&l4ls_gclk>;
2026 clock-names = "sysclkout";
2027 interrupts = <88>;
2028 status = "disabled";
2029 };
2030
2031 ehrpwm1: pwm@200 {
2032 compatible = "ti,am3352-ehrpwm",
2033 "ti,am33xx-ehrpwm";
2034 #pwm-cells = <3>;
2035 reg = <0x200 0x80>;
2036 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
2037 clock-names = "tbclk", "fck";
2038 status = "disabled";
2039 };
2040 };
2041 };
2042
2043 target-module@4000 { /* 0x48304000, ap 70 44.0 */
2044 compatible = "ti,sysc-omap4", "ti,sysc";
2045 reg = <0x4000 0x4>,
2046 <0x4004 0x4>;
2047 reg-names = "rev", "sysc";
2048 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2049 <SYSC_IDLE_NO>,
2050 <SYSC_IDLE_SMART>,
2051 <SYSC_IDLE_SMART_WKUP>;
2052 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2053 <SYSC_IDLE_NO>,
2054 <SYSC_IDLE_SMART>,
2055 <SYSC_IDLE_SMART_WKUP>;
2056 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
2057 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
2058 clock-names = "fck";
2059 #address-cells = <1>;
2060 #size-cells = <1>;
2061 ranges = <0x0 0x4000 0x1000>;
2062
2063 epwmss2: epwmss@0 {
2064 compatible = "ti,am33xx-pwmss";
2065 reg = <0x0 0x10>;
2066 #address-cells = <1>;
2067 #size-cells = <1>;
2068 status = "disabled";
2069 ranges = <0 0 0x1000>;
2070
2071 ecap2: ecap@100 {
2072 compatible = "ti,am3352-ecap",
2073 "ti,am33xx-ecap";
2074 #pwm-cells = <3>;
2075 reg = <0x100 0x80>;
2076 clocks = <&l4ls_gclk>;
2077 clock-names = "fck";
2078 interrupts = <61>;
2079 interrupt-names = "ecap2";
2080 status = "disabled";
2081 };
2082
2083 eqep2: counter@180 {
2084 compatible = "ti,am3352-eqep";
2085 reg = <0x180 0x80>;
2086 clocks = <&l4ls_gclk>;
2087 clock-names = "sysclkout";
2088 interrupts = <89>;
2089 status = "disabled";
2090 };
2091
2092 ehrpwm2: pwm@200 {
2093 compatible = "ti,am3352-ehrpwm",
2094 "ti,am33xx-ehrpwm";
2095 #pwm-cells = <3>;
2096 reg = <0x200 0x80>;
2097 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
2098 clock-names = "tbclk", "fck";
2099 status = "disabled";
2100 };
2101 };
2102 };
2103
2104 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
2105 compatible = "ti,sysc-omap4", "ti,sysc";
2106 reg = <0xe000 0x4>,
2107 <0xe054 0x4>;
2108 reg-names = "rev", "sysc";
2109 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2110 <SYSC_IDLE_NO>,
2111 <SYSC_IDLE_SMART>;
2112 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2113 <SYSC_IDLE_NO>,
2114 <SYSC_IDLE_SMART>;
2115 /* Domains (P, C): per_pwrdm, lcdc_clkdm */
2116 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
2117 clock-names = "fck";
2118 #address-cells = <1>;
2119 #size-cells = <1>;
2120 ranges = <0x0 0xe000 0x1000>;
2121
2122 lcdc: lcdc@0 {
2123 compatible = "ti,am33xx-tilcdc";
2124 reg = <0x0 0x1000>;
2125 interrupts = <36>;
2126 status = "disabled";
2127 };
2128 };
2129
2130 target-module@10000 { /* 0x48310000, ap 76 4e.1 */
2131 compatible = "ti,sysc-omap2", "ti,sysc";
2132 reg = <0x11fe0 0x4>,
2133 <0x11fe4 0x4>;
2134 reg-names = "rev", "sysc";
2135 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
2136 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2137 <SYSC_IDLE_NO>;
2138 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
2139 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
2140 clock-names = "fck";
2141 #address-cells = <1>;
2142 #size-cells = <1>;
2143 ranges = <0x0 0x10000 0x2000>;
2144
2145 rng: rng@0 {
2146 compatible = "ti,omap4-rng";
2147 reg = <0x0 0x2000>;
2148 interrupts = <111>;
2149 };
2150 };
2151
2152 target-module@13000 { /* 0x48313000, ap 97 62.0 */
2153 compatible = "ti,sysc";
2154 status = "disabled";
2155 #address-cells = <1>;
2156 #size-cells = <1>;
2157 ranges = <0x0 0x13000 0x1000>;
2158 };
2159
2160 target-module@15000 { /* 0x48315000, ap 94 56.0 */
2161 compatible = "ti,sysc";
2162 status = "disabled";
2163 #address-cells = <1>;
2164 #size-cells = <1>;
2165 ranges = <0x00000000 0x00015000 0x00001000>,
2166 <0x00001000 0x00016000 0x00001000>;
2167 };
2168
2169 target-module@18000 { /* 0x48318000, ap 74 4c.0 */
2170 compatible = "ti,sysc";
2171 status = "disabled";
2172 #address-cells = <1>;
2173 #size-cells = <1>;
2174 ranges = <0x0 0x18000 0x4000>;
2175 };
2176
2177 target-module@20000 { /* 0x48320000, ap 99 34.0 */
2178 compatible = "ti,sysc";
2179 status = "disabled";
2180 #address-cells = <1>;
2181 #size-cells = <1>;
2182 ranges = <0x0 0x20000 0x1000>;
2183 };
2184
2185 target-module@22000 { /* 0x48322000, ap 101 3e.0 */
2186 compatible = "ti,sysc";
2187 status = "disabled";
2188 #address-cells = <1>;
2189 #size-cells = <1>;
2190 ranges = <0x0 0x22000 0x1000>;
2191 };
2192
2193 target-module@24000 { /* 0x48324000, ap 103 68.0 */
2194 compatible = "ti,sysc";
2195 status = "disabled";
2196 #address-cells = <1>;
2197 #size-cells = <1>;
2198 ranges = <0x0 0x24000 0x1000>;
2199 };
2200 };
2201};
2202