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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
8
9maintainers:
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
12
13description:
14 The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
15 (one external) and provides Ethernet packet communication for the device.
16 CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
17 Reduced Media Independent Interface (RMII), the Management Data
18 Input/Output (MDIO) interface for physical layer device (PHY) management,
19 new version of Common Platform Time Sync (CPTS), updated Address Lookup
20 Engine (ALE).
21 One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and
22 an internal Communications Port Programming Interface (CPPI5) (Host port 0).
23 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
24 and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA
25 Peripheral Root Complex (UDMA-P) controller.
26 The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0.
27
28 Additional features
29 priority level Quality Of Service (QOS) support (802.1p)
30 Support for Audio/Video Bridging (P802.1Qav/D6.0)
31 Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
32 Flow Control (802.3x) Support
33 Time Sensitive Network Support
34 IEEE P902.3br/D2.0 Interspersing Express Traffic
35 IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
36 Configurable number of addresses plus VLANs
37 Configurable number of classifier/policers
38 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
39 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
40 RX/TX csum offload
41
42 Specifications can be found at
43 http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
44 http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf
45
46properties:
47 "#address-cells": true
48 "#size-cells": true
49
50 compatible:
51 oneOf:
52 - const: ti,am654-cpsw-nuss
53 - const: ti,j721e-cpsw-nuss
54
55 reg:
56 maxItems: 1
57 description:
58 The physical base address and size of full the CPSW2G NUSS IO range
59
60 reg-names:
61 items:
62 - const: cpsw_nuss
63
64 ranges: true
65
66 dma-coherent: true
67
68 clocks:
69 description: CPSW2G NUSS functional clock
70
71 clock-names:
72 items:
73 - const: fck
74
75 power-domains:
76 maxItems: 1
77
78 dmas:
79 maxItems: 9
80
81 dma-names:
82 items:
83 - const: tx0
84 - const: tx1
85 - const: tx2
86 - const: tx3
87 - const: tx4
88 - const: tx5
89 - const: tx6
90 - const: tx7
91 - const: rx
92
93 ethernet-ports:
94 type: object
95 properties:
96 '#address-cells':
97 const: 1
98 '#size-cells':
99 const: 0
100
101 patternProperties:
102 port@1:
103 type: object
104 description: CPSW2G NUSS external ports
105
106 $ref: ethernet-controller.yaml#
107
108 properties:
109 reg:
110 items:
111 - const: 1
112 description: CPSW port number
113
114 phys:
115 maxItems: 1
116 description: phandle on phy-gmii-sel PHY
117
118 label:
119 description: label associated with this port
120
121 ti,mac-only:
122 $ref: /schemas/types.yaml#/definitions/flag
123 description:
124 Specifies the port works in mac-only mode.
125
126 ti,syscon-efuse:
127 $ref: /schemas/types.yaml#/definitions/phandle-array
128 description:
129 Phandle to the system control device node which provides access
130 to efuse IO range with MAC addresses
131
132 required:
133 - reg
134 - phys
135
136 additionalProperties: false
137
138patternProperties:
139 "^mdio@[0-9a-f]+$":
140 type: object
141 $ref: "ti,davinci-mdio.yaml#"
142
143 description:
144 CPSW MDIO bus.
145
146 "^cpts@[0-9a-f]+":
147 type: object
148 $ref: "ti,k3-am654-cpts.yaml#"
149 description:
150 CPSW Common Platform Time Sync (CPTS) module.
151
152required:
153 - compatible
154 - reg
155 - reg-names
156 - ranges
157 - clocks
158 - clock-names
159 - power-domains
160 - dmas
161 - dma-names
162 - '#address-cells'
163 - '#size-cells'
164
165additionalProperties: false
166
167examples:
168 - |
169 #include <dt-bindings/pinctrl/k3.h>
170 #include <dt-bindings/soc/ti,sci_pm_domain.h>
171 #include <dt-bindings/net/ti-dp83867.h>
172 #include <dt-bindings/interrupt-controller/irq.h>
173 #include <dt-bindings/interrupt-controller/arm-gic.h>
174
175 bus {
176 #address-cells = <2>;
177 #size-cells = <2>;
178
179 mcu_cpsw: ethernet@46000000 {
180 compatible = "ti,am654-cpsw-nuss";
181 #address-cells = <2>;
182 #size-cells = <2>;
183 reg = <0x0 0x46000000 0x0 0x200000>;
184 reg-names = "cpsw_nuss";
185 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
186 dma-coherent;
187 clocks = <&k3_clks 5 10>;
188 clock-names = "fck";
189 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
192
193 dmas = <&mcu_udmap 0xf000>,
194 <&mcu_udmap 0xf001>,
195 <&mcu_udmap 0xf002>,
196 <&mcu_udmap 0xf003>,
197 <&mcu_udmap 0xf004>,
198 <&mcu_udmap 0xf005>,
199 <&mcu_udmap 0xf006>,
200 <&mcu_udmap 0xf007>,
201 <&mcu_udmap 0x7000>;
202 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
203 "rx";
204
205 ethernet-ports {
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 cpsw_port1: port@1 {
210 reg = <1>;
211 ti,mac-only;
212 label = "port1";
213 ti,syscon-efuse = <&mcu_conf 0x200>;
214 phys = <&phy_gmii_sel 1>;
215
216 phy-mode = "rgmii-rxid";
217 phy-handle = <&phy0>;
218 };
219 };
220
221 davinci_mdio: mdio@f00 {
222 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
223 reg = <0x0 0xf00 0x0 0x100>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 clocks = <&k3_clks 5 10>;
227 clock-names = "fck";
228 bus_freq = <1000000>;
229
230 phy0: ethernet-phy@0 {
231 reg = <0>;
232 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
233 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
234 };
235 };
236 };
237
238 cpts@3d000 {
239 compatible = "ti,am65-cpts";
240 reg = <0x0 0x3d000 0x0 0x400>;
241 clocks = <&k3_clks 18 2>;
242 clock-names = "cpts";
243 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
244 interrupt-names = "cpts";
245 ti,cpts-ext-ts-inputs = <4>;
246 ti,cpts-periodic-outputs = <2>;
247 };
248 };