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Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Altera Corporation
4 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
5 *
6 * Modified from mach-picoxcell/time.c
7 */
8#include <linux/delay.h>
9#include <linux/dw_apb_timer.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_irq.h>
13#include <linux/clk.h>
14#include <linux/reset.h>
15#include <linux/sched_clock.h>
16
17static int __init timer_get_base_and_rate(struct device_node *np,
18 void __iomem **base, u32 *rate)
19{
20 struct clk *timer_clk;
21 struct clk *pclk;
22 struct reset_control *rstc;
23 int ret;
24
25 *base = of_iomap(np, 0);
26
27 if (!*base)
28 panic("Unable to map regs for %pOFn", np);
29
30 /*
31 * Reset the timer if the reset control is available, wiping
32 * out the state the firmware may have left it
33 */
34 rstc = of_reset_control_get(np, NULL);
35 if (!IS_ERR(rstc)) {
36 reset_control_assert(rstc);
37 reset_control_deassert(rstc);
38 }
39
40 /*
41 * Not all implementations use a periphal clock, so don't panic
42 * if it's not present
43 */
44 pclk = of_clk_get_by_name(np, "pclk");
45 if (!IS_ERR(pclk))
46 if (clk_prepare_enable(pclk))
47 pr_warn("pclk for %pOFn is present, but could not be activated\n",
48 np);
49
50 if (!of_property_read_u32(np, "clock-freq", rate) &&
51 !of_property_read_u32(np, "clock-frequency", rate))
52 return 0;
53
54 timer_clk = of_clk_get_by_name(np, "timer");
55 if (IS_ERR(timer_clk))
56 return PTR_ERR(timer_clk);
57
58 ret = clk_prepare_enable(timer_clk);
59 if (ret)
60 return ret;
61
62 *rate = clk_get_rate(timer_clk);
63 if (!(*rate))
64 return -EINVAL;
65
66 return 0;
67}
68
69static int __init add_clockevent(struct device_node *event_timer)
70{
71 void __iomem *iobase;
72 struct dw_apb_clock_event_device *ced;
73 u32 irq, rate;
74 int ret = 0;
75
76 irq = irq_of_parse_and_map(event_timer, 0);
77 if (irq == 0)
78 panic("No IRQ for clock event timer");
79
80 ret = timer_get_base_and_rate(event_timer, &iobase, &rate);
81 if (ret)
82 return ret;
83
84 ced = dw_apb_clockevent_init(-1, event_timer->name, 300, iobase, irq,
85 rate);
86 if (!ced)
87 return -EINVAL;
88
89 dw_apb_clockevent_register(ced);
90
91 return 0;
92}
93
94static void __iomem *sched_io_base;
95static u32 sched_rate;
96
97static int __init add_clocksource(struct device_node *source_timer)
98{
99 void __iomem *iobase;
100 struct dw_apb_clocksource *cs;
101 u32 rate;
102 int ret;
103
104 ret = timer_get_base_and_rate(source_timer, &iobase, &rate);
105 if (ret)
106 return ret;
107
108 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
109 if (!cs)
110 return -EINVAL;
111
112 dw_apb_clocksource_start(cs);
113 dw_apb_clocksource_register(cs);
114
115 /*
116 * Fallback to use the clocksource as sched_clock if no separate
117 * timer is found. sched_io_base then points to the current_value
118 * register of the clocksource timer.
119 */
120 sched_io_base = iobase + 0x04;
121 sched_rate = rate;
122
123 return 0;
124}
125
126static u64 notrace read_sched_clock(void)
127{
128 return ~readl_relaxed(sched_io_base);
129}
130
131static const struct of_device_id sptimer_ids[] __initconst = {
132 { .compatible = "picochip,pc3x2-rtc" },
133 { /* Sentinel */ },
134};
135
136static void __init init_sched_clock(void)
137{
138 struct device_node *sched_timer;
139
140 sched_timer = of_find_matching_node(NULL, sptimer_ids);
141 if (sched_timer) {
142 timer_get_base_and_rate(sched_timer, &sched_io_base,
143 &sched_rate);
144 of_node_put(sched_timer);
145 }
146
147 sched_clock_register(read_sched_clock, 32, sched_rate);
148}
149
150#ifdef CONFIG_ARM
151static unsigned long dw_apb_delay_timer_read(void)
152{
153 return ~readl_relaxed(sched_io_base);
154}
155
156static struct delay_timer dw_apb_delay_timer = {
157 .read_current_timer = dw_apb_delay_timer_read,
158};
159#endif
160
161static int num_called;
162static int __init dw_apb_timer_init(struct device_node *timer)
163{
164 int ret = 0;
165
166 switch (num_called) {
167 case 1:
168 pr_debug("%s: found clocksource timer\n", __func__);
169 ret = add_clocksource(timer);
170 if (ret)
171 return ret;
172 init_sched_clock();
173#ifdef CONFIG_ARM
174 dw_apb_delay_timer.freq = sched_rate;
175 register_current_timer_delay(&dw_apb_delay_timer);
176#endif
177 break;
178 default:
179 pr_debug("%s: found clockevent timer\n", __func__);
180 ret = add_clockevent(timer);
181 if (ret)
182 return ret;
183 break;
184 }
185
186 num_called++;
187
188 return 0;
189}
190TIMER_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
191TIMER_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
192TIMER_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
193TIMER_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);