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1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
4#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
5
6#include "mtk-pm-domains.h"
7#include <dt-bindings/power/mt8183-power.h>
8
9/*
10 * MT8183 power domain support
11 */
12
13static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
14 [MT8183_POWER_DOMAIN_AUDIO] = {
15 .sta_mask = PWR_STATUS_AUDIO,
16 .ctl_offs = 0x0314,
17 .sram_pdn_bits = GENMASK(11, 8),
18 .sram_pdn_ack_bits = GENMASK(15, 12),
19 },
20 [MT8183_POWER_DOMAIN_CONN] = {
21 .sta_mask = PWR_STATUS_CONN,
22 .ctl_offs = 0x032c,
23 .sram_pdn_bits = 0,
24 .sram_pdn_ack_bits = 0,
25 .bp_infracfg = {
26 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,
27 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
28 },
29 },
30 [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
31 .sta_mask = PWR_STATUS_MFG_ASYNC,
32 .ctl_offs = 0x0334,
33 .sram_pdn_bits = 0,
34 .sram_pdn_ack_bits = 0,
35 },
36 [MT8183_POWER_DOMAIN_MFG] = {
37 .sta_mask = PWR_STATUS_MFG,
38 .ctl_offs = 0x0338,
39 .sram_pdn_bits = GENMASK(8, 8),
40 .sram_pdn_ack_bits = GENMASK(12, 12),
41 },
42 [MT8183_POWER_DOMAIN_MFG_CORE0] = {
43 .sta_mask = BIT(7),
44 .ctl_offs = 0x034c,
45 .sram_pdn_bits = GENMASK(8, 8),
46 .sram_pdn_ack_bits = GENMASK(12, 12),
47 },
48 [MT8183_POWER_DOMAIN_MFG_CORE1] = {
49 .sta_mask = BIT(20),
50 .ctl_offs = 0x0310,
51 .sram_pdn_bits = GENMASK(8, 8),
52 .sram_pdn_ack_bits = GENMASK(12, 12),
53 },
54 [MT8183_POWER_DOMAIN_MFG_2D] = {
55 .sta_mask = PWR_STATUS_MFG_2D,
56 .ctl_offs = 0x0348,
57 .sram_pdn_bits = GENMASK(8, 8),
58 .sram_pdn_ack_bits = GENMASK(12, 12),
59 .bp_infracfg = {
60 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,
61 MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
62 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,
63 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
64 },
65 },
66 [MT8183_POWER_DOMAIN_DISP] = {
67 .sta_mask = PWR_STATUS_DISP,
68 .ctl_offs = 0x030c,
69 .sram_pdn_bits = GENMASK(8, 8),
70 .sram_pdn_ack_bits = GENMASK(12, 12),
71 .bp_infracfg = {
72 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,
73 MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
74 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,
75 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
76 },
77 .bp_smi = {
78 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
79 MT8183_SMI_COMMON_CLAMP_EN_SET,
80 MT8183_SMI_COMMON_CLAMP_EN_CLR,
81 MT8183_SMI_COMMON_CLAMP_EN),
82 },
83 },
84 [MT8183_POWER_DOMAIN_CAM] = {
85 .sta_mask = BIT(25),
86 .ctl_offs = 0x0344,
87 .sram_pdn_bits = GENMASK(9, 8),
88 .sram_pdn_ack_bits = GENMASK(13, 12),
89 .bp_infracfg = {
90 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,
91 MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),
92 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,
93 MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
94 BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
95 MT8183_TOP_AXI_PROT_EN_MM_SET,
96 MT8183_TOP_AXI_PROT_EN_MM_CLR,
97 MT8183_TOP_AXI_PROT_EN_MM_STA1),
98 },
99 .bp_smi = {
100 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
101 MT8183_SMI_COMMON_CLAMP_EN_SET,
102 MT8183_SMI_COMMON_CLAMP_EN_CLR,
103 MT8183_SMI_COMMON_CLAMP_EN),
104 },
105 },
106 [MT8183_POWER_DOMAIN_ISP] = {
107 .sta_mask = PWR_STATUS_ISP,
108 .ctl_offs = 0x0308,
109 .sram_pdn_bits = GENMASK(9, 8),
110 .sram_pdn_ack_bits = GENMASK(13, 12),
111 .bp_infracfg = {
112 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
113 MT8183_TOP_AXI_PROT_EN_MM_SET,
114 MT8183_TOP_AXI_PROT_EN_MM_CLR,
115 MT8183_TOP_AXI_PROT_EN_MM_STA1),
116 BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
117 MT8183_TOP_AXI_PROT_EN_MM_SET,
118 MT8183_TOP_AXI_PROT_EN_MM_CLR,
119 MT8183_TOP_AXI_PROT_EN_MM_STA1),
120 },
121 .bp_smi = {
122 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
123 MT8183_SMI_COMMON_CLAMP_EN_SET,
124 MT8183_SMI_COMMON_CLAMP_EN_CLR,
125 MT8183_SMI_COMMON_CLAMP_EN),
126 },
127 },
128 [MT8183_POWER_DOMAIN_VDEC] = {
129 .sta_mask = BIT(31),
130 .ctl_offs = 0x0300,
131 .sram_pdn_bits = GENMASK(8, 8),
132 .sram_pdn_ack_bits = GENMASK(12, 12),
133 .bp_smi = {
134 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
135 MT8183_SMI_COMMON_CLAMP_EN_SET,
136 MT8183_SMI_COMMON_CLAMP_EN_CLR,
137 MT8183_SMI_COMMON_CLAMP_EN),
138 },
139 },
140 [MT8183_POWER_DOMAIN_VENC] = {
141 .sta_mask = PWR_STATUS_VENC,
142 .ctl_offs = 0x0304,
143 .sram_pdn_bits = GENMASK(11, 8),
144 .sram_pdn_ack_bits = GENMASK(15, 12),
145 .bp_smi = {
146 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
147 MT8183_SMI_COMMON_CLAMP_EN_SET,
148 MT8183_SMI_COMMON_CLAMP_EN_CLR,
149 MT8183_SMI_COMMON_CLAMP_EN),
150 },
151 },
152 [MT8183_POWER_DOMAIN_VPU_TOP] = {
153 .sta_mask = BIT(26),
154 .ctl_offs = 0x0324,
155 .sram_pdn_bits = GENMASK(8, 8),
156 .sram_pdn_ack_bits = GENMASK(12, 12),
157 .bp_infracfg = {
158 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
159 MT8183_TOP_AXI_PROT_EN_MM_SET,
160 MT8183_TOP_AXI_PROT_EN_MM_CLR,
161 MT8183_TOP_AXI_PROT_EN_MM_STA1),
162 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
163 MT8183_TOP_AXI_PROT_EN_SET,
164 MT8183_TOP_AXI_PROT_EN_CLR,
165 MT8183_TOP_AXI_PROT_EN_STA1),
166 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
167 MT8183_TOP_AXI_PROT_EN_MM_SET,
168 MT8183_TOP_AXI_PROT_EN_MM_CLR,
169 MT8183_TOP_AXI_PROT_EN_MM_STA1),
170 },
171 .bp_smi = {
172 BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
173 MT8183_SMI_COMMON_CLAMP_EN_SET,
174 MT8183_SMI_COMMON_CLAMP_EN_CLR,
175 MT8183_SMI_COMMON_CLAMP_EN),
176 },
177 },
178 [MT8183_POWER_DOMAIN_VPU_CORE0] = {
179 .sta_mask = BIT(27),
180 .ctl_offs = 0x33c,
181 .sram_pdn_bits = GENMASK(11, 8),
182 .sram_pdn_ack_bits = GENMASK(13, 12),
183 .bp_infracfg = {
184 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
185 MT8183_TOP_AXI_PROT_EN_MCU_SET,
186 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
187 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
188 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
189 MT8183_TOP_AXI_PROT_EN_MCU_SET,
190 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
191 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
192 },
193 .caps = MTK_SCPD_SRAM_ISO,
194 },
195 [MT8183_POWER_DOMAIN_VPU_CORE1] = {
196 .sta_mask = BIT(28),
197 .ctl_offs = 0x0340,
198 .sram_pdn_bits = GENMASK(11, 8),
199 .sram_pdn_ack_bits = GENMASK(13, 12),
200 .bp_infracfg = {
201 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
202 MT8183_TOP_AXI_PROT_EN_MCU_SET,
203 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
204 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
205 BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
206 MT8183_TOP_AXI_PROT_EN_MCU_SET,
207 MT8183_TOP_AXI_PROT_EN_MCU_CLR,
208 MT8183_TOP_AXI_PROT_EN_MCU_STA1),
209 },
210 .caps = MTK_SCPD_SRAM_ISO,
211 },
212};
213
214static const struct scpsys_soc_data mt8183_scpsys_data = {
215 .domains_data = scpsys_domain_data_mt8183,
216 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
217 .pwr_sta_offs = 0x0180,
218 .pwr_sta2nd_offs = 0x0184
219};
220
221#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */