tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32
33#include <linux/compat.h>
34#include <linux/console.h>
35#include <linux/module.h>
36#include <linux/pm_runtime.h>
37#include <linux/vga_switcheroo.h>
38#include <linux/mmu_notifier.h>
39#include <linux/pci.h>
40
41#include <drm/drm_agpsupport.h>
42#include <drm/drm_crtc_helper.h>
43#include <drm/drm_drv.h>
44#include <drm/drm_fb_helper.h>
45#include <drm/drm_file.h>
46#include <drm/drm_gem.h>
47#include <drm/drm_ioctl.h>
48#include <drm/drm_pciids.h>
49#include <drm/drm_probe_helper.h>
50#include <drm/drm_vblank.h>
51#include <drm/radeon_drm.h>
52
53#include "radeon_drv.h"
54#include "radeon.h"
55#include "radeon_kms.h"
56#include "radeon_ttm.h"
57#include "radeon_device.h"
58#include "radeon_prime.h"
59
60/*
61 * KMS wrapper.
62 * - 2.0.0 - initial interface
63 * - 2.1.0 - add square tiling interface
64 * - 2.2.0 - add r6xx/r7xx const buffer support
65 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
66 * - 2.4.0 - add crtc id query
67 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
68 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
69 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
70 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
71 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
72 * 2.10.0 - fusion 2D tiling
73 * 2.11.0 - backend map, initial compute support for the CS checker
74 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
75 * 2.13.0 - virtual memory support, streamout
76 * 2.14.0 - add evergreen tiling informations
77 * 2.15.0 - add max_pipes query
78 * 2.16.0 - fix evergreen 2D tiled surface calculation
79 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
80 * 2.18.0 - r600-eg: allow "invalid" DB formats
81 * 2.19.0 - r600-eg: MSAA textures
82 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
83 * 2.21.0 - r600-r700: FMASK and CMASK
84 * 2.22.0 - r600 only: RESOLVE_BOX allowed
85 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
86 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
87 * 2.25.0 - eg+: new info request for num SE and num SH
88 * 2.26.0 - r600-eg: fix htile size computation
89 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
90 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
91 * 2.29.0 - R500 FP16 color clear registers
92 * 2.30.0 - fix for FMASK texturing
93 * 2.31.0 - Add fastfb support for rs690
94 * 2.32.0 - new info request for rings working
95 * 2.33.0 - Add SI tiling mode array query
96 * 2.34.0 - Add CIK tiling mode array query
97 * 2.35.0 - Add CIK macrotile mode array query
98 * 2.36.0 - Fix CIK DCE tiling setup
99 * 2.37.0 - allow GS ring setup on r6xx/r7xx
100 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
101 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
102 * 2.39.0 - Add INFO query for number of active CUs
103 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
104 * CS to GPU on >= r600
105 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
106 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
107 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
108 * 2.44.0 - SET_APPEND_CNT packet3 support
109 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
110 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
111 * 2.47.0 - Add UVD_NO_OP register support
112 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
113 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
114 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
115 */
116#define KMS_DRIVER_MAJOR 2
117#define KMS_DRIVER_MINOR 50
118#define KMS_DRIVER_PATCHLEVEL 0
119int radeon_suspend_kms(struct drm_device *dev, bool suspend,
120 bool fbcon, bool freeze);
121int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
122extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
123 unsigned int flags, int *vpos, int *hpos,
124 ktime_t *stime, ktime_t *etime,
125 const struct drm_display_mode *mode);
126extern bool radeon_is_px(struct drm_device *dev);
127int radeon_mode_dumb_mmap(struct drm_file *filp,
128 struct drm_device *dev,
129 uint32_t handle, uint64_t *offset_p);
130int radeon_mode_dumb_create(struct drm_file *file_priv,
131 struct drm_device *dev,
132 struct drm_mode_create_dumb *args);
133
134/* atpx handler */
135#if defined(CONFIG_VGA_SWITCHEROO)
136void radeon_register_atpx_handler(void);
137void radeon_unregister_atpx_handler(void);
138bool radeon_has_atpx_dgpu_power_cntl(void);
139bool radeon_is_atpx_hybrid(void);
140#else
141static inline void radeon_register_atpx_handler(void) {}
142static inline void radeon_unregister_atpx_handler(void) {}
143static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
144static inline bool radeon_is_atpx_hybrid(void) { return false; }
145#endif
146
147int radeon_no_wb;
148int radeon_modeset = -1;
149int radeon_dynclks = -1;
150int radeon_r4xx_atom = 0;
151int radeon_agpmode = -1;
152int radeon_vram_limit = 0;
153int radeon_gart_size = -1; /* auto */
154int radeon_benchmarking = 0;
155int radeon_testing = 0;
156int radeon_connector_table = 0;
157int radeon_tv = 1;
158int radeon_audio = -1;
159int radeon_disp_priority = 0;
160int radeon_hw_i2c = 0;
161int radeon_pcie_gen2 = -1;
162int radeon_msi = -1;
163int radeon_lockup_timeout = 10000;
164int radeon_fastfb = 0;
165int radeon_dpm = -1;
166int radeon_aspm = -1;
167int radeon_runtime_pm = -1;
168int radeon_hard_reset = 0;
169int radeon_vm_size = 8;
170int radeon_vm_block_size = -1;
171int radeon_deep_color = 0;
172int radeon_use_pflipirq = 2;
173int radeon_bapm = -1;
174int radeon_backlight = -1;
175int radeon_auxch = -1;
176int radeon_mst = 0;
177int radeon_uvd = 1;
178int radeon_vce = 1;
179
180MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
181module_param_named(no_wb, radeon_no_wb, int, 0444);
182
183MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
184module_param_named(modeset, radeon_modeset, int, 0400);
185
186MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
187module_param_named(dynclks, radeon_dynclks, int, 0444);
188
189MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
190module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
191
192MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
193module_param_named(vramlimit, radeon_vram_limit, int, 0600);
194
195MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
196module_param_named(agpmode, radeon_agpmode, int, 0444);
197
198MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
199module_param_named(gartsize, radeon_gart_size, int, 0600);
200
201MODULE_PARM_DESC(benchmark, "Run benchmark");
202module_param_named(benchmark, radeon_benchmarking, int, 0444);
203
204MODULE_PARM_DESC(test, "Run tests");
205module_param_named(test, radeon_testing, int, 0444);
206
207MODULE_PARM_DESC(connector_table, "Force connector table");
208module_param_named(connector_table, radeon_connector_table, int, 0444);
209
210MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
211module_param_named(tv, radeon_tv, int, 0444);
212
213MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
214module_param_named(audio, radeon_audio, int, 0444);
215
216MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
217module_param_named(disp_priority, radeon_disp_priority, int, 0444);
218
219MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
220module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
221
222MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
223module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
224
225MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
226module_param_named(msi, radeon_msi, int, 0444);
227
228MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
229module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
230
231MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
232module_param_named(fastfb, radeon_fastfb, int, 0444);
233
234MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
235module_param_named(dpm, radeon_dpm, int, 0444);
236
237MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
238module_param_named(aspm, radeon_aspm, int, 0444);
239
240MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
241module_param_named(runpm, radeon_runtime_pm, int, 0444);
242
243MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
244module_param_named(hard_reset, radeon_hard_reset, int, 0444);
245
246MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
247module_param_named(vm_size, radeon_vm_size, int, 0444);
248
249MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
250module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
251
252MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
253module_param_named(deep_color, radeon_deep_color, int, 0444);
254
255MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
256module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
257
258MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
259module_param_named(bapm, radeon_bapm, int, 0444);
260
261MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
262module_param_named(backlight, radeon_backlight, int, 0444);
263
264MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
265module_param_named(auxch, radeon_auxch, int, 0444);
266
267MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
268module_param_named(mst, radeon_mst, int, 0444);
269
270MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
271module_param_named(uvd, radeon_uvd, int, 0444);
272
273MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
274module_param_named(vce, radeon_vce, int, 0444);
275
276int radeon_si_support = 1;
277MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
278module_param_named(si_support, radeon_si_support, int, 0444);
279
280int radeon_cik_support = 1;
281MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
282module_param_named(cik_support, radeon_cik_support, int, 0444);
283
284static struct pci_device_id pciidlist[] = {
285 radeon_PCI_IDS
286};
287
288MODULE_DEVICE_TABLE(pci, pciidlist);
289
290static const struct drm_driver kms_driver;
291
292static int radeon_pci_probe(struct pci_dev *pdev,
293 const struct pci_device_id *ent)
294{
295 unsigned long flags = 0;
296 struct drm_device *dev;
297 int ret;
298
299 if (!ent)
300 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */
301
302 flags = ent->driver_data;
303
304 if (!radeon_si_support) {
305 switch (flags & RADEON_FAMILY_MASK) {
306 case CHIP_TAHITI:
307 case CHIP_PITCAIRN:
308 case CHIP_VERDE:
309 case CHIP_OLAND:
310 case CHIP_HAINAN:
311 dev_info(&pdev->dev,
312 "SI support disabled by module param\n");
313 return -ENODEV;
314 }
315 }
316 if (!radeon_cik_support) {
317 switch (flags & RADEON_FAMILY_MASK) {
318 case CHIP_KAVERI:
319 case CHIP_BONAIRE:
320 case CHIP_HAWAII:
321 case CHIP_KABINI:
322 case CHIP_MULLINS:
323 dev_info(&pdev->dev,
324 "CIK support disabled by module param\n");
325 return -ENODEV;
326 }
327 }
328
329 if (vga_switcheroo_client_probe_defer(pdev))
330 return -EPROBE_DEFER;
331
332 /* Get rid of things like offb */
333 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "radeondrmfb");
334 if (ret)
335 return ret;
336
337 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
338 if (IS_ERR(dev))
339 return PTR_ERR(dev);
340
341 ret = pci_enable_device(pdev);
342 if (ret)
343 goto err_free;
344
345 dev->pdev = pdev;
346#ifdef __alpha__
347 dev->hose = pdev->sysdata;
348#endif
349
350 pci_set_drvdata(pdev, dev);
351
352 if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
353 dev->agp = drm_agp_init(dev);
354 if (dev->agp) {
355 dev->agp->agp_mtrr = arch_phys_wc_add(
356 dev->agp->agp_info.aper_base,
357 dev->agp->agp_info.aper_size *
358 1024 * 1024);
359 }
360
361 ret = drm_dev_register(dev, ent->driver_data);
362 if (ret)
363 goto err_agp;
364
365 return 0;
366
367err_agp:
368 if (dev->agp)
369 arch_phys_wc_del(dev->agp->agp_mtrr);
370 kfree(dev->agp);
371 pci_disable_device(pdev);
372err_free:
373 drm_dev_put(dev);
374 return ret;
375}
376
377static void
378radeon_pci_remove(struct pci_dev *pdev)
379{
380 struct drm_device *dev = pci_get_drvdata(pdev);
381
382 drm_put_dev(dev);
383}
384
385static void
386radeon_pci_shutdown(struct pci_dev *pdev)
387{
388 /* if we are running in a VM, make sure the device
389 * torn down properly on reboot/shutdown
390 */
391 if (radeon_device_is_virtual())
392 radeon_pci_remove(pdev);
393
394#ifdef CONFIG_PPC64
395 /*
396 * Some adapters need to be suspended before a
397 * shutdown occurs in order to prevent an error
398 * during kexec.
399 * Make this power specific becauase it breaks
400 * some non-power boards.
401 */
402 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false);
403#endif
404}
405
406static int radeon_pmops_suspend(struct device *dev)
407{
408 struct drm_device *drm_dev = dev_get_drvdata(dev);
409 return radeon_suspend_kms(drm_dev, true, true, false);
410}
411
412static int radeon_pmops_resume(struct device *dev)
413{
414 struct drm_device *drm_dev = dev_get_drvdata(dev);
415
416 /* GPU comes up enabled by the bios on resume */
417 if (radeon_is_px(drm_dev)) {
418 pm_runtime_disable(dev);
419 pm_runtime_set_active(dev);
420 pm_runtime_enable(dev);
421 }
422
423 return radeon_resume_kms(drm_dev, true, true);
424}
425
426static int radeon_pmops_freeze(struct device *dev)
427{
428 struct drm_device *drm_dev = dev_get_drvdata(dev);
429 return radeon_suspend_kms(drm_dev, false, true, true);
430}
431
432static int radeon_pmops_thaw(struct device *dev)
433{
434 struct drm_device *drm_dev = dev_get_drvdata(dev);
435 return radeon_resume_kms(drm_dev, false, true);
436}
437
438static int radeon_pmops_runtime_suspend(struct device *dev)
439{
440 struct pci_dev *pdev = to_pci_dev(dev);
441 struct drm_device *drm_dev = pci_get_drvdata(pdev);
442
443 if (!radeon_is_px(drm_dev)) {
444 pm_runtime_forbid(dev);
445 return -EBUSY;
446 }
447
448 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
449 drm_kms_helper_poll_disable(drm_dev);
450
451 radeon_suspend_kms(drm_dev, false, false, false);
452 pci_save_state(pdev);
453 pci_disable_device(pdev);
454 pci_ignore_hotplug(pdev);
455 if (radeon_is_atpx_hybrid())
456 pci_set_power_state(pdev, PCI_D3cold);
457 else if (!radeon_has_atpx_dgpu_power_cntl())
458 pci_set_power_state(pdev, PCI_D3hot);
459 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
460
461 return 0;
462}
463
464static int radeon_pmops_runtime_resume(struct device *dev)
465{
466 struct pci_dev *pdev = to_pci_dev(dev);
467 struct drm_device *drm_dev = pci_get_drvdata(pdev);
468 int ret;
469
470 if (!radeon_is_px(drm_dev))
471 return -EINVAL;
472
473 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
474
475 if (radeon_is_atpx_hybrid() ||
476 !radeon_has_atpx_dgpu_power_cntl())
477 pci_set_power_state(pdev, PCI_D0);
478 pci_restore_state(pdev);
479 ret = pci_enable_device(pdev);
480 if (ret)
481 return ret;
482 pci_set_master(pdev);
483
484 ret = radeon_resume_kms(drm_dev, false, false);
485 drm_kms_helper_poll_enable(drm_dev);
486 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
487 return 0;
488}
489
490static int radeon_pmops_runtime_idle(struct device *dev)
491{
492 struct drm_device *drm_dev = dev_get_drvdata(dev);
493 struct drm_crtc *crtc;
494
495 if (!radeon_is_px(drm_dev)) {
496 pm_runtime_forbid(dev);
497 return -EBUSY;
498 }
499
500 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
501 if (crtc->enabled) {
502 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
503 return -EBUSY;
504 }
505 }
506
507 pm_runtime_mark_last_busy(dev);
508 pm_runtime_autosuspend(dev);
509 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
510 return 1;
511}
512
513long radeon_drm_ioctl(struct file *filp,
514 unsigned int cmd, unsigned long arg)
515{
516 struct drm_file *file_priv = filp->private_data;
517 struct drm_device *dev;
518 long ret;
519 dev = file_priv->minor->dev;
520 ret = pm_runtime_get_sync(dev->dev);
521 if (ret < 0) {
522 pm_runtime_put_autosuspend(dev->dev);
523 return ret;
524 }
525
526 ret = drm_ioctl(filp, cmd, arg);
527
528 pm_runtime_mark_last_busy(dev->dev);
529 pm_runtime_put_autosuspend(dev->dev);
530 return ret;
531}
532
533#ifdef CONFIG_COMPAT
534static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
535{
536 unsigned int nr = DRM_IOCTL_NR(cmd);
537 int ret;
538
539 if (nr < DRM_COMMAND_BASE)
540 return drm_compat_ioctl(filp, cmd, arg);
541
542 ret = radeon_drm_ioctl(filp, cmd, arg);
543
544 return ret;
545}
546#endif
547
548static const struct dev_pm_ops radeon_pm_ops = {
549 .suspend = radeon_pmops_suspend,
550 .resume = radeon_pmops_resume,
551 .freeze = radeon_pmops_freeze,
552 .thaw = radeon_pmops_thaw,
553 .poweroff = radeon_pmops_freeze,
554 .restore = radeon_pmops_resume,
555 .runtime_suspend = radeon_pmops_runtime_suspend,
556 .runtime_resume = radeon_pmops_runtime_resume,
557 .runtime_idle = radeon_pmops_runtime_idle,
558};
559
560static const struct file_operations radeon_driver_kms_fops = {
561 .owner = THIS_MODULE,
562 .open = drm_open,
563 .release = drm_release,
564 .unlocked_ioctl = radeon_drm_ioctl,
565 .mmap = radeon_mmap,
566 .poll = drm_poll,
567 .read = drm_read,
568#ifdef CONFIG_COMPAT
569 .compat_ioctl = radeon_kms_compat_ioctl,
570#endif
571};
572
573static const struct drm_ioctl_desc radeon_ioctls_kms[] = {
574 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
575 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
576 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
577 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
578 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
579 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
580 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
581 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
582 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
583 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
584 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
585 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
586 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
587 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
588 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
589 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
590 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
591 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
592 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
593 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
594 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
595 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
596 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
597 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
598 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
599 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
600 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
601 /* KMS */
602 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
603 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
604 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
605 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
606 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
607 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
608 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
609 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
610 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
611 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
612 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
613 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
614 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
615 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
616 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
617};
618
619static const struct drm_driver kms_driver = {
620 .driver_features =
621 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET,
622 .load = radeon_driver_load_kms,
623 .open = radeon_driver_open_kms,
624 .postclose = radeon_driver_postclose_kms,
625 .lastclose = radeon_driver_lastclose_kms,
626 .unload = radeon_driver_unload_kms,
627 .irq_preinstall = radeon_driver_irq_preinstall_kms,
628 .irq_postinstall = radeon_driver_irq_postinstall_kms,
629 .irq_uninstall = radeon_driver_irq_uninstall_kms,
630 .irq_handler = radeon_driver_irq_handler_kms,
631 .ioctls = radeon_ioctls_kms,
632 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms),
633 .dumb_create = radeon_mode_dumb_create,
634 .dumb_map_offset = radeon_mode_dumb_mmap,
635 .fops = &radeon_driver_kms_fops,
636
637 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
638 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
639 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
640
641 .name = DRIVER_NAME,
642 .desc = DRIVER_DESC,
643 .date = DRIVER_DATE,
644 .major = KMS_DRIVER_MAJOR,
645 .minor = KMS_DRIVER_MINOR,
646 .patchlevel = KMS_DRIVER_PATCHLEVEL,
647};
648
649static struct pci_driver radeon_kms_pci_driver = {
650 .name = DRIVER_NAME,
651 .id_table = pciidlist,
652 .probe = radeon_pci_probe,
653 .remove = radeon_pci_remove,
654 .shutdown = radeon_pci_shutdown,
655 .driver.pm = &radeon_pm_ops,
656};
657
658static int __init radeon_module_init(void)
659{
660 if (vgacon_text_force() && radeon_modeset == -1) {
661 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
662 radeon_modeset = 0;
663 }
664
665 if (radeon_modeset == 0) {
666 DRM_ERROR("No UMS support in radeon module!\n");
667 return -EINVAL;
668 }
669
670 DRM_INFO("radeon kernel modesetting enabled.\n");
671 radeon_register_atpx_handler();
672
673 return pci_register_driver(&radeon_kms_pci_driver);
674}
675
676static void __exit radeon_module_exit(void)
677{
678 pci_unregister_driver(&radeon_kms_pci_driver);
679 radeon_unregister_atpx_handler();
680 mmu_notifier_synchronize();
681}
682
683module_init(radeon_module_init);
684module_exit(radeon_module_exit);
685
686MODULE_AUTHOR(DRIVER_AUTHOR);
687MODULE_DESCRIPTION(DRIVER_DESC);
688MODULE_LICENSE("GPL and additional rights");