tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
21 device_type = "cpu";
22 reg = <0>;
23 };
24 };
25
26 arm-pmu {
27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>;
31 };
32
33 psci {
34 compatible = "arm,psci-1.0";
35 method = "smc";
36 };
37
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
53 };
54
55 clocks {
56 clk_hse: clk-hse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61
62 clk_hsi: clk-hsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
66 };
67
68 clk_lse: clk-lse {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 };
73
74 clk_lsi: clk-lsi {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 };
79
80 clk_csi: clk-csi {
81 #clock-cells = <0>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
84 };
85 };
86
87 thermal-zones {
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
90 polling-delay = <0>;
91 thermal-sensors = <&dts>;
92
93 trips {
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
96 hysteresis = <0>;
97 type = "passive";
98 };
99
100 cpu-crit {
101 temperature = <120000>;
102 hysteresis = <0>;
103 type = "critical";
104 };
105 };
106
107 cooling-maps {
108 };
109 };
110 };
111
112 booster: regulator-booster {
113 compatible = "st,stm32mp1-booster";
114 st,syscfg = <&syscfg>;
115 status = "disabled";
116 };
117
118 soc {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 interrupt-parent = <&intc>;
123 ranges;
124
125 timers2: timer@40000000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "st,stm32-timers";
129 reg = <0x40000000 0x400>;
130 clocks = <&rcc TIM2_K>;
131 clock-names = "int";
132 dmas = <&dmamux1 18 0x400 0x1>,
133 <&dmamux1 19 0x400 0x1>,
134 <&dmamux1 20 0x400 0x1>,
135 <&dmamux1 21 0x400 0x1>,
136 <&dmamux1 22 0x400 0x1>;
137 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
138 status = "disabled";
139
140 pwm {
141 compatible = "st,stm32-pwm";
142 #pwm-cells = <3>;
143 status = "disabled";
144 };
145
146 timer@1 {
147 compatible = "st,stm32h7-timer-trigger";
148 reg = <1>;
149 status = "disabled";
150 };
151
152 counter {
153 compatible = "st,stm32-timer-counter";
154 status = "disabled";
155 };
156 };
157
158 timers3: timer@40001000 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "st,stm32-timers";
162 reg = <0x40001000 0x400>;
163 clocks = <&rcc TIM3_K>;
164 clock-names = "int";
165 dmas = <&dmamux1 23 0x400 0x1>,
166 <&dmamux1 24 0x400 0x1>,
167 <&dmamux1 25 0x400 0x1>,
168 <&dmamux1 26 0x400 0x1>,
169 <&dmamux1 27 0x400 0x1>,
170 <&dmamux1 28 0x400 0x1>;
171 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
172 status = "disabled";
173
174 pwm {
175 compatible = "st,stm32-pwm";
176 #pwm-cells = <3>;
177 status = "disabled";
178 };
179
180 timer@2 {
181 compatible = "st,stm32h7-timer-trigger";
182 reg = <2>;
183 status = "disabled";
184 };
185
186 counter {
187 compatible = "st,stm32-timer-counter";
188 status = "disabled";
189 };
190 };
191
192 timers4: timer@40002000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "st,stm32-timers";
196 reg = <0x40002000 0x400>;
197 clocks = <&rcc TIM4_K>;
198 clock-names = "int";
199 dmas = <&dmamux1 29 0x400 0x1>,
200 <&dmamux1 30 0x400 0x1>,
201 <&dmamux1 31 0x400 0x1>,
202 <&dmamux1 32 0x400 0x1>;
203 dma-names = "ch1", "ch2", "ch3", "ch4";
204 status = "disabled";
205
206 pwm {
207 compatible = "st,stm32-pwm";
208 #pwm-cells = <3>;
209 status = "disabled";
210 };
211
212 timer@3 {
213 compatible = "st,stm32h7-timer-trigger";
214 reg = <3>;
215 status = "disabled";
216 };
217
218 counter {
219 compatible = "st,stm32-timer-counter";
220 status = "disabled";
221 };
222 };
223
224 timers5: timer@40003000 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "st,stm32-timers";
228 reg = <0x40003000 0x400>;
229 clocks = <&rcc TIM5_K>;
230 clock-names = "int";
231 dmas = <&dmamux1 55 0x400 0x1>,
232 <&dmamux1 56 0x400 0x1>,
233 <&dmamux1 57 0x400 0x1>,
234 <&dmamux1 58 0x400 0x1>,
235 <&dmamux1 59 0x400 0x1>,
236 <&dmamux1 60 0x400 0x1>;
237 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
238 status = "disabled";
239
240 pwm {
241 compatible = "st,stm32-pwm";
242 #pwm-cells = <3>;
243 status = "disabled";
244 };
245
246 timer@4 {
247 compatible = "st,stm32h7-timer-trigger";
248 reg = <4>;
249 status = "disabled";
250 };
251
252 counter {
253 compatible = "st,stm32-timer-counter";
254 status = "disabled";
255 };
256 };
257
258 timers6: timer@40004000 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 compatible = "st,stm32-timers";
262 reg = <0x40004000 0x400>;
263 clocks = <&rcc TIM6_K>;
264 clock-names = "int";
265 dmas = <&dmamux1 69 0x400 0x1>;
266 dma-names = "up";
267 status = "disabled";
268
269 timer@5 {
270 compatible = "st,stm32h7-timer-trigger";
271 reg = <5>;
272 status = "disabled";
273 };
274 };
275
276 timers7: timer@40005000 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "st,stm32-timers";
280 reg = <0x40005000 0x400>;
281 clocks = <&rcc TIM7_K>;
282 clock-names = "int";
283 dmas = <&dmamux1 70 0x400 0x1>;
284 dma-names = "up";
285 status = "disabled";
286
287 timer@6 {
288 compatible = "st,stm32h7-timer-trigger";
289 reg = <6>;
290 status = "disabled";
291 };
292 };
293
294 timers12: timer@40006000 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "st,stm32-timers";
298 reg = <0x40006000 0x400>;
299 clocks = <&rcc TIM12_K>;
300 clock-names = "int";
301 status = "disabled";
302
303 pwm {
304 compatible = "st,stm32-pwm";
305 #pwm-cells = <3>;
306 status = "disabled";
307 };
308
309 timer@11 {
310 compatible = "st,stm32h7-timer-trigger";
311 reg = <11>;
312 status = "disabled";
313 };
314 };
315
316 timers13: timer@40007000 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 compatible = "st,stm32-timers";
320 reg = <0x40007000 0x400>;
321 clocks = <&rcc TIM13_K>;
322 clock-names = "int";
323 status = "disabled";
324
325 pwm {
326 compatible = "st,stm32-pwm";
327 #pwm-cells = <3>;
328 status = "disabled";
329 };
330
331 timer@12 {
332 compatible = "st,stm32h7-timer-trigger";
333 reg = <12>;
334 status = "disabled";
335 };
336 };
337
338 timers14: timer@40008000 {
339 #address-cells = <1>;
340 #size-cells = <0>;
341 compatible = "st,stm32-timers";
342 reg = <0x40008000 0x400>;
343 clocks = <&rcc TIM14_K>;
344 clock-names = "int";
345 status = "disabled";
346
347 pwm {
348 compatible = "st,stm32-pwm";
349 #pwm-cells = <3>;
350 status = "disabled";
351 };
352
353 timer@13 {
354 compatible = "st,stm32h7-timer-trigger";
355 reg = <13>;
356 status = "disabled";
357 };
358 };
359
360 lptimer1: timer@40009000 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 compatible = "st,stm32-lptimer";
364 reg = <0x40009000 0x400>;
365 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&rcc LPTIM1_K>;
367 clock-names = "mux";
368 wakeup-source;
369 status = "disabled";
370
371 pwm {
372 compatible = "st,stm32-pwm-lp";
373 #pwm-cells = <3>;
374 status = "disabled";
375 };
376
377 trigger@0 {
378 compatible = "st,stm32-lptimer-trigger";
379 reg = <0>;
380 status = "disabled";
381 };
382
383 counter {
384 compatible = "st,stm32-lptimer-counter";
385 status = "disabled";
386 };
387 };
388
389 spi2: spi@4000b000 {
390 #address-cells = <1>;
391 #size-cells = <0>;
392 compatible = "st,stm32h7-spi";
393 reg = <0x4000b000 0x400>;
394 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&rcc SPI2_K>;
396 resets = <&rcc SPI2_R>;
397 dmas = <&dmamux1 39 0x400 0x05>,
398 <&dmamux1 40 0x400 0x05>;
399 dma-names = "rx", "tx";
400 status = "disabled";
401 };
402
403 i2s2: audio-controller@4000b000 {
404 compatible = "st,stm32h7-i2s";
405 #sound-dai-cells = <0>;
406 reg = <0x4000b000 0x400>;
407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
408 dmas = <&dmamux1 39 0x400 0x01>,
409 <&dmamux1 40 0x400 0x01>;
410 dma-names = "rx", "tx";
411 status = "disabled";
412 };
413
414 spi3: spi@4000c000 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "st,stm32h7-spi";
418 reg = <0x4000c000 0x400>;
419 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&rcc SPI3_K>;
421 resets = <&rcc SPI3_R>;
422 dmas = <&dmamux1 61 0x400 0x05>,
423 <&dmamux1 62 0x400 0x05>;
424 dma-names = "rx", "tx";
425 status = "disabled";
426 };
427
428 i2s3: audio-controller@4000c000 {
429 compatible = "st,stm32h7-i2s";
430 #sound-dai-cells = <0>;
431 reg = <0x4000c000 0x400>;
432 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
433 dmas = <&dmamux1 61 0x400 0x01>,
434 <&dmamux1 62 0x400 0x01>;
435 dma-names = "rx", "tx";
436 status = "disabled";
437 };
438
439 spdifrx: audio-controller@4000d000 {
440 compatible = "st,stm32h7-spdifrx";
441 #sound-dai-cells = <0>;
442 reg = <0x4000d000 0x400>;
443 clocks = <&rcc SPDIF_K>;
444 clock-names = "kclk";
445 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
446 dmas = <&dmamux1 93 0x400 0x01>,
447 <&dmamux1 94 0x400 0x01>;
448 dma-names = "rx", "rx-ctrl";
449 status = "disabled";
450 };
451
452 usart2: serial@4000e000 {
453 compatible = "st,stm32h7-uart";
454 reg = <0x4000e000 0x400>;
455 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&rcc USART2_K>;
457 status = "disabled";
458 };
459
460 usart3: serial@4000f000 {
461 compatible = "st,stm32h7-uart";
462 reg = <0x4000f000 0x400>;
463 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&rcc USART3_K>;
465 status = "disabled";
466 };
467
468 uart4: serial@40010000 {
469 compatible = "st,stm32h7-uart";
470 reg = <0x40010000 0x400>;
471 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&rcc UART4_K>;
473 status = "disabled";
474 };
475
476 uart5: serial@40011000 {
477 compatible = "st,stm32h7-uart";
478 reg = <0x40011000 0x400>;
479 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&rcc UART5_K>;
481 status = "disabled";
482 };
483
484 i2c1: i2c@40012000 {
485 compatible = "st,stm32mp15-i2c";
486 reg = <0x40012000 0x400>;
487 interrupt-names = "event", "error";
488 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&rcc I2C1_K>;
491 resets = <&rcc I2C1_R>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 st,syscfg-fmp = <&syscfg 0x4 0x1>;
495 wakeup-source;
496 status = "disabled";
497 };
498
499 i2c2: i2c@40013000 {
500 compatible = "st,stm32mp15-i2c";
501 reg = <0x40013000 0x400>;
502 interrupt-names = "event", "error";
503 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&rcc I2C2_K>;
506 resets = <&rcc I2C2_R>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 st,syscfg-fmp = <&syscfg 0x4 0x2>;
510 wakeup-source;
511 status = "disabled";
512 };
513
514 i2c3: i2c@40014000 {
515 compatible = "st,stm32mp15-i2c";
516 reg = <0x40014000 0x400>;
517 interrupt-names = "event", "error";
518 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&rcc I2C3_K>;
521 resets = <&rcc I2C3_R>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524 st,syscfg-fmp = <&syscfg 0x4 0x4>;
525 wakeup-source;
526 status = "disabled";
527 };
528
529 i2c5: i2c@40015000 {
530 compatible = "st,stm32mp15-i2c";
531 reg = <0x40015000 0x400>;
532 interrupt-names = "event", "error";
533 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&rcc I2C5_K>;
536 resets = <&rcc I2C5_R>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 st,syscfg-fmp = <&syscfg 0x4 0x10>;
540 wakeup-source;
541 status = "disabled";
542 };
543
544 cec: cec@40016000 {
545 compatible = "st,stm32-cec";
546 reg = <0x40016000 0x400>;
547 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&rcc CEC_K>, <&clk_lse>;
549 clock-names = "cec", "hdmi-cec";
550 status = "disabled";
551 };
552
553 dac: dac@40017000 {
554 compatible = "st,stm32h7-dac-core";
555 reg = <0x40017000 0x400>;
556 clocks = <&rcc DAC12>;
557 clock-names = "pclk";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 status = "disabled";
561
562 dac1: dac@1 {
563 compatible = "st,stm32-dac";
564 #io-channel-cells = <1>;
565 reg = <1>;
566 status = "disabled";
567 };
568
569 dac2: dac@2 {
570 compatible = "st,stm32-dac";
571 #io-channel-cells = <1>;
572 reg = <2>;
573 status = "disabled";
574 };
575 };
576
577 uart7: serial@40018000 {
578 compatible = "st,stm32h7-uart";
579 reg = <0x40018000 0x400>;
580 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&rcc UART7_K>;
582 status = "disabled";
583 };
584
585 uart8: serial@40019000 {
586 compatible = "st,stm32h7-uart";
587 reg = <0x40019000 0x400>;
588 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&rcc UART8_K>;
590 status = "disabled";
591 };
592
593 timers1: timer@44000000 {
594 #address-cells = <1>;
595 #size-cells = <0>;
596 compatible = "st,stm32-timers";
597 reg = <0x44000000 0x400>;
598 clocks = <&rcc TIM1_K>;
599 clock-names = "int";
600 dmas = <&dmamux1 11 0x400 0x1>,
601 <&dmamux1 12 0x400 0x1>,
602 <&dmamux1 13 0x400 0x1>,
603 <&dmamux1 14 0x400 0x1>,
604 <&dmamux1 15 0x400 0x1>,
605 <&dmamux1 16 0x400 0x1>,
606 <&dmamux1 17 0x400 0x1>;
607 dma-names = "ch1", "ch2", "ch3", "ch4",
608 "up", "trig", "com";
609 status = "disabled";
610
611 pwm {
612 compatible = "st,stm32-pwm";
613 #pwm-cells = <3>;
614 status = "disabled";
615 };
616
617 timer@0 {
618 compatible = "st,stm32h7-timer-trigger";
619 reg = <0>;
620 status = "disabled";
621 };
622
623 counter {
624 compatible = "st,stm32-timer-counter";
625 status = "disabled";
626 };
627 };
628
629 timers8: timer@44001000 {
630 #address-cells = <1>;
631 #size-cells = <0>;
632 compatible = "st,stm32-timers";
633 reg = <0x44001000 0x400>;
634 clocks = <&rcc TIM8_K>;
635 clock-names = "int";
636 dmas = <&dmamux1 47 0x400 0x1>,
637 <&dmamux1 48 0x400 0x1>,
638 <&dmamux1 49 0x400 0x1>,
639 <&dmamux1 50 0x400 0x1>,
640 <&dmamux1 51 0x400 0x1>,
641 <&dmamux1 52 0x400 0x1>,
642 <&dmamux1 53 0x400 0x1>;
643 dma-names = "ch1", "ch2", "ch3", "ch4",
644 "up", "trig", "com";
645 status = "disabled";
646
647 pwm {
648 compatible = "st,stm32-pwm";
649 #pwm-cells = <3>;
650 status = "disabled";
651 };
652
653 timer@7 {
654 compatible = "st,stm32h7-timer-trigger";
655 reg = <7>;
656 status = "disabled";
657 };
658
659 counter {
660 compatible = "st,stm32-timer-counter";
661 status = "disabled";
662 };
663 };
664
665 usart6: serial@44003000 {
666 compatible = "st,stm32h7-uart";
667 reg = <0x44003000 0x400>;
668 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&rcc USART6_K>;
670 status = "disabled";
671 };
672
673 spi1: spi@44004000 {
674 #address-cells = <1>;
675 #size-cells = <0>;
676 compatible = "st,stm32h7-spi";
677 reg = <0x44004000 0x400>;
678 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&rcc SPI1_K>;
680 resets = <&rcc SPI1_R>;
681 dmas = <&dmamux1 37 0x400 0x05>,
682 <&dmamux1 38 0x400 0x05>;
683 dma-names = "rx", "tx";
684 status = "disabled";
685 };
686
687 i2s1: audio-controller@44004000 {
688 compatible = "st,stm32h7-i2s";
689 #sound-dai-cells = <0>;
690 reg = <0x44004000 0x400>;
691 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
692 dmas = <&dmamux1 37 0x400 0x01>,
693 <&dmamux1 38 0x400 0x01>;
694 dma-names = "rx", "tx";
695 status = "disabled";
696 };
697
698 spi4: spi@44005000 {
699 #address-cells = <1>;
700 #size-cells = <0>;
701 compatible = "st,stm32h7-spi";
702 reg = <0x44005000 0x400>;
703 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&rcc SPI4_K>;
705 resets = <&rcc SPI4_R>;
706 dmas = <&dmamux1 83 0x400 0x05>,
707 <&dmamux1 84 0x400 0x05>;
708 dma-names = "rx", "tx";
709 status = "disabled";
710 };
711
712 timers15: timer@44006000 {
713 #address-cells = <1>;
714 #size-cells = <0>;
715 compatible = "st,stm32-timers";
716 reg = <0x44006000 0x400>;
717 clocks = <&rcc TIM15_K>;
718 clock-names = "int";
719 dmas = <&dmamux1 105 0x400 0x1>,
720 <&dmamux1 106 0x400 0x1>,
721 <&dmamux1 107 0x400 0x1>,
722 <&dmamux1 108 0x400 0x1>;
723 dma-names = "ch1", "up", "trig", "com";
724 status = "disabled";
725
726 pwm {
727 compatible = "st,stm32-pwm";
728 #pwm-cells = <3>;
729 status = "disabled";
730 };
731
732 timer@14 {
733 compatible = "st,stm32h7-timer-trigger";
734 reg = <14>;
735 status = "disabled";
736 };
737 };
738
739 timers16: timer@44007000 {
740 #address-cells = <1>;
741 #size-cells = <0>;
742 compatible = "st,stm32-timers";
743 reg = <0x44007000 0x400>;
744 clocks = <&rcc TIM16_K>;
745 clock-names = "int";
746 dmas = <&dmamux1 109 0x400 0x1>,
747 <&dmamux1 110 0x400 0x1>;
748 dma-names = "ch1", "up";
749 status = "disabled";
750
751 pwm {
752 compatible = "st,stm32-pwm";
753 #pwm-cells = <3>;
754 status = "disabled";
755 };
756 timer@15 {
757 compatible = "st,stm32h7-timer-trigger";
758 reg = <15>;
759 status = "disabled";
760 };
761 };
762
763 timers17: timer@44008000 {
764 #address-cells = <1>;
765 #size-cells = <0>;
766 compatible = "st,stm32-timers";
767 reg = <0x44008000 0x400>;
768 clocks = <&rcc TIM17_K>;
769 clock-names = "int";
770 dmas = <&dmamux1 111 0x400 0x1>,
771 <&dmamux1 112 0x400 0x1>;
772 dma-names = "ch1", "up";
773 status = "disabled";
774
775 pwm {
776 compatible = "st,stm32-pwm";
777 #pwm-cells = <3>;
778 status = "disabled";
779 };
780
781 timer@16 {
782 compatible = "st,stm32h7-timer-trigger";
783 reg = <16>;
784 status = "disabled";
785 };
786 };
787
788 spi5: spi@44009000 {
789 #address-cells = <1>;
790 #size-cells = <0>;
791 compatible = "st,stm32h7-spi";
792 reg = <0x44009000 0x400>;
793 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&rcc SPI5_K>;
795 resets = <&rcc SPI5_R>;
796 dmas = <&dmamux1 85 0x400 0x05>,
797 <&dmamux1 86 0x400 0x05>;
798 dma-names = "rx", "tx";
799 status = "disabled";
800 };
801
802 sai1: sai@4400a000 {
803 compatible = "st,stm32h7-sai";
804 #address-cells = <1>;
805 #size-cells = <1>;
806 ranges = <0 0x4400a000 0x400>;
807 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
808 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
809 resets = <&rcc SAI1_R>;
810 status = "disabled";
811
812 sai1a: audio-controller@4400a004 {
813 #sound-dai-cells = <0>;
814
815 compatible = "st,stm32-sai-sub-a";
816 reg = <0x4 0x1c>;
817 clocks = <&rcc SAI1_K>;
818 clock-names = "sai_ck";
819 dmas = <&dmamux1 87 0x400 0x01>;
820 status = "disabled";
821 };
822
823 sai1b: audio-controller@4400a024 {
824 #sound-dai-cells = <0>;
825 compatible = "st,stm32-sai-sub-b";
826 reg = <0x24 0x1c>;
827 clocks = <&rcc SAI1_K>;
828 clock-names = "sai_ck";
829 dmas = <&dmamux1 88 0x400 0x01>;
830 status = "disabled";
831 };
832 };
833
834 sai2: sai@4400b000 {
835 compatible = "st,stm32h7-sai";
836 #address-cells = <1>;
837 #size-cells = <1>;
838 ranges = <0 0x4400b000 0x400>;
839 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
840 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
841 resets = <&rcc SAI2_R>;
842 status = "disabled";
843
844 sai2a: audio-controller@4400b004 {
845 #sound-dai-cells = <0>;
846 compatible = "st,stm32-sai-sub-a";
847 reg = <0x4 0x1c>;
848 clocks = <&rcc SAI2_K>;
849 clock-names = "sai_ck";
850 dmas = <&dmamux1 89 0x400 0x01>;
851 status = "disabled";
852 };
853
854 sai2b: audio-controller@4400b024 {
855 #sound-dai-cells = <0>;
856 compatible = "st,stm32-sai-sub-b";
857 reg = <0x24 0x1c>;
858 clocks = <&rcc SAI2_K>;
859 clock-names = "sai_ck";
860 dmas = <&dmamux1 90 0x400 0x01>;
861 status = "disabled";
862 };
863 };
864
865 sai3: sai@4400c000 {
866 compatible = "st,stm32h7-sai";
867 #address-cells = <1>;
868 #size-cells = <1>;
869 ranges = <0 0x4400c000 0x400>;
870 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
871 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
872 resets = <&rcc SAI3_R>;
873 status = "disabled";
874
875 sai3a: audio-controller@4400c004 {
876 #sound-dai-cells = <0>;
877 compatible = "st,stm32-sai-sub-a";
878 reg = <0x04 0x1c>;
879 clocks = <&rcc SAI3_K>;
880 clock-names = "sai_ck";
881 dmas = <&dmamux1 113 0x400 0x01>;
882 status = "disabled";
883 };
884
885 sai3b: audio-controller@4400c024 {
886 #sound-dai-cells = <0>;
887 compatible = "st,stm32-sai-sub-b";
888 reg = <0x24 0x1c>;
889 clocks = <&rcc SAI3_K>;
890 clock-names = "sai_ck";
891 dmas = <&dmamux1 114 0x400 0x01>;
892 status = "disabled";
893 };
894 };
895
896 dfsdm: dfsdm@4400d000 {
897 compatible = "st,stm32mp1-dfsdm";
898 reg = <0x4400d000 0x800>;
899 clocks = <&rcc DFSDM_K>;
900 clock-names = "dfsdm";
901 #address-cells = <1>;
902 #size-cells = <0>;
903 status = "disabled";
904
905 dfsdm0: filter@0 {
906 compatible = "st,stm32-dfsdm-adc";
907 #io-channel-cells = <1>;
908 reg = <0>;
909 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
910 dmas = <&dmamux1 101 0x400 0x01>;
911 dma-names = "rx";
912 status = "disabled";
913 };
914
915 dfsdm1: filter@1 {
916 compatible = "st,stm32-dfsdm-adc";
917 #io-channel-cells = <1>;
918 reg = <1>;
919 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
920 dmas = <&dmamux1 102 0x400 0x01>;
921 dma-names = "rx";
922 status = "disabled";
923 };
924
925 dfsdm2: filter@2 {
926 compatible = "st,stm32-dfsdm-adc";
927 #io-channel-cells = <1>;
928 reg = <2>;
929 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
930 dmas = <&dmamux1 103 0x400 0x01>;
931 dma-names = "rx";
932 status = "disabled";
933 };
934
935 dfsdm3: filter@3 {
936 compatible = "st,stm32-dfsdm-adc";
937 #io-channel-cells = <1>;
938 reg = <3>;
939 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
940 dmas = <&dmamux1 104 0x400 0x01>;
941 dma-names = "rx";
942 status = "disabled";
943 };
944
945 dfsdm4: filter@4 {
946 compatible = "st,stm32-dfsdm-adc";
947 #io-channel-cells = <1>;
948 reg = <4>;
949 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
950 dmas = <&dmamux1 91 0x400 0x01>;
951 dma-names = "rx";
952 status = "disabled";
953 };
954
955 dfsdm5: filter@5 {
956 compatible = "st,stm32-dfsdm-adc";
957 #io-channel-cells = <1>;
958 reg = <5>;
959 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
960 dmas = <&dmamux1 92 0x400 0x01>;
961 dma-names = "rx";
962 status = "disabled";
963 };
964 };
965
966 dma1: dma-controller@48000000 {
967 compatible = "st,stm32-dma";
968 reg = <0x48000000 0x400>;
969 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
977 clocks = <&rcc DMA1>;
978 resets = <&rcc DMA1_R>;
979 #dma-cells = <4>;
980 st,mem2mem;
981 dma-requests = <8>;
982 };
983
984 dma2: dma-controller@48001000 {
985 compatible = "st,stm32-dma";
986 reg = <0x48001000 0x400>;
987 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&rcc DMA2>;
996 resets = <&rcc DMA2_R>;
997 #dma-cells = <4>;
998 st,mem2mem;
999 dma-requests = <8>;
1000 };
1001
1002 dmamux1: dma-router@48002000 {
1003 compatible = "st,stm32h7-dmamux";
1004 reg = <0x48002000 0x40>;
1005 #dma-cells = <3>;
1006 dma-requests = <128>;
1007 dma-masters = <&dma1 &dma2>;
1008 dma-channels = <16>;
1009 clocks = <&rcc DMAMUX>;
1010 resets = <&rcc DMAMUX_R>;
1011 };
1012
1013 adc: adc@48003000 {
1014 compatible = "st,stm32mp1-adc-core";
1015 reg = <0x48003000 0x400>;
1016 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1019 clock-names = "bus", "adc";
1020 interrupt-controller;
1021 st,syscfg = <&syscfg>;
1022 #interrupt-cells = <1>;
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1025 status = "disabled";
1026
1027 adc1: adc@0 {
1028 compatible = "st,stm32mp1-adc";
1029 #io-channel-cells = <1>;
1030 reg = <0x0>;
1031 interrupt-parent = <&adc>;
1032 interrupts = <0>;
1033 dmas = <&dmamux1 9 0x400 0x01>;
1034 dma-names = "rx";
1035 status = "disabled";
1036 };
1037
1038 adc2: adc@100 {
1039 compatible = "st,stm32mp1-adc";
1040 #io-channel-cells = <1>;
1041 reg = <0x100>;
1042 interrupt-parent = <&adc>;
1043 interrupts = <1>;
1044 dmas = <&dmamux1 10 0x400 0x01>;
1045 dma-names = "rx";
1046 status = "disabled";
1047 };
1048 };
1049
1050 sdmmc3: sdmmc@48004000 {
1051 compatible = "arm,pl18x", "arm,primecell";
1052 arm,primecell-periphid = <0x00253180>;
1053 reg = <0x48004000 0x400>;
1054 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1055 interrupt-names = "cmd_irq";
1056 clocks = <&rcc SDMMC3_K>;
1057 clock-names = "apb_pclk";
1058 resets = <&rcc SDMMC3_R>;
1059 cap-sd-highspeed;
1060 cap-mmc-highspeed;
1061 max-frequency = <120000000>;
1062 status = "disabled";
1063 };
1064
1065 usbotg_hs: usb-otg@49000000 {
1066 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1067 reg = <0x49000000 0x10000>;
1068 clocks = <&rcc USBO_K>;
1069 clock-names = "otg";
1070 resets = <&rcc USBO_R>;
1071 reset-names = "dwc2";
1072 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1073 g-rx-fifo-size = <512>;
1074 g-np-tx-fifo-size = <32>;
1075 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1076 dr_mode = "otg";
1077 usb33d-supply = <&usb33>;
1078 status = "disabled";
1079 };
1080
1081 ipcc: mailbox@4c001000 {
1082 compatible = "st,stm32mp1-ipcc";
1083 #mbox-cells = <1>;
1084 reg = <0x4c001000 0x400>;
1085 st,proc-id = <0>;
1086 interrupts-extended =
1087 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1088 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1089 <&exti 61 1>;
1090 interrupt-names = "rx", "tx", "wakeup";
1091 clocks = <&rcc IPCC>;
1092 wakeup-source;
1093 status = "disabled";
1094 };
1095
1096 dcmi: dcmi@4c006000 {
1097 compatible = "st,stm32-dcmi";
1098 reg = <0x4c006000 0x400>;
1099 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1100 resets = <&rcc CAMITF_R>;
1101 clocks = <&rcc DCMI>;
1102 clock-names = "mclk";
1103 dmas = <&dmamux1 75 0x400 0x01>;
1104 dma-names = "tx";
1105 status = "disabled";
1106 };
1107
1108 rcc: rcc@50000000 {
1109 compatible = "st,stm32mp1-rcc", "syscon";
1110 reg = <0x50000000 0x1000>;
1111 #clock-cells = <1>;
1112 #reset-cells = <1>;
1113 };
1114
1115 pwr_regulators: pwr@50001000 {
1116 compatible = "st,stm32mp1,pwr-reg";
1117 reg = <0x50001000 0x10>;
1118
1119 reg11: reg11 {
1120 regulator-name = "reg11";
1121 regulator-min-microvolt = <1100000>;
1122 regulator-max-microvolt = <1100000>;
1123 };
1124
1125 reg18: reg18 {
1126 regulator-name = "reg18";
1127 regulator-min-microvolt = <1800000>;
1128 regulator-max-microvolt = <1800000>;
1129 };
1130
1131 usb33: usb33 {
1132 regulator-name = "usb33";
1133 regulator-min-microvolt = <3300000>;
1134 regulator-max-microvolt = <3300000>;
1135 };
1136 };
1137
1138 pwr_mcu: pwr_mcu@50001014 {
1139 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1140 reg = <0x50001014 0x4>;
1141 };
1142
1143 exti: interrupt-controller@5000d000 {
1144 compatible = "st,stm32mp1-exti", "syscon";
1145 interrupt-controller;
1146 #interrupt-cells = <2>;
1147 reg = <0x5000d000 0x400>;
1148 };
1149
1150 syscfg: syscon@50020000 {
1151 compatible = "st,stm32mp157-syscfg", "syscon";
1152 reg = <0x50020000 0x400>;
1153 clocks = <&rcc SYSCFG>;
1154 };
1155
1156 lptimer2: timer@50021000 {
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1159 compatible = "st,stm32-lptimer";
1160 reg = <0x50021000 0x400>;
1161 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&rcc LPTIM2_K>;
1163 clock-names = "mux";
1164 wakeup-source;
1165 status = "disabled";
1166
1167 pwm {
1168 compatible = "st,stm32-pwm-lp";
1169 #pwm-cells = <3>;
1170 status = "disabled";
1171 };
1172
1173 trigger@1 {
1174 compatible = "st,stm32-lptimer-trigger";
1175 reg = <1>;
1176 status = "disabled";
1177 };
1178
1179 counter {
1180 compatible = "st,stm32-lptimer-counter";
1181 status = "disabled";
1182 };
1183 };
1184
1185 lptimer3: timer@50022000 {
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 compatible = "st,stm32-lptimer";
1189 reg = <0x50022000 0x400>;
1190 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&rcc LPTIM3_K>;
1192 clock-names = "mux";
1193 wakeup-source;
1194 status = "disabled";
1195
1196 pwm {
1197 compatible = "st,stm32-pwm-lp";
1198 #pwm-cells = <3>;
1199 status = "disabled";
1200 };
1201
1202 trigger@2 {
1203 compatible = "st,stm32-lptimer-trigger";
1204 reg = <2>;
1205 status = "disabled";
1206 };
1207 };
1208
1209 lptimer4: timer@50023000 {
1210 compatible = "st,stm32-lptimer";
1211 reg = <0x50023000 0x400>;
1212 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&rcc LPTIM4_K>;
1214 clock-names = "mux";
1215 wakeup-source;
1216 status = "disabled";
1217
1218 pwm {
1219 compatible = "st,stm32-pwm-lp";
1220 #pwm-cells = <3>;
1221 status = "disabled";
1222 };
1223 };
1224
1225 lptimer5: timer@50024000 {
1226 compatible = "st,stm32-lptimer";
1227 reg = <0x50024000 0x400>;
1228 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1229 clocks = <&rcc LPTIM5_K>;
1230 clock-names = "mux";
1231 wakeup-source;
1232 status = "disabled";
1233
1234 pwm {
1235 compatible = "st,stm32-pwm-lp";
1236 #pwm-cells = <3>;
1237 status = "disabled";
1238 };
1239 };
1240
1241 vrefbuf: vrefbuf@50025000 {
1242 compatible = "st,stm32-vrefbuf";
1243 reg = <0x50025000 0x8>;
1244 regulator-min-microvolt = <1500000>;
1245 regulator-max-microvolt = <2500000>;
1246 clocks = <&rcc VREF>;
1247 status = "disabled";
1248 };
1249
1250 sai4: sai@50027000 {
1251 compatible = "st,stm32h7-sai";
1252 #address-cells = <1>;
1253 #size-cells = <1>;
1254 ranges = <0 0x50027000 0x400>;
1255 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1256 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1257 resets = <&rcc SAI4_R>;
1258 status = "disabled";
1259
1260 sai4a: audio-controller@50027004 {
1261 #sound-dai-cells = <0>;
1262 compatible = "st,stm32-sai-sub-a";
1263 reg = <0x04 0x1c>;
1264 clocks = <&rcc SAI4_K>;
1265 clock-names = "sai_ck";
1266 dmas = <&dmamux1 99 0x400 0x01>;
1267 status = "disabled";
1268 };
1269
1270 sai4b: audio-controller@50027024 {
1271 #sound-dai-cells = <0>;
1272 compatible = "st,stm32-sai-sub-b";
1273 reg = <0x24 0x1c>;
1274 clocks = <&rcc SAI4_K>;
1275 clock-names = "sai_ck";
1276 dmas = <&dmamux1 100 0x400 0x01>;
1277 status = "disabled";
1278 };
1279 };
1280
1281 dts: thermal@50028000 {
1282 compatible = "st,stm32-thermal";
1283 reg = <0x50028000 0x100>;
1284 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1285 clocks = <&rcc TMPSENS>;
1286 clock-names = "pclk";
1287 #thermal-sensor-cells = <0>;
1288 status = "disabled";
1289 };
1290
1291 hash1: hash@54002000 {
1292 compatible = "st,stm32f756-hash";
1293 reg = <0x54002000 0x400>;
1294 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1295 clocks = <&rcc HASH1>;
1296 resets = <&rcc HASH1_R>;
1297 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1298 dma-names = "in";
1299 dma-maxburst = <2>;
1300 status = "disabled";
1301 };
1302
1303 rng1: rng@54003000 {
1304 compatible = "st,stm32-rng";
1305 reg = <0x54003000 0x400>;
1306 clocks = <&rcc RNG1_K>;
1307 resets = <&rcc RNG1_R>;
1308 status = "disabled";
1309 };
1310
1311 mdma1: dma-controller@58000000 {
1312 compatible = "st,stm32h7-mdma";
1313 reg = <0x58000000 0x1000>;
1314 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1315 clocks = <&rcc MDMA>;
1316 resets = <&rcc MDMA_R>;
1317 #dma-cells = <5>;
1318 dma-channels = <32>;
1319 dma-requests = <48>;
1320 };
1321
1322 fmc: memory-controller@58002000 {
1323 #address-cells = <2>;
1324 #size-cells = <1>;
1325 compatible = "st,stm32mp1-fmc2-ebi";
1326 reg = <0x58002000 0x1000>;
1327 clocks = <&rcc FMC_K>;
1328 resets = <&rcc FMC_R>;
1329 status = "disabled";
1330
1331 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1332 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1333 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1334 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1335 <4 0 0x80000000 0x10000000>; /* NAND */
1336
1337 nand-controller@4,0 {
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1340 compatible = "st,stm32mp1-fmc2-nfc";
1341 reg = <4 0x00000000 0x1000>,
1342 <4 0x08010000 0x1000>,
1343 <4 0x08020000 0x1000>,
1344 <4 0x01000000 0x1000>,
1345 <4 0x09010000 0x1000>,
1346 <4 0x09020000 0x1000>;
1347 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1348 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1349 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1350 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1351 dma-names = "tx", "rx", "ecc";
1352 status = "disabled";
1353 };
1354 };
1355
1356 qspi: spi@58003000 {
1357 compatible = "st,stm32f469-qspi";
1358 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1359 reg-names = "qspi", "qspi_mm";
1360 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1361 dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
1362 <&mdma1 22 0x2 0x100008 0x0 0x0>;
1363 dma-names = "tx", "rx";
1364 clocks = <&rcc QSPI_K>;
1365 resets = <&rcc QSPI_R>;
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1368 status = "disabled";
1369 };
1370
1371 sdmmc1: sdmmc@58005000 {
1372 compatible = "arm,pl18x", "arm,primecell";
1373 arm,primecell-periphid = <0x00253180>;
1374 reg = <0x58005000 0x1000>;
1375 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1376 interrupt-names = "cmd_irq";
1377 clocks = <&rcc SDMMC1_K>;
1378 clock-names = "apb_pclk";
1379 resets = <&rcc SDMMC1_R>;
1380 cap-sd-highspeed;
1381 cap-mmc-highspeed;
1382 max-frequency = <120000000>;
1383 status = "disabled";
1384 };
1385
1386 sdmmc2: sdmmc@58007000 {
1387 compatible = "arm,pl18x", "arm,primecell";
1388 arm,primecell-periphid = <0x00253180>;
1389 reg = <0x58007000 0x1000>;
1390 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1391 interrupt-names = "cmd_irq";
1392 clocks = <&rcc SDMMC2_K>;
1393 clock-names = "apb_pclk";
1394 resets = <&rcc SDMMC2_R>;
1395 cap-sd-highspeed;
1396 cap-mmc-highspeed;
1397 max-frequency = <120000000>;
1398 status = "disabled";
1399 };
1400
1401 crc1: crc@58009000 {
1402 compatible = "st,stm32f7-crc";
1403 reg = <0x58009000 0x400>;
1404 clocks = <&rcc CRC1>;
1405 status = "disabled";
1406 };
1407
1408 stmmac_axi_config_0: stmmac-axi-config {
1409 snps,wr_osr_lmt = <0x7>;
1410 snps,rd_osr_lmt = <0x7>;
1411 snps,blen = <0 0 0 0 16 8 4>;
1412 };
1413
1414 ethernet0: ethernet@5800a000 {
1415 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1416 reg = <0x5800a000 0x2000>;
1417 reg-names = "stmmaceth";
1418 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1419 interrupt-names = "macirq";
1420 clock-names = "stmmaceth",
1421 "mac-clk-tx",
1422 "mac-clk-rx",
1423 "eth-ck",
1424 "ethstp";
1425 clocks = <&rcc ETHMAC>,
1426 <&rcc ETHTX>,
1427 <&rcc ETHRX>,
1428 <&rcc ETHCK_K>,
1429 <&rcc ETHSTP>;
1430 st,syscon = <&syscfg 0x4>;
1431 snps,mixed-burst;
1432 snps,pbl = <2>;
1433 snps,en-tx-lpi-clockgating;
1434 snps,axi-config = <&stmmac_axi_config_0>;
1435 snps,tso;
1436 status = "disabled";
1437 };
1438
1439 usbh_ohci: usb@5800c000 {
1440 compatible = "generic-ohci";
1441 reg = <0x5800c000 0x1000>;
1442 clocks = <&rcc USBH>;
1443 resets = <&rcc USBH_R>;
1444 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1445 status = "disabled";
1446 };
1447
1448 usbh_ehci: usb@5800d000 {
1449 compatible = "generic-ehci";
1450 reg = <0x5800d000 0x1000>;
1451 clocks = <&rcc USBH>;
1452 resets = <&rcc USBH_R>;
1453 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1454 companion = <&usbh_ohci>;
1455 status = "disabled";
1456 };
1457
1458 ltdc: display-controller@5a001000 {
1459 compatible = "st,stm32-ltdc";
1460 reg = <0x5a001000 0x400>;
1461 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&rcc LTDC_PX>;
1464 clock-names = "lcd";
1465 resets = <&rcc LTDC_R>;
1466 status = "disabled";
1467
1468 port {
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1471 };
1472 };
1473
1474 iwdg2: watchdog@5a002000 {
1475 compatible = "st,stm32mp1-iwdg";
1476 reg = <0x5a002000 0x400>;
1477 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1478 clock-names = "pclk", "lsi";
1479 status = "disabled";
1480 };
1481
1482 usbphyc: usbphyc@5a006000 {
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485 compatible = "st,stm32mp1-usbphyc";
1486 reg = <0x5a006000 0x1000>;
1487 clocks = <&rcc USBPHY_K>;
1488 resets = <&rcc USBPHY_R>;
1489 status = "disabled";
1490
1491 usbphyc_port0: usb-phy@0 {
1492 #phy-cells = <0>;
1493 reg = <0>;
1494 };
1495
1496 usbphyc_port1: usb-phy@1 {
1497 #phy-cells = <1>;
1498 reg = <1>;
1499 };
1500 };
1501
1502 usart1: serial@5c000000 {
1503 compatible = "st,stm32h7-uart";
1504 reg = <0x5c000000 0x400>;
1505 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1506 clocks = <&rcc USART1_K>;
1507 status = "disabled";
1508 };
1509
1510 spi6: spi@5c001000 {
1511 #address-cells = <1>;
1512 #size-cells = <0>;
1513 compatible = "st,stm32h7-spi";
1514 reg = <0x5c001000 0x400>;
1515 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1516 clocks = <&rcc SPI6_K>;
1517 resets = <&rcc SPI6_R>;
1518 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1519 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1520 dma-names = "rx", "tx";
1521 status = "disabled";
1522 };
1523
1524 i2c4: i2c@5c002000 {
1525 compatible = "st,stm32mp15-i2c";
1526 reg = <0x5c002000 0x400>;
1527 interrupt-names = "event", "error";
1528 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1530 clocks = <&rcc I2C4_K>;
1531 resets = <&rcc I2C4_R>;
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1534 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1535 wakeup-source;
1536 status = "disabled";
1537 };
1538
1539 rtc: rtc@5c004000 {
1540 compatible = "st,stm32mp1-rtc";
1541 reg = <0x5c004000 0x400>;
1542 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1543 clock-names = "pclk", "rtc_ck";
1544 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1545 status = "disabled";
1546 };
1547
1548 bsec: efuse@5c005000 {
1549 compatible = "st,stm32mp15-bsec";
1550 reg = <0x5c005000 0x400>;
1551 #address-cells = <1>;
1552 #size-cells = <1>;
1553 ts_cal1: calib@5c {
1554 reg = <0x5c 0x2>;
1555 };
1556 ts_cal2: calib@5e {
1557 reg = <0x5e 0x2>;
1558 };
1559 };
1560
1561 i2c6: i2c@5c009000 {
1562 compatible = "st,stm32mp15-i2c";
1563 reg = <0x5c009000 0x400>;
1564 interrupt-names = "event", "error";
1565 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1566 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1567 clocks = <&rcc I2C6_K>;
1568 resets = <&rcc I2C6_R>;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1572 wakeup-source;
1573 status = "disabled";
1574 };
1575
1576 tamp: tamp@5c00a000 {
1577 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1578 reg = <0x5c00a000 0x400>;
1579 };
1580
1581 /*
1582 * Break node order to solve dependency probe issue between
1583 * pinctrl and exti.
1584 */
1585 pinctrl: pin-controller@50002000 {
1586 #address-cells = <1>;
1587 #size-cells = <1>;
1588 compatible = "st,stm32mp157-pinctrl";
1589 ranges = <0 0x50002000 0xa400>;
1590 interrupt-parent = <&exti>;
1591 st,syscfg = <&exti 0x60 0xff>;
1592 pins-are-numbered;
1593
1594 gpioa: gpio@50002000 {
1595 gpio-controller;
1596 #gpio-cells = <2>;
1597 interrupt-controller;
1598 #interrupt-cells = <2>;
1599 reg = <0x0 0x400>;
1600 clocks = <&rcc GPIOA>;
1601 st,bank-name = "GPIOA";
1602 status = "disabled";
1603 };
1604
1605 gpiob: gpio@50003000 {
1606 gpio-controller;
1607 #gpio-cells = <2>;
1608 interrupt-controller;
1609 #interrupt-cells = <2>;
1610 reg = <0x1000 0x400>;
1611 clocks = <&rcc GPIOB>;
1612 st,bank-name = "GPIOB";
1613 status = "disabled";
1614 };
1615
1616 gpioc: gpio@50004000 {
1617 gpio-controller;
1618 #gpio-cells = <2>;
1619 interrupt-controller;
1620 #interrupt-cells = <2>;
1621 reg = <0x2000 0x400>;
1622 clocks = <&rcc GPIOC>;
1623 st,bank-name = "GPIOC";
1624 status = "disabled";
1625 };
1626
1627 gpiod: gpio@50005000 {
1628 gpio-controller;
1629 #gpio-cells = <2>;
1630 interrupt-controller;
1631 #interrupt-cells = <2>;
1632 reg = <0x3000 0x400>;
1633 clocks = <&rcc GPIOD>;
1634 st,bank-name = "GPIOD";
1635 status = "disabled";
1636 };
1637
1638 gpioe: gpio@50006000 {
1639 gpio-controller;
1640 #gpio-cells = <2>;
1641 interrupt-controller;
1642 #interrupt-cells = <2>;
1643 reg = <0x4000 0x400>;
1644 clocks = <&rcc GPIOE>;
1645 st,bank-name = "GPIOE";
1646 status = "disabled";
1647 };
1648
1649 gpiof: gpio@50007000 {
1650 gpio-controller;
1651 #gpio-cells = <2>;
1652 interrupt-controller;
1653 #interrupt-cells = <2>;
1654 reg = <0x5000 0x400>;
1655 clocks = <&rcc GPIOF>;
1656 st,bank-name = "GPIOF";
1657 status = "disabled";
1658 };
1659
1660 gpiog: gpio@50008000 {
1661 gpio-controller;
1662 #gpio-cells = <2>;
1663 interrupt-controller;
1664 #interrupt-cells = <2>;
1665 reg = <0x6000 0x400>;
1666 clocks = <&rcc GPIOG>;
1667 st,bank-name = "GPIOG";
1668 status = "disabled";
1669 };
1670
1671 gpioh: gpio@50009000 {
1672 gpio-controller;
1673 #gpio-cells = <2>;
1674 interrupt-controller;
1675 #interrupt-cells = <2>;
1676 reg = <0x7000 0x400>;
1677 clocks = <&rcc GPIOH>;
1678 st,bank-name = "GPIOH";
1679 status = "disabled";
1680 };
1681
1682 gpioi: gpio@5000a000 {
1683 gpio-controller;
1684 #gpio-cells = <2>;
1685 interrupt-controller;
1686 #interrupt-cells = <2>;
1687 reg = <0x8000 0x400>;
1688 clocks = <&rcc GPIOI>;
1689 st,bank-name = "GPIOI";
1690 status = "disabled";
1691 };
1692
1693 gpioj: gpio@5000b000 {
1694 gpio-controller;
1695 #gpio-cells = <2>;
1696 interrupt-controller;
1697 #interrupt-cells = <2>;
1698 reg = <0x9000 0x400>;
1699 clocks = <&rcc GPIOJ>;
1700 st,bank-name = "GPIOJ";
1701 status = "disabled";
1702 };
1703
1704 gpiok: gpio@5000c000 {
1705 gpio-controller;
1706 #gpio-cells = <2>;
1707 interrupt-controller;
1708 #interrupt-cells = <2>;
1709 reg = <0xa000 0x400>;
1710 clocks = <&rcc GPIOK>;
1711 st,bank-name = "GPIOK";
1712 status = "disabled";
1713 };
1714 };
1715
1716 pinctrl_z: pin-controller-z@54004000 {
1717 #address-cells = <1>;
1718 #size-cells = <1>;
1719 compatible = "st,stm32mp157-z-pinctrl";
1720 ranges = <0 0x54004000 0x400>;
1721 pins-are-numbered;
1722 interrupt-parent = <&exti>;
1723 st,syscfg = <&exti 0x60 0xff>;
1724
1725 gpioz: gpio@54004000 {
1726 gpio-controller;
1727 #gpio-cells = <2>;
1728 interrupt-controller;
1729 #interrupt-cells = <2>;
1730 reg = <0 0x400>;
1731 clocks = <&rcc GPIOZ>;
1732 st,bank-name = "GPIOZ";
1733 st,bank-ioport = <11>;
1734 status = "disabled";
1735 };
1736 };
1737 };
1738
1739 mlahb: ahb {
1740 compatible = "st,mlahb", "simple-bus";
1741 #address-cells = <1>;
1742 #size-cells = <1>;
1743 ranges;
1744 dma-ranges = <0x00000000 0x38000000 0x10000>,
1745 <0x10000000 0x10000000 0x60000>,
1746 <0x30000000 0x30000000 0x60000>;
1747
1748 m4_rproc: m4@10000000 {
1749 compatible = "st,stm32mp1-m4";
1750 reg = <0x10000000 0x40000>,
1751 <0x30000000 0x40000>,
1752 <0x38000000 0x10000>;
1753 resets = <&rcc MCU_R>;
1754 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1755 st,syscfg-tz = <&rcc 0x000 0x1>;
1756 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1757 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1758 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1759 status = "disabled";
1760 };
1761 };
1762};