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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QMP PHY controller
9
10maintainers:
11 - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14 QMP phy controller supports physical layer functionality for a number of
15 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
16
17properties:
18 compatible:
19 enum:
20 - qcom,ipq8074-qmp-pcie-phy
21 - qcom,ipq8074-qmp-usb3-phy
22 - qcom,msm8996-qmp-pcie-phy
23 - qcom,msm8996-qmp-ufs-phy
24 - qcom,msm8996-qmp-usb3-phy
25 - qcom,msm8998-qmp-pcie-phy
26 - qcom,msm8998-qmp-ufs-phy
27 - qcom,msm8998-qmp-usb3-phy
28 - qcom,sdm845-qhp-pcie-phy
29 - qcom,sdm845-qmp-pcie-phy
30 - qcom,sdm845-qmp-ufs-phy
31 - qcom,sdm845-qmp-usb3-uni-phy
32 - qcom,sm8150-qmp-ufs-phy
33 - qcom,sm8250-qmp-ufs-phy
34 - qcom,sm8250-qmp-gen3x1-pcie-phy
35 - qcom,sm8250-qmp-gen3x2-pcie-phy
36 - qcom,sm8250-qmp-modem-pcie-phy
37
38 reg:
39 items:
40 - description: Address and length of PHY's common serdes block.
41
42 "#clock-cells":
43 enum: [ 1, 2 ]
44
45 "#address-cells":
46 enum: [ 1, 2 ]
47
48 "#size-cells":
49 enum: [ 1, 2 ]
50
51 ranges: true
52
53 clocks:
54 minItems: 1
55 maxItems: 4
56
57 clock-names:
58 minItems: 1
59 maxItems: 4
60
61 resets:
62 minItems: 1
63 maxItems: 3
64
65 reset-names:
66 minItems: 1
67 maxItems: 3
68
69 vdda-phy-supply:
70 description:
71 Phandle to a regulator supply to PHY core block.
72
73 vdda-pll-supply:
74 description:
75 Phandle to 1.8V regulator supply to PHY refclk pll block.
76
77 vddp-ref-clk-supply:
78 description:
79 Phandle to a regulator supply to any specific refclk pll block.
80
81#Required nodes:
82patternProperties:
83 "^phy@[0-9a-f]+$":
84 type: object
85 description:
86 Each device node of QMP phy is required to have as many child nodes as
87 the number of lanes the PHY has.
88
89required:
90 - compatible
91 - reg
92 - "#clock-cells"
93 - "#address-cells"
94 - "#size-cells"
95 - ranges
96 - clocks
97 - clock-names
98 - resets
99 - reset-names
100 - vdda-phy-supply
101 - vdda-pll-supply
102
103additionalProperties: false
104
105allOf:
106 - if:
107 properties:
108 compatible:
109 contains:
110 enum:
111 - qcom,sdm845-qmp-usb3-uni-phy
112 then:
113 properties:
114 clocks:
115 items:
116 - description: Phy aux clock.
117 - description: Phy config clock.
118 - description: 19.2 MHz ref clk.
119 - description: Phy common block aux clock.
120 clock-names:
121 items:
122 - const: aux
123 - const: cfg_ahb
124 - const: ref
125 - const: com_aux
126 resets:
127 items:
128 - description: reset of phy block.
129 - description: phy common block reset.
130 reset-names:
131 items:
132 - const: phy
133 - const: common
134 - if:
135 properties:
136 compatible:
137 contains:
138 enum:
139 - qcom,msm8996-qmp-pcie-phy
140 then:
141 properties:
142 clocks:
143 items:
144 - description: Phy aux clock.
145 - description: Phy config clock.
146 - description: 19.2 MHz ref clk.
147 clock-names:
148 items:
149 - const: aux
150 - const: cfg_ahb
151 - const: ref
152 resets:
153 items:
154 - description: reset of phy block.
155 - description: phy common block reset.
156 - description: phy's ahb cfg block reset.
157 reset-names:
158 items:
159 - const: phy
160 - const: common
161 - const: cfg
162 - if:
163 properties:
164 compatible:
165 contains:
166 enum:
167 - qcom,ipq8074-qmp-usb3-phy
168 - qcom,msm8996-qmp-usb3-phy
169 - qcom,msm8998-qmp-pcie-phy
170 - qcom,msm8998-qmp-usb3-phy
171 then:
172 properties:
173 clocks:
174 items:
175 - description: Phy aux clock.
176 - description: Phy config clock.
177 - description: 19.2 MHz ref clk.
178 clock-names:
179 items:
180 - const: aux
181 - const: cfg_ahb
182 - const: ref
183 resets:
184 items:
185 - description: reset of phy block.
186 - description: phy common block reset.
187 reset-names:
188 items:
189 - const: phy
190 - const: common
191 - if:
192 properties:
193 compatible:
194 contains:
195 enum:
196 - qcom,msm8996-qmp-ufs-phy
197 then:
198 properties:
199 clocks:
200 items:
201 - description: 19.2 MHz ref clk.
202 clock-names:
203 items:
204 - const: ref
205 resets:
206 items:
207 - description: PHY reset in the UFS controller.
208 reset-names:
209 items:
210 - const: ufsphy
211 - if:
212 properties:
213 compatible:
214 contains:
215 enum:
216 - qcom,msm8998-qmp-ufs-phy
217 - qcom,sdm845-qmp-ufs-phy
218 - qcom,sm8150-qmp-ufs-phy
219 - qcom,sm8250-qmp-ufs-phy
220 then:
221 properties:
222 clocks:
223 items:
224 - description: 19.2 MHz ref clk.
225 - description: Phy reference aux clock.
226 clock-names:
227 items:
228 - const: ref
229 - const: ref_aux
230 resets:
231 items:
232 - description: PHY reset in the UFS controller.
233 reset-names:
234 items:
235 - const: ufsphy
236 - if:
237 properties:
238 compatible:
239 contains:
240 enum:
241 - qcom,ipq8074-qmp-pcie-phy
242 then:
243 properties:
244 clocks:
245 items:
246 - description: pipe clk.
247 clock-names:
248 items:
249 - const: pipe_clk
250 resets:
251 items:
252 - description: reset of phy block.
253 - description: phy common block reset.
254 reset-names:
255 items:
256 - const: phy
257 - const: common
258 - if:
259 properties:
260 compatible:
261 contains:
262 enum:
263 - qcom,sdm845-qhp-pcie-phy
264 - qcom,sdm845-qmp-pcie-phy
265 - qcom,sm8250-qmp-gen3x1-pcie-phy
266 - qcom,sm8250-qmp-gen3x2-pcie-phy
267 - qcom,sm8250-qmp-modem-pcie-phy
268 then:
269 properties:
270 clocks:
271 items:
272 - description: Phy aux clock.
273 - description: Phy config clock.
274 - description: 19.2 MHz ref clk.
275 - description: Phy refgen clk.
276 clock-names:
277 items:
278 - const: aux
279 - const: cfg_ahb
280 - const: ref
281 - const: refgen
282 resets:
283 items:
284 - description: reset of phy block.
285 reset-names:
286 items:
287 - const: phy
288
289examples:
290 - |
291 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
292 usb_2_qmpphy: phy-wrapper@88eb000 {
293 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
294 reg = <0x088eb000 0x18c>;
295 #clock-cells = <1>;
296 #address-cells = <1>;
297 #size-cells = <1>;
298 ranges = <0x0 0x088eb000 0x2000>;
299
300 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
301 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
302 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
303 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
304 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
305
306 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
307 <&gcc GCC_USB3_PHY_SEC_BCR>;
308 reset-names = "phy", "common";
309
310 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
311 vdda-pll-supply = <&vdda_usb2_ss_core>;
312
313 usb_2_ssphy: phy@200 {
314 reg = <0x200 0x128>,
315 <0x400 0x1fc>,
316 <0x800 0x218>,
317 <0x600 0x70>;
318 #clock-cells = <0>;
319 #phy-cells = <0>;
320 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
321 clock-names = "pipe0";
322 clock-output-names = "usb3_uni_phy_pipe_clk_src";
323 };
324 };