Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 MLX5_SET(typ, p, fld[idx], v); \
85} while (0)
86
87#define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 << __mlx5_dw_bit_off(typ, fld))); \
93} while (0)
94
95#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97__mlx5_mask(typ, fld))
98
99#define MLX5_GET_PR(typ, p, fld) ({ \
100 u32 ___t = MLX5_GET(typ, p, fld); \
101 pr_debug(#fld " = 0x%x\n", ___t); \
102 ___t; \
103})
104
105#define __MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108} while (0)
109
110#define MLX5_SET64(typ, p, fld, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld, v); \
113} while (0)
114
115#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 __MLX5_SET64(typ, p, fld[idx], v); \
118} while (0)
119
120#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET64_PR(typ, p, fld) ({ \
123 u64 ___t = MLX5_GET64(typ, p, fld); \
124 pr_debug(#fld " = 0x%llx\n", ___t); \
125 ___t; \
126})
127
128#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130__mlx5_mask16(typ, fld))
131
132#define MLX5_SET16(typ, p, fld, v) do { \
133 u16 _v = v; \
134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 << __mlx5_16_bit_off(typ, fld))); \
139} while (0)
140
141/* Big endian getters */
142#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 __mlx5_64_off(typ, fld)))
144
145#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
146 type_t tmp; \
147 switch (sizeof(tmp)) { \
148 case sizeof(u8): \
149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
150 break; \
151 case sizeof(u16): \
152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 break; \
154 case sizeof(u32): \
155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 break; \
157 case sizeof(u64): \
158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 break; \
160 } \
161 tmp; \
162 })
163
164enum mlx5_inline_modes {
165 MLX5_INLINE_MODE_NONE,
166 MLX5_INLINE_MODE_L2,
167 MLX5_INLINE_MODE_IP,
168 MLX5_INLINE_MODE_TCP_UDP,
169};
170
171enum {
172 MLX5_MAX_COMMANDS = 32,
173 MLX5_CMD_DATA_BLOCK_SIZE = 512,
174 MLX5_PCI_CMD_XPORT = 7,
175 MLX5_MKEY_BSF_OCTO_SIZE = 4,
176 MLX5_MAX_PSVS = 4,
177};
178
179enum {
180 MLX5_EXTENDED_UD_AV = 0x80000000,
181};
182
183enum {
184 MLX5_CQ_STATE_ARMED = 9,
185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
186 MLX5_CQ_STATE_FIRED = 0xa,
187};
188
189enum {
190 MLX5_STAT_RATE_OFFSET = 5,
191};
192
193enum {
194 MLX5_INLINE_SEG = 0x80000000,
195};
196
197enum {
198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199};
200
201enum {
202 MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 MLX5_MAX_LOG_PKEY_TABLE = 5,
204};
205
206enum {
207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208};
209
210enum {
211 MLX5_PFAULT_SUBTYPE_WQE = 0,
212 MLX5_PFAULT_SUBTYPE_RDMA = 1,
213};
214
215enum wqe_page_fault_type {
216 MLX5_WQE_PF_TYPE_RMP = 0,
217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
218 MLX5_WQE_PF_TYPE_RESP = 2,
219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
220};
221
222enum {
223 MLX5_PERM_LOCAL_READ = 1 << 2,
224 MLX5_PERM_LOCAL_WRITE = 1 << 3,
225 MLX5_PERM_REMOTE_READ = 1 << 4,
226 MLX5_PERM_REMOTE_WRITE = 1 << 5,
227 MLX5_PERM_ATOMIC = 1 << 6,
228 MLX5_PERM_UMR_EN = 1 << 7,
229};
230
231enum {
232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
237};
238
239enum {
240 MLX5_EN_RD = (u64)1,
241 MLX5_EN_WR = (u64)2
242};
243
244enum {
245 MLX5_ADAPTER_PAGE_SHIFT = 12,
246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
247};
248
249enum {
250 MLX5_BFREGS_PER_UAR = 4,
251 MLX5_MAX_UARS = 1 << 8,
252 MLX5_NON_FP_BFREGS_PER_UAR = 2,
253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
254 MLX5_NON_FP_BFREGS_PER_UAR,
255 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
256 MLX5_NON_FP_BFREGS_PER_UAR,
257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
259 MLX5_MIN_DYN_BFREGS = 512,
260 MLX5_MAX_DYN_BFREGS = 1024,
261};
262
263enum {
264 MLX5_MKEY_MASK_LEN = 1ull << 0,
265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
267 MLX5_MKEY_MASK_PD = 1ull << 7,
268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
271 MLX5_MKEY_MASK_KEY = 1ull << 13,
272 MLX5_MKEY_MASK_QPN = 1ull << 14,
273 MLX5_MKEY_MASK_LR = 1ull << 17,
274 MLX5_MKEY_MASK_LW = 1ull << 18,
275 MLX5_MKEY_MASK_RR = 1ull << 19,
276 MLX5_MKEY_MASK_RW = 1ull << 20,
277 MLX5_MKEY_MASK_A = 1ull << 21,
278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
279 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25,
280 MLX5_MKEY_MASK_FREE = 1ull << 29,
281 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47,
282};
283
284enum {
285 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
286
287 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
288 MLX5_UMR_CHECK_FREE = (2 << 5),
289
290 MLX5_UMR_INLINE = (1 << 7),
291};
292
293#define MLX5_UMR_MTT_ALIGNMENT 0x40
294#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
295#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
296
297#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
298
299enum {
300 MLX5_EVENT_QUEUE_TYPE_QP = 0,
301 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
302 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
303 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
304};
305
306/* mlx5 components can subscribe to any one of these events via
307 * mlx5_eq_notifier_register API.
308 */
309enum mlx5_event {
310 /* Special value to subscribe to any event */
311 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
312 /* HW events enum start: comp events are not subscribable */
313 MLX5_EVENT_TYPE_COMP = 0x0,
314 /* HW Async events enum start: subscribable events */
315 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
316 MLX5_EVENT_TYPE_COMM_EST = 0x02,
317 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
318 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
319 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
320
321 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
322 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
323 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
324 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
325 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
326 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
327
328 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
329 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
330 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
331 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
332 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
333 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18,
334 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
335 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
336 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
337 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
338
339 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
340 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
341
342 MLX5_EVENT_TYPE_CMD = 0x0a,
343 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
344
345 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
346 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
347
348 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
349
350 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
351 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
352
353 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
354 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
355
356 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
357
358 MLX5_EVENT_TYPE_MAX = 0x100,
359};
360
361enum {
362 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
363 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
364};
365
366enum {
367 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
368 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
369 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7,
370 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
371};
372
373enum {
374 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
375 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
376 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
377 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
378 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
379 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
380 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
381};
382
383enum {
384 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
385 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
386 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
387 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
388 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
389 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
390 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
391 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
392 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
393 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
394 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
395 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
396};
397
398enum {
399 MLX5_ROCE_VERSION_1 = 0,
400 MLX5_ROCE_VERSION_2 = 2,
401};
402
403enum {
404 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
405 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
406};
407
408enum {
409 MLX5_ROCE_L3_TYPE_IPV4 = 0,
410 MLX5_ROCE_L3_TYPE_IPV6 = 1,
411};
412
413enum {
414 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
415 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
416};
417
418enum {
419 MLX5_OPCODE_NOP = 0x00,
420 MLX5_OPCODE_SEND_INVAL = 0x01,
421 MLX5_OPCODE_RDMA_WRITE = 0x08,
422 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
423 MLX5_OPCODE_SEND = 0x0a,
424 MLX5_OPCODE_SEND_IMM = 0x0b,
425 MLX5_OPCODE_LSO = 0x0e,
426 MLX5_OPCODE_RDMA_READ = 0x10,
427 MLX5_OPCODE_ATOMIC_CS = 0x11,
428 MLX5_OPCODE_ATOMIC_FA = 0x12,
429 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
430 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
431 MLX5_OPCODE_BIND_MW = 0x18,
432 MLX5_OPCODE_CONFIG_CMD = 0x1f,
433 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
434
435 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
436 MLX5_RECV_OPCODE_SEND = 0x01,
437 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
438 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
439
440 MLX5_CQE_OPCODE_ERROR = 0x1e,
441 MLX5_CQE_OPCODE_RESIZE = 0x16,
442
443 MLX5_OPCODE_SET_PSV = 0x20,
444 MLX5_OPCODE_GET_PSV = 0x21,
445 MLX5_OPCODE_CHECK_PSV = 0x22,
446 MLX5_OPCODE_DUMP = 0x23,
447 MLX5_OPCODE_RGET_PSV = 0x26,
448 MLX5_OPCODE_RCHECK_PSV = 0x27,
449
450 MLX5_OPCODE_UMR = 0x25,
451
452};
453
454enum {
455 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
456 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
457};
458
459enum {
460 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
461 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
462};
463
464struct mlx5_wqe_tls_static_params_seg {
465 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
466};
467
468struct mlx5_wqe_tls_progress_params_seg {
469 __be32 tis_tir_num;
470 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
471};
472
473enum {
474 MLX5_SET_PORT_RESET_QKEY = 0,
475 MLX5_SET_PORT_GUID0 = 16,
476 MLX5_SET_PORT_NODE_GUID = 17,
477 MLX5_SET_PORT_SYS_GUID = 18,
478 MLX5_SET_PORT_GID_TABLE = 19,
479 MLX5_SET_PORT_PKEY_TABLE = 20,
480};
481
482enum {
483 MLX5_BW_NO_LIMIT = 0,
484 MLX5_100_MBPS_UNIT = 3,
485 MLX5_GBPS_UNIT = 4,
486};
487
488enum {
489 MLX5_MAX_PAGE_SHIFT = 31
490};
491
492enum {
493 MLX5_CAP_OFF_CMDIF_CSUM = 46,
494};
495
496enum {
497 /*
498 * Max wqe size for rdma read is 512 bytes, so this
499 * limits our max_sge_rd as the wqe needs to fit:
500 * - ctrl segment (16 bytes)
501 * - rdma segment (16 bytes)
502 * - scatter elements (16 bytes each)
503 */
504 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
505};
506
507enum mlx5_odp_transport_cap_bits {
508 MLX5_ODP_SUPPORT_SEND = 1 << 31,
509 MLX5_ODP_SUPPORT_RECV = 1 << 30,
510 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
511 MLX5_ODP_SUPPORT_READ = 1 << 28,
512};
513
514struct mlx5_odp_caps {
515 char reserved[0x10];
516 struct {
517 __be32 rc_odp_caps;
518 __be32 uc_odp_caps;
519 __be32 ud_odp_caps;
520 } per_transport_caps;
521 char reserved2[0xe4];
522};
523
524struct mlx5_cmd_layout {
525 u8 type;
526 u8 rsvd0[3];
527 __be32 inlen;
528 __be64 in_ptr;
529 __be32 in[4];
530 __be32 out[4];
531 __be64 out_ptr;
532 __be32 outlen;
533 u8 token;
534 u8 sig;
535 u8 rsvd1;
536 u8 status_own;
537};
538
539enum mlx5_fatal_assert_bit_offsets {
540 MLX5_RFR_OFFSET = 31,
541};
542
543struct health_buffer {
544 __be32 assert_var[5];
545 __be32 rsvd0[3];
546 __be32 assert_exit_ptr;
547 __be32 assert_callra;
548 __be32 rsvd1[2];
549 __be32 fw_ver;
550 __be32 hw_id;
551 __be32 rfr;
552 u8 irisc_index;
553 u8 synd;
554 __be16 ext_synd;
555};
556
557enum mlx5_initializing_bit_offsets {
558 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
559};
560
561enum mlx5_cmd_addr_l_sz_offset {
562 MLX5_NIC_IFC_OFFSET = 8,
563};
564
565struct mlx5_init_seg {
566 __be32 fw_rev;
567 __be32 cmdif_rev_fw_sub;
568 __be32 rsvd0[2];
569 __be32 cmdq_addr_h;
570 __be32 cmdq_addr_l_sz;
571 __be32 cmd_dbell;
572 __be32 rsvd1[120];
573 __be32 initializing;
574 struct health_buffer health;
575 __be32 rsvd2[880];
576 __be32 internal_timer_h;
577 __be32 internal_timer_l;
578 __be32 rsvd3[2];
579 __be32 health_counter;
580 __be32 rsvd4[1019];
581 __be64 ieee1588_clk;
582 __be32 ieee1588_clk_type;
583 __be32 clr_intx;
584};
585
586struct mlx5_eqe_comp {
587 __be32 reserved[6];
588 __be32 cqn;
589};
590
591struct mlx5_eqe_qp_srq {
592 __be32 reserved1[5];
593 u8 type;
594 u8 reserved2[3];
595 __be32 qp_srq_n;
596};
597
598struct mlx5_eqe_cq_err {
599 __be32 cqn;
600 u8 reserved1[7];
601 u8 syndrome;
602};
603
604struct mlx5_eqe_xrq_err {
605 __be32 reserved1[5];
606 __be32 type_xrqn;
607 __be32 reserved2;
608};
609
610struct mlx5_eqe_port_state {
611 u8 reserved0[8];
612 u8 port;
613};
614
615struct mlx5_eqe_gpio {
616 __be32 reserved0[2];
617 __be64 gpio_event;
618};
619
620struct mlx5_eqe_congestion {
621 u8 type;
622 u8 rsvd0;
623 u8 congestion_level;
624};
625
626struct mlx5_eqe_stall_vl {
627 u8 rsvd0[3];
628 u8 port_vl;
629};
630
631struct mlx5_eqe_cmd {
632 __be32 vector;
633 __be32 rsvd[6];
634};
635
636struct mlx5_eqe_page_req {
637 __be16 ec_function;
638 __be16 func_id;
639 __be32 num_pages;
640 __be32 rsvd1[5];
641};
642
643struct mlx5_eqe_page_fault {
644 __be32 bytes_committed;
645 union {
646 struct {
647 u16 reserved1;
648 __be16 wqe_index;
649 u16 reserved2;
650 __be16 packet_length;
651 __be32 token;
652 u8 reserved4[8];
653 __be32 pftype_wq;
654 } __packed wqe;
655 struct {
656 __be32 r_key;
657 u16 reserved1;
658 __be16 packet_length;
659 __be32 rdma_op_len;
660 __be64 rdma_va;
661 __be32 pftype_token;
662 } __packed rdma;
663 } __packed;
664} __packed;
665
666struct mlx5_eqe_vport_change {
667 u8 rsvd0[2];
668 __be16 vport_num;
669 __be32 rsvd1[6];
670} __packed;
671
672struct mlx5_eqe_port_module {
673 u8 reserved_at_0[1];
674 u8 module;
675 u8 reserved_at_2[1];
676 u8 module_status;
677 u8 reserved_at_4[2];
678 u8 error_type;
679} __packed;
680
681struct mlx5_eqe_pps {
682 u8 rsvd0[3];
683 u8 pin;
684 u8 rsvd1[4];
685 union {
686 struct {
687 __be32 time_sec;
688 __be32 time_nsec;
689 };
690 struct {
691 __be64 time_stamp;
692 };
693 };
694 u8 rsvd2[12];
695} __packed;
696
697struct mlx5_eqe_dct {
698 __be32 reserved[6];
699 __be32 dctn;
700};
701
702struct mlx5_eqe_temp_warning {
703 __be64 sensor_warning_msb;
704 __be64 sensor_warning_lsb;
705} __packed;
706
707#define SYNC_RST_STATE_MASK 0xf
708
709enum sync_rst_state_type {
710 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0,
711 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1,
712 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2,
713};
714
715struct mlx5_eqe_sync_fw_update {
716 u8 reserved_at_0[3];
717 u8 sync_rst_state;
718};
719
720union ev_data {
721 __be32 raw[7];
722 struct mlx5_eqe_cmd cmd;
723 struct mlx5_eqe_comp comp;
724 struct mlx5_eqe_qp_srq qp_srq;
725 struct mlx5_eqe_cq_err cq_err;
726 struct mlx5_eqe_port_state port;
727 struct mlx5_eqe_gpio gpio;
728 struct mlx5_eqe_congestion cong;
729 struct mlx5_eqe_stall_vl stall_vl;
730 struct mlx5_eqe_page_req req_pages;
731 struct mlx5_eqe_page_fault page_fault;
732 struct mlx5_eqe_vport_change vport_change;
733 struct mlx5_eqe_port_module port_module;
734 struct mlx5_eqe_pps pps;
735 struct mlx5_eqe_dct dct;
736 struct mlx5_eqe_temp_warning temp_warning;
737 struct mlx5_eqe_xrq_err xrq_err;
738 struct mlx5_eqe_sync_fw_update sync_fw_update;
739} __packed;
740
741struct mlx5_eqe {
742 u8 rsvd0;
743 u8 type;
744 u8 rsvd1;
745 u8 sub_type;
746 __be32 rsvd2[7];
747 union ev_data data;
748 __be16 rsvd3;
749 u8 signature;
750 u8 owner;
751} __packed;
752
753struct mlx5_cmd_prot_block {
754 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
755 u8 rsvd0[48];
756 __be64 next;
757 __be32 block_num;
758 u8 rsvd1;
759 u8 token;
760 u8 ctrl_sig;
761 u8 sig;
762};
763
764enum {
765 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
766};
767
768struct mlx5_err_cqe {
769 u8 rsvd0[32];
770 __be32 srqn;
771 u8 rsvd1[18];
772 u8 vendor_err_synd;
773 u8 syndrome;
774 __be32 s_wqe_opcode_qpn;
775 __be16 wqe_counter;
776 u8 signature;
777 u8 op_own;
778};
779
780struct mlx5_cqe64 {
781 u8 tls_outer_l3_tunneled;
782 u8 rsvd0;
783 __be16 wqe_id;
784 u8 lro_tcppsh_abort_dupack;
785 u8 lro_min_ttl;
786 __be16 lro_tcp_win;
787 __be32 lro_ack_seq_num;
788 __be32 rss_hash_result;
789 u8 rss_hash_type;
790 u8 ml_path;
791 u8 rsvd20[2];
792 __be16 check_sum;
793 __be16 slid;
794 __be32 flags_rqpn;
795 u8 hds_ip_ext;
796 u8 l4_l3_hdr_type;
797 __be16 vlan_info;
798 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
799 union {
800 __be32 immediate;
801 __be32 inval_rkey;
802 __be32 pkey;
803 __be32 ft_metadata;
804 };
805 u8 rsvd40[4];
806 __be32 byte_cnt;
807 __be32 timestamp_h;
808 __be32 timestamp_l;
809 __be32 sop_drop_qpn;
810 __be16 wqe_counter;
811 u8 signature;
812 u8 op_own;
813};
814
815struct mlx5_mini_cqe8 {
816 union {
817 __be32 rx_hash_result;
818 struct {
819 __be16 checksum;
820 __be16 stridx;
821 };
822 struct {
823 __be16 wqe_counter;
824 u8 s_wqe_opcode;
825 u8 reserved;
826 } s_wqe_info;
827 };
828 __be32 byte_cnt;
829};
830
831enum {
832 MLX5_NO_INLINE_DATA,
833 MLX5_INLINE_DATA32_SEG,
834 MLX5_INLINE_DATA64_SEG,
835 MLX5_COMPRESSED,
836};
837
838enum {
839 MLX5_CQE_FORMAT_CSUM = 0x1,
840 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
841};
842
843#define MLX5_MINI_CQE_ARRAY_SIZE 8
844
845static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
846{
847 return (cqe->op_own >> 2) & 0x3;
848}
849
850static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
851{
852 return cqe->op_own >> 4;
853}
854
855static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
856{
857 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
858}
859
860static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
861{
862 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
863}
864
865static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
866{
867 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
868}
869
870static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
871{
872 return cqe->tls_outer_l3_tunneled & 0x1;
873}
874
875static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
876{
877 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
878}
879
880static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
881{
882 return cqe->l4_l3_hdr_type & 0x1;
883}
884
885static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
886{
887 u32 hi, lo;
888
889 hi = be32_to_cpu(cqe->timestamp_h);
890 lo = be32_to_cpu(cqe->timestamp_l);
891
892 return (u64)lo | ((u64)hi << 32);
893}
894
895#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
896#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
897
898struct mpwrq_cqe_bc {
899 __be16 filler_consumed_strides;
900 __be16 byte_cnt;
901};
902
903static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
904{
905 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
906
907 return be16_to_cpu(bc->byte_cnt);
908}
909
910static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
911{
912 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
913}
914
915static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
916{
917 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
918
919 return mpwrq_get_cqe_bc_consumed_strides(bc);
920}
921
922static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
923{
924 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
925
926 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
927}
928
929static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
930{
931 return be16_to_cpu(cqe->wqe_counter);
932}
933
934enum {
935 CQE_L4_HDR_TYPE_NONE = 0x0,
936 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
937 CQE_L4_HDR_TYPE_UDP = 0x2,
938 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
939 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
940};
941
942enum {
943 CQE_RSS_HTYPE_IP = 0x3 << 2,
944 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
945 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
946 */
947 CQE_RSS_HTYPE_L4 = 0x3 << 6,
948 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
949 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
950 */
951};
952
953enum {
954 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
955 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
956 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
957};
958
959enum {
960 CQE_L2_OK = 1 << 0,
961 CQE_L3_OK = 1 << 1,
962 CQE_L4_OK = 1 << 2,
963};
964
965enum {
966 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0,
967 CQE_TLS_OFFLOAD_DECRYPTED = 0x1,
968 CQE_TLS_OFFLOAD_RESYNC = 0x2,
969 CQE_TLS_OFFLOAD_ERROR = 0x3,
970};
971
972struct mlx5_sig_err_cqe {
973 u8 rsvd0[16];
974 __be32 expected_trans_sig;
975 __be32 actual_trans_sig;
976 __be32 expected_reftag;
977 __be32 actual_reftag;
978 __be16 syndrome;
979 u8 rsvd22[2];
980 __be32 mkey;
981 __be64 err_offset;
982 u8 rsvd30[8];
983 __be32 qpn;
984 u8 rsvd38[2];
985 u8 signature;
986 u8 op_own;
987};
988
989struct mlx5_wqe_srq_next_seg {
990 u8 rsvd0[2];
991 __be16 next_wqe_index;
992 u8 signature;
993 u8 rsvd1[11];
994};
995
996union mlx5_ext_cqe {
997 struct ib_grh grh;
998 u8 inl[64];
999};
1000
1001struct mlx5_cqe128 {
1002 union mlx5_ext_cqe inl_grh;
1003 struct mlx5_cqe64 cqe64;
1004};
1005
1006enum {
1007 MLX5_MKEY_STATUS_FREE = 1 << 6,
1008};
1009
1010enum {
1011 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
1012 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
1013 MLX5_MKEY_BSF_EN = 1 << 30,
1014};
1015
1016struct mlx5_mkey_seg {
1017 /* This is a two bit field occupying bits 31-30.
1018 * bit 31 is always 0,
1019 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
1020 */
1021 u8 status;
1022 u8 pcie_control;
1023 u8 flags;
1024 u8 version;
1025 __be32 qpn_mkey7_0;
1026 u8 rsvd1[4];
1027 __be32 flags_pd;
1028 __be64 start_addr;
1029 __be64 len;
1030 __be32 bsfs_octo_size;
1031 u8 rsvd2[16];
1032 __be32 xlt_oct_size;
1033 u8 rsvd3[3];
1034 u8 log2_page_size;
1035 u8 rsvd4[4];
1036};
1037
1038#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1039
1040enum {
1041 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1042};
1043
1044enum {
1045 VPORT_STATE_DOWN = 0x0,
1046 VPORT_STATE_UP = 0x1,
1047};
1048
1049enum {
1050 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
1051 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
1052 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
1053};
1054
1055enum {
1056 MLX5_L3_PROT_TYPE_IPV4 = 0,
1057 MLX5_L3_PROT_TYPE_IPV6 = 1,
1058};
1059
1060enum {
1061 MLX5_L4_PROT_TYPE_TCP = 0,
1062 MLX5_L4_PROT_TYPE_UDP = 1,
1063};
1064
1065enum {
1066 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1067 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1068 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1069 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1070 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1071};
1072
1073enum {
1074 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1075 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1076 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1077 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
1078 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
1079};
1080
1081enum {
1082 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1083 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1084};
1085
1086enum {
1087 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1088 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1089 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1090};
1091
1092enum mlx5_list_type {
1093 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1094 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1095 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1096};
1097
1098enum {
1099 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1100 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1101};
1102
1103enum mlx5_wol_mode {
1104 MLX5_WOL_DISABLE = 0,
1105 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1106 MLX5_WOL_MAGIC = 1 << 2,
1107 MLX5_WOL_ARP = 1 << 3,
1108 MLX5_WOL_BROADCAST = 1 << 4,
1109 MLX5_WOL_MULTICAST = 1 << 5,
1110 MLX5_WOL_UNICAST = 1 << 6,
1111 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1112};
1113
1114enum mlx5_mpls_supported_fields {
1115 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1116 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1117 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1118 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1119};
1120
1121enum mlx5_flex_parser_protos {
1122 MLX5_FLEX_PROTO_GENEVE = 1 << 3,
1123 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1124 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1125};
1126
1127/* MLX5 DEV CAPs */
1128
1129/* TODO: EAT.ME */
1130enum mlx5_cap_mode {
1131 HCA_CAP_OPMOD_GET_MAX = 0,
1132 HCA_CAP_OPMOD_GET_CUR = 1,
1133};
1134
1135enum mlx5_cap_type {
1136 MLX5_CAP_GENERAL = 0,
1137 MLX5_CAP_ETHERNET_OFFLOADS,
1138 MLX5_CAP_ODP,
1139 MLX5_CAP_ATOMIC,
1140 MLX5_CAP_ROCE,
1141 MLX5_CAP_IPOIB_OFFLOADS,
1142 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1143 MLX5_CAP_FLOW_TABLE,
1144 MLX5_CAP_ESWITCH_FLOW_TABLE,
1145 MLX5_CAP_ESWITCH,
1146 MLX5_CAP_RESERVED,
1147 MLX5_CAP_VECTOR_CALC,
1148 MLX5_CAP_QOS,
1149 MLX5_CAP_DEBUG,
1150 MLX5_CAP_RESERVED_14,
1151 MLX5_CAP_DEV_MEM,
1152 MLX5_CAP_RESERVED_16,
1153 MLX5_CAP_TLS,
1154 MLX5_CAP_VDPA_EMULATION = 0x13,
1155 MLX5_CAP_DEV_EVENT = 0x14,
1156 MLX5_CAP_IPSEC,
1157 /* NUM OF CAP Types */
1158 MLX5_CAP_NUM
1159};
1160
1161enum mlx5_pcam_reg_groups {
1162 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1163};
1164
1165enum mlx5_pcam_feature_groups {
1166 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1167};
1168
1169enum mlx5_mcam_reg_groups {
1170 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1171 MLX5_MCAM_REGS_0x9080_0x90FF = 0x1,
1172 MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
1173 MLX5_MCAM_REGS_NUM = 0x3,
1174};
1175
1176enum mlx5_mcam_feature_groups {
1177 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1178};
1179
1180enum mlx5_qcam_reg_groups {
1181 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1182};
1183
1184enum mlx5_qcam_feature_groups {
1185 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1186};
1187
1188/* GET Dev Caps macros */
1189#define MLX5_CAP_GEN(mdev, cap) \
1190 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1191
1192#define MLX5_CAP_GEN_64(mdev, cap) \
1193 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1194
1195#define MLX5_CAP_GEN_MAX(mdev, cap) \
1196 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1197
1198#define MLX5_CAP_ETH(mdev, cap) \
1199 MLX5_GET(per_protocol_networking_offload_caps,\
1200 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1201
1202#define MLX5_CAP_ETH_MAX(mdev, cap) \
1203 MLX5_GET(per_protocol_networking_offload_caps,\
1204 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1205
1206#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1207 MLX5_GET(per_protocol_networking_offload_caps,\
1208 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1209
1210#define MLX5_CAP_ROCE(mdev, cap) \
1211 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1212
1213#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1214 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1215
1216#define MLX5_CAP_ATOMIC(mdev, cap) \
1217 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1218
1219#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1220 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1221
1222#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1223 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1224
1225#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1226 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1227
1228#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1229 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1230
1231#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1232 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1233
1234#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1235 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1236
1237#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1238 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1239
1240#define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1241 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1242
1243#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1244 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1245
1246#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1247 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1248
1249#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1250 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1251
1252#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1253 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1254
1255#define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1256 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1257
1258#define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \
1259 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1260
1261#define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1262 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1263
1264#define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \
1265 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1266
1267#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1268 MLX5_GET(flow_table_eswitch_cap, \
1269 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1270
1271#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1272 MLX5_GET(flow_table_eswitch_cap, \
1273 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1274
1275#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1276 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1277
1278#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1279 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1280
1281#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1282 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1283
1284#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1285 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1286
1287#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1288 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1289
1290#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1291 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1292
1293#define MLX5_CAP_ESW(mdev, cap) \
1294 MLX5_GET(e_switch_cap, \
1295 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1296
1297#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1298 MLX5_GET64(flow_table_eswitch_cap, \
1299 (mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1300
1301#define MLX5_CAP_ESW_MAX(mdev, cap) \
1302 MLX5_GET(e_switch_cap, \
1303 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1304
1305#define MLX5_CAP_ODP(mdev, cap)\
1306 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1307
1308#define MLX5_CAP_ODP_MAX(mdev, cap)\
1309 MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
1310
1311#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1312 MLX5_GET(vector_calc_cap, \
1313 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1314
1315#define MLX5_CAP_QOS(mdev, cap)\
1316 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1317
1318#define MLX5_CAP_DEBUG(mdev, cap)\
1319 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1320
1321#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1322 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1323
1324#define MLX5_CAP_PCAM_REG(mdev, reg) \
1325 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1326
1327#define MLX5_CAP_MCAM_REG(mdev, reg) \
1328 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1329 mng_access_reg_cap_mask.access_regs.reg)
1330
1331#define MLX5_CAP_MCAM_REG1(mdev, reg) \
1332 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \
1333 mng_access_reg_cap_mask.access_regs1.reg)
1334
1335#define MLX5_CAP_MCAM_REG2(mdev, reg) \
1336 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1337 mng_access_reg_cap_mask.access_regs2.reg)
1338
1339#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1340 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1341
1342#define MLX5_CAP_QCAM_REG(mdev, fld) \
1343 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1344
1345#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1346 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1347
1348#define MLX5_CAP_FPGA(mdev, cap) \
1349 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1350
1351#define MLX5_CAP64_FPGA(mdev, cap) \
1352 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1353
1354#define MLX5_CAP_DEV_MEM(mdev, cap)\
1355 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1356
1357#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1358 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1359
1360#define MLX5_CAP_TLS(mdev, cap) \
1361 MLX5_GET(tls_cap, (mdev)->caps.hca_cur[MLX5_CAP_TLS], cap)
1362
1363#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1364 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1365
1366#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1367 MLX5_GET(virtio_emulation_cap, \
1368 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1369
1370#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1371 MLX5_GET64(virtio_emulation_cap, \
1372 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1373
1374#define MLX5_CAP_IPSEC(mdev, cap)\
1375 MLX5_GET(ipsec_cap, (mdev)->caps.hca_cur[MLX5_CAP_IPSEC], cap)
1376
1377enum {
1378 MLX5_CMD_STAT_OK = 0x0,
1379 MLX5_CMD_STAT_INT_ERR = 0x1,
1380 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1381 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1382 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1383 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1384 MLX5_CMD_STAT_RES_BUSY = 0x6,
1385 MLX5_CMD_STAT_LIM_ERR = 0x8,
1386 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1387 MLX5_CMD_STAT_IX_ERR = 0xa,
1388 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1389 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1390 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1391 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1392 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1393 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1394};
1395
1396enum {
1397 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1398 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1399 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1400 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1401 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1402 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1403 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1404 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1405 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1406 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1407 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1408};
1409
1410enum {
1411 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1412};
1413
1414static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1415{
1416 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1417 return 0;
1418 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1419}
1420
1421#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1422#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1423#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1424#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1425 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1426 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1427
1428#endif /* MLX5_DEVICE_H */