Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Pentium III FXSR, SSE support
6 * General FPU state handling cleanups
7 * Gareth Hughes <gareth@valinux.com>, May 2000
8 * x86-64 work by Andi Kleen 2002
9 */
10
11#ifndef _ASM_X86_FPU_API_H
12#define _ASM_X86_FPU_API_H
13#include <linux/bottom_half.h>
14
15/*
16 * Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It
17 * disables preemption so be careful if you intend to use it for long periods
18 * of time.
19 * If you intend to use the FPU in softirq you need to check first with
20 * irq_fpu_usable() if it is possible.
21 */
22extern void kernel_fpu_begin(void);
23extern void kernel_fpu_end(void);
24extern bool irq_fpu_usable(void);
25extern void fpregs_mark_activate(void);
26
27/*
28 * Use fpregs_lock() while editing CPU's FPU registers or fpu->state.
29 * A context switch will (and softirq might) save CPU's FPU registers to
30 * fpu->state and set TIF_NEED_FPU_LOAD leaving CPU's FPU registers in
31 * a random state.
32 */
33static inline void fpregs_lock(void)
34{
35 preempt_disable();
36 local_bh_disable();
37}
38
39static inline void fpregs_unlock(void)
40{
41 local_bh_enable();
42 preempt_enable();
43}
44
45#ifdef CONFIG_X86_DEBUG_FPU
46extern void fpregs_assert_state_consistent(void);
47#else
48static inline void fpregs_assert_state_consistent(void) { }
49#endif
50
51/*
52 * Load the task FPU state before returning to userspace.
53 */
54extern void switch_fpu_return(void);
55
56/*
57 * Query the presence of one or more xfeatures. Works on any legacy CPU as well.
58 *
59 * If 'feature_name' is set then put a human-readable description of
60 * the feature there as well - this can be used to print error (or success)
61 * messages.
62 */
63extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name);
64
65/*
66 * Tasks that are not using SVA have mm->pasid set to zero to note that they
67 * will not have the valid bit set in MSR_IA32_PASID while they are running.
68 */
69#define PASID_DISABLED 0
70
71#ifdef CONFIG_IOMMU_SUPPORT
72/* Update current's PASID MSR/state by mm's PASID. */
73void update_pasid(void);
74#else
75static inline void update_pasid(void) { }
76#endif
77#endif /* _ASM_X86_FPU_API_H */