tjh.dev
Linux kernel mirror (for testing)
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linux
1RPMH RSC:
2------------
3
4Resource Power Manager Hardened (RPMH) is the mechanism for communicating with
5the hardened resource accelerators on Qualcomm SoCs. Requests to the resources
6can be written to the Trigger Command Set (TCS) registers and using a (addr,
7val) pair and triggered. Messages in the TCS are then sent in sequence over an
8internal bus.
9
10The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
11(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
12active/wake resource requests. Multiple such DRVs can exist in a SoC and can
13be written to from Linux. The structure of each DRV follows the same template
14with a few variations that are captured by the properties here.
15
16A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
17have powered off to facilitate idle power saving. TCS could be classified as -
18
19 ACTIVE /* Triggered by Linux */
20 SLEEP /* Triggered by F/W */
21 WAKE /* Triggered by F/W */
22 CONTROL /* Triggered by F/W */
23
24The order in which they are described in the DT, should match the hardware
25configuration.
26
27Requests can be made for the state of a resource, when the subsystem is active
28or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state
29will be an aggregate of the sleep votes from each of those subsystems. Clients
30may request a sleep value for their shared resources in addition to the active
31mode requests.
32
33Properties:
34
35- compatible:
36 Usage: required
37 Value type: <string>
38 Definition: Should be "qcom,rpmh-rsc".
39
40- reg:
41 Usage: required
42 Value type: <prop-encoded-array>
43 Definition: The first register specifies the base address of the
44 DRV(s). The number of DRVs in the dependent on the RSC.
45 The tcs-offset specifies the start address of the
46 TCS in the DRVs.
47
48- reg-names:
49 Usage: required
50 Value type: <string>
51 Definition: Maps the register specified in the reg property. Must be
52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
53
54- interrupts:
55 Usage: required
56 Value type: <prop-encoded-interrupt>
57 Definition: The interrupt that trips when a message complete/response
58 is received for this DRV from the accelerators.
59
60- qcom,drv-id:
61 Usage: required
62 Value type: <u32>
63 Definition: The id of the DRV in the RSC block that will be used by
64 this controller.
65
66- qcom,tcs-config:
67 Usage: required
68 Value type: <prop-encoded-array>
69 Definition: The tuple defining the configuration of TCS.
70 Must have 2 cells which describe each TCS type.
71 <type number_of_tcs>.
72 The order of the TCS must match the hardware
73 configuration.
74 - Cell #1 (TCS Type): TCS types to be specified -
75 ACTIVE_TCS
76 SLEEP_TCS
77 WAKE_TCS
78 CONTROL_TCS
79 - Cell #2 (Number of TCS): <u32>
80
81- label:
82 Usage: optional
83 Value type: <string>
84 Definition: Name for the RSC. The name would be used in trace logs.
85
86Drivers that want to use the RSC to communicate with RPMH must specify their
87bindings as child nodes of the RSC controllers they wish to communicate with.
88
89Example 1:
90
91For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
92register offsets for DRV2 start at 0D00, the register calculations are like
93this -
94DRV0: 0x179C0000
95DRV2: 0x179C0000 + 0x10000 = 0x179D0000
96DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
97TCS-OFFSET: 0xD00
98
99 apps_rsc: rsc@179c0000 {
100 label = "apps_rsc";
101 compatible = "qcom,rpmh-rsc";
102 reg = <0x179c0000 0x10000>,
103 <0x179d0000 0x10000>,
104 <0x179e0000 0x10000>;
105 reg-names = "drv-0", "drv-1", "drv-2";
106 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
109 qcom,tcs-offset = <0xd00>;
110 qcom,drv-id = <2>;
111 qcom,tcs-config = <ACTIVE_TCS 2>,
112 <SLEEP_TCS 3>,
113 <WAKE_TCS 3>,
114 <CONTROL_TCS 1>;
115 };
116
117Example 2:
118
119For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
120register offsets for DRV0 start at 01C00, the register calculations are like
121this -
122DRV0: 0xAF20000
123TCS-OFFSET: 0x1C00
124
125 disp_rsc: rsc@af20000 {
126 label = "disp_rsc";
127 compatible = "qcom,rpmh-rsc";
128 reg = <0xaf20000 0x10000>;
129 reg-names = "drv-0";
130 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
131 qcom,tcs-offset = <0x1c00>;
132 qcom,drv-id = <0>;
133 qcom,tcs-config = <ACTIVE_TCS 0>,
134 <SLEEP_TCS 1>,
135 <WAKE_TCS 1>,
136 <CONTROL_TCS 0>;
137 };