tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _PSP_TEE_GFX_IF_H_
25#define _PSP_TEE_GFX_IF_H_
26
27#define PSP_GFX_CMD_BUF_VERSION 0x00000001
28
29#define GFX_CMD_STATUS_MASK 0x0000FFFF
30#define GFX_CMD_ID_MASK 0x000F0000
31#define GFX_CMD_RESERVED_MASK 0x7FF00000
32#define GFX_CMD_RESPONSE_MASK 0x80000000
33
34/* USBC PD FW version retrieval command */
35#define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000
36
37/* TEE Gfx Command IDs for the register interface.
38* Command ID must be between 0x00010000 and 0x000F0000.
39*/
40enum psp_gfx_crtl_cmd_id
41{
42 GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
43 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
44 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
45 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
48 GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
49 GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
50 GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A0000, /* send interrupt to psp for updating write pointer of vf */
51 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
52
53 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
54};
55
56
57/*-----------------------------------------------------------------------------
58 NOTE: All physical addresses used in this interface are actually
59 GPU Virtual Addresses.
60*/
61
62
63/* Control registers of the TEE Gfx interface. These are located in
64* SRBM-to-PSP mailbox registers (total 8 registers).
65*/
66struct psp_gfx_ctrl
67{
68 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */
69 volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */
70 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
71 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
72 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
73 volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74 volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
75 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
76
77};
78
79
80/* Response flag is set in the command when command is completed by PSP.
81* Used in the GFX_CTRL.CmdResp.
82* When PSP GFX I/F is initialized, the flag is set.
83*/
84#define GFX_FLAG_RESPONSE 0x80000000
85
86/* TEE Gfx Command IDs for the ring buffer interface. */
87enum psp_gfx_cmd_id
88{
89 GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */
90 GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */
91 GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */
92 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
93 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
94 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
95 GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */
96 GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */
97 GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */
98 GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */
99 GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */
100 GFX_CMD_ID_CLEAR_VF_FW = 0x0000000D, /* Clear VF FW, to be used on VF shutdown. */
101 /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
102 GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */
103 GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */
104};
105
106/* Command to load Trusted Application binary into PSP OS. */
107struct psp_gfx_cmd_load_ta
108{
109 uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
110 uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */
111 uint32_t app_len; /* length of the TA binary in bytes */
112 uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
113 uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
114 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
115
116 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
117 * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
118 * of using global persistent buffer.
119 */
120};
121
122
123/* Command to Unload Trusted Application binary from PSP OS. */
124struct psp_gfx_cmd_unload_ta
125{
126 uint32_t session_id; /* Session ID of the loaded TA to be unloaded */
127
128};
129
130
131/* Shared buffers for InvokeCommand.
132*/
133struct psp_gfx_buf_desc
134{
135 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
136 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
137 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
138
139};
140
141/* Max number of descriptors for one shared buffer (in how many different
142* physical locations one shared buffer can be stored). If buffer is too much
143* fragmented, error will be returned.
144*/
145#define GFX_BUF_MAX_DESC 64
146
147struct psp_gfx_buf_list
148{
149 uint32_t num_desc; /* number of buffer descriptors in the list */
150 uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
151 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */
152
153 /* total 776 bytes */
154};
155
156/* Command to execute InvokeCommand entry point of the TA. */
157struct psp_gfx_cmd_invoke_cmd
158{
159 uint32_t session_id; /* Session ID of the TA to be executed */
160 uint32_t ta_cmd_id; /* Command ID to be sent to TA */
161 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */
162
163};
164
165
166/* Command to setup TMR region. */
167struct psp_gfx_cmd_setup_tmr
168{
169 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
170 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
171 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
172
173};
174
175
176/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
177enum psp_gfx_fw_type {
178 GFX_FW_TYPE_NONE = 0, /* */
179 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
180 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
181 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
182 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
183 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
184 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
185 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
186 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
187 GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */
188 GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */
189 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
190 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
191 GFX_FW_TYPE_VCN = 13, /* VCN RV */
192 GFX_FW_TYPE_UVD = 14, /* UVD VG */
193 GFX_FW_TYPE_VCE = 15, /* VCE VG */
194 GFX_FW_TYPE_ISP = 16, /* ISP RV */
195 GFX_FW_TYPE_ACP = 17, /* ACP RV */
196 GFX_FW_TYPE_SMU = 18, /* SMU VG */
197 GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */
198 GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */
199 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */
200 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */
201 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
202 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
203 GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */
204 GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */
205 GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */
206 GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */
207 GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */
208 GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */
209 GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */
210 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
211 GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */
212 GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */
213 GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */
214 GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */
215 GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */
216 GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */
217 GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */
218 GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */
219 GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */
220 GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */
221 GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */
222 GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */
223 GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */
224 GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */
225 GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */
226 GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */
227 GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */
228 GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */
229 GFX_FW_TYPE_DMUB = 51, /* DMUB RN */
230 GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */
231 GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */
232 GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */
233 GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */
234 GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */
235 GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */
236 GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */
237 GFX_FW_TYPE_MAX
238};
239
240/* Command to load HW IP FW. */
241struct psp_gfx_cmd_load_ip_fw
242{
243 uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
244 uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
245 uint32_t fw_size; /* FW buffer size in bytes */
246 enum psp_gfx_fw_type fw_type; /* FW type */
247
248};
249
250/* Command to save/restore HW IP FW. */
251struct psp_gfx_cmd_save_restore_ip_fw
252{
253 uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/
254 uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
255 uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
256 uint32_t buf_size; /* Size of the save/restore buffer in bytes */
257 enum psp_gfx_fw_type fw_type; /* FW type */
258};
259
260/* Command to setup register program */
261struct psp_gfx_cmd_reg_prog {
262 uint32_t reg_value;
263 uint32_t reg_id;
264};
265
266/* Command to load TOC */
267struct psp_gfx_cmd_load_toc
268{
269 uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
270 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
271 uint32_t toc_size; /* FW buffer size in bytes */
272};
273
274/* All GFX ring buffer commands. */
275union psp_gfx_commands
276{
277 struct psp_gfx_cmd_load_ta cmd_load_ta;
278 struct psp_gfx_cmd_unload_ta cmd_unload_ta;
279 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
280 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
281 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
282 struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
283 struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog;
284 struct psp_gfx_cmd_setup_tmr cmd_setup_vmr;
285 struct psp_gfx_cmd_load_toc cmd_load_toc;
286};
287
288/* Structure of GFX Response buffer.
289* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
290* it is separate buffer.
291*/
292struct psp_gfx_resp
293{
294 uint32_t status; /* +0 status of command execution */
295 uint32_t session_id; /* +4 session ID in response to LoadTa command */
296 uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
297 uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
298 uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
299
300 uint32_t reserved[3];
301
302 /* total 32 bytes */
303};
304
305/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
306* and psp_gfx_rb_frame.cmd_buf_addr_lo.
307*/
308struct psp_gfx_cmd_resp
309{
310 uint32_t buf_size; /* +0 total size of the buffer in bytes */
311 uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
312 uint32_t cmd_id; /* +8 command ID */
313
314 /* These fields are used for RBI only. They are all 0 in GPCOM commands
315 */
316 uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
317 uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */
318 uint32_t resp_offset; /* +20 offset within response buffer */
319 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */
320
321 union psp_gfx_commands cmd; /* +28 command specific structures */
322
323 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
324
325 /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
326 * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
327 */
328 struct psp_gfx_resp resp; /* +864 response */
329
330 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
331
332 /* total size 1024 bytes */
333};
334
335
336#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
337
338/* Structure of the Ring Buffer Frame */
339struct psp_gfx_rb_frame
340{
341 uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
342 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
343 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
344 uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
345 uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
346 uint32_t fence_value; /* +20 Fence value */
347 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
348 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
349 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */
350 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
351 uint8_t reserved1[2]; /* +34 reserved, must be 0 */
352 uint32_t reserved2[7]; /* +36 reserved, must be 0 */
353 /* total 64 bytes */
354};
355
356#define PSP_ERR_UNKNOWN_COMMAND 0x00000100
357
358enum tee_error_code {
359 TEE_SUCCESS = 0x00000000,
360 TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A,
361};
362
363#endif /* _PSP_TEE_GFX_IF_H_ */