Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef AMDGPU_MODE_H
31#define AMDGPU_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_encoder.h>
36#include <drm/drm_dp_helper.h>
37#include <drm/drm_fixed.h>
38#include <drm/drm_crtc_helper.h>
39#include <drm/drm_fb_helper.h>
40#include <drm/drm_plane_helper.h>
41#include <drm/drm_probe_helper.h>
42#include <linux/i2c.h>
43#include <linux/i2c-algo-bit.h>
44#include <linux/hrtimer.h>
45#include "amdgpu_irq.h"
46
47#include <drm/drm_dp_mst_helper.h>
48#include "modules/inc/mod_freesync.h"
49#include "amdgpu_dm_irq_params.h"
50
51struct amdgpu_bo;
52struct amdgpu_device;
53struct amdgpu_encoder;
54struct amdgpu_router;
55struct amdgpu_hpd;
56
57#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
58#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
59#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
60#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
61
62#define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base)
63
64#define AMDGPU_MAX_HPD_PINS 6
65#define AMDGPU_MAX_CRTCS 6
66#define AMDGPU_MAX_PLANES 6
67#define AMDGPU_MAX_AFMT_BLOCKS 9
68
69enum amdgpu_rmx_type {
70 RMX_OFF,
71 RMX_FULL,
72 RMX_CENTER,
73 RMX_ASPECT
74};
75
76enum amdgpu_underscan_type {
77 UNDERSCAN_OFF,
78 UNDERSCAN_ON,
79 UNDERSCAN_AUTO,
80};
81
82#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
83#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
84
85enum amdgpu_hpd_id {
86 AMDGPU_HPD_1 = 0,
87 AMDGPU_HPD_2,
88 AMDGPU_HPD_3,
89 AMDGPU_HPD_4,
90 AMDGPU_HPD_5,
91 AMDGPU_HPD_6,
92 AMDGPU_HPD_NONE = 0xff,
93};
94
95enum amdgpu_crtc_irq {
96 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
97 AMDGPU_CRTC_IRQ_VBLANK2,
98 AMDGPU_CRTC_IRQ_VBLANK3,
99 AMDGPU_CRTC_IRQ_VBLANK4,
100 AMDGPU_CRTC_IRQ_VBLANK5,
101 AMDGPU_CRTC_IRQ_VBLANK6,
102 AMDGPU_CRTC_IRQ_VLINE1,
103 AMDGPU_CRTC_IRQ_VLINE2,
104 AMDGPU_CRTC_IRQ_VLINE3,
105 AMDGPU_CRTC_IRQ_VLINE4,
106 AMDGPU_CRTC_IRQ_VLINE5,
107 AMDGPU_CRTC_IRQ_VLINE6,
108 AMDGPU_CRTC_IRQ_NONE = 0xff
109};
110
111enum amdgpu_pageflip_irq {
112 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
113 AMDGPU_PAGEFLIP_IRQ_D2,
114 AMDGPU_PAGEFLIP_IRQ_D3,
115 AMDGPU_PAGEFLIP_IRQ_D4,
116 AMDGPU_PAGEFLIP_IRQ_D5,
117 AMDGPU_PAGEFLIP_IRQ_D6,
118 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
119};
120
121enum amdgpu_flip_status {
122 AMDGPU_FLIP_NONE,
123 AMDGPU_FLIP_PENDING,
124 AMDGPU_FLIP_SUBMITTED
125};
126
127#define AMDGPU_MAX_I2C_BUS 16
128
129/* amdgpu gpio-based i2c
130 * 1. "mask" reg and bits
131 * grabs the gpio pins for software use
132 * 0=not held 1=held
133 * 2. "a" reg and bits
134 * output pin value
135 * 0=low 1=high
136 * 3. "en" reg and bits
137 * sets the pin direction
138 * 0=input 1=output
139 * 4. "y" reg and bits
140 * input pin value
141 * 0=low 1=high
142 */
143struct amdgpu_i2c_bus_rec {
144 bool valid;
145 /* id used by atom */
146 uint8_t i2c_id;
147 /* id used by atom */
148 enum amdgpu_hpd_id hpd;
149 /* can be used with hw i2c engine */
150 bool hw_capable;
151 /* uses multi-media i2c engine */
152 bool mm_i2c;
153 /* regs and bits */
154 uint32_t mask_clk_reg;
155 uint32_t mask_data_reg;
156 uint32_t a_clk_reg;
157 uint32_t a_data_reg;
158 uint32_t en_clk_reg;
159 uint32_t en_data_reg;
160 uint32_t y_clk_reg;
161 uint32_t y_data_reg;
162 uint32_t mask_clk_mask;
163 uint32_t mask_data_mask;
164 uint32_t a_clk_mask;
165 uint32_t a_data_mask;
166 uint32_t en_clk_mask;
167 uint32_t en_data_mask;
168 uint32_t y_clk_mask;
169 uint32_t y_data_mask;
170};
171
172#define AMDGPU_MAX_BIOS_CONNECTOR 16
173
174/* pll flags */
175#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
176#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
177#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
178#define AMDGPU_PLL_LEGACY (1 << 3)
179#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
180#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
181#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
182#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
183#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
184#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
185#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
186#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
187#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
188#define AMDGPU_PLL_IS_LCD (1 << 13)
189#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
190
191struct amdgpu_pll {
192 /* reference frequency */
193 uint32_t reference_freq;
194
195 /* fixed dividers */
196 uint32_t reference_div;
197 uint32_t post_div;
198
199 /* pll in/out limits */
200 uint32_t pll_in_min;
201 uint32_t pll_in_max;
202 uint32_t pll_out_min;
203 uint32_t pll_out_max;
204 uint32_t lcd_pll_out_min;
205 uint32_t lcd_pll_out_max;
206 uint32_t best_vco;
207
208 /* divider limits */
209 uint32_t min_ref_div;
210 uint32_t max_ref_div;
211 uint32_t min_post_div;
212 uint32_t max_post_div;
213 uint32_t min_feedback_div;
214 uint32_t max_feedback_div;
215 uint32_t min_frac_feedback_div;
216 uint32_t max_frac_feedback_div;
217
218 /* flags for the current clock */
219 uint32_t flags;
220
221 /* pll id */
222 uint32_t id;
223};
224
225struct amdgpu_i2c_chan {
226 struct i2c_adapter adapter;
227 struct drm_device *dev;
228 struct i2c_algo_bit_data bit;
229 struct amdgpu_i2c_bus_rec rec;
230 struct drm_dp_aux aux;
231 bool has_aux;
232 struct mutex mutex;
233};
234
235struct amdgpu_fbdev;
236
237struct amdgpu_afmt {
238 bool enabled;
239 int offset;
240 bool last_buffer_filled_status;
241 int id;
242 struct amdgpu_audio_pin *pin;
243};
244
245/*
246 * Audio
247 */
248struct amdgpu_audio_pin {
249 int channels;
250 int rate;
251 int bits_per_sample;
252 u8 status_bits;
253 u8 category_code;
254 u32 offset;
255 bool connected;
256 u32 id;
257};
258
259struct amdgpu_audio {
260 bool enabled;
261 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
262 int num_pins;
263};
264
265struct amdgpu_display_funcs {
266 /* display watermarks */
267 void (*bandwidth_update)(struct amdgpu_device *adev);
268 /* get frame count */
269 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
270 /* set backlight level */
271 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
272 u8 level);
273 /* get backlight level */
274 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
275 /* hotplug detect */
276 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
277 void (*hpd_set_polarity)(struct amdgpu_device *adev,
278 enum amdgpu_hpd_id hpd);
279 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
280 /* pageflipping */
281 void (*page_flip)(struct amdgpu_device *adev,
282 int crtc_id, u64 crtc_base, bool async);
283 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
284 u32 *vbl, u32 *position);
285 /* display topology setup */
286 void (*add_encoder)(struct amdgpu_device *adev,
287 uint32_t encoder_enum,
288 uint32_t supported_device,
289 u16 caps);
290 void (*add_connector)(struct amdgpu_device *adev,
291 uint32_t connector_id,
292 uint32_t supported_device,
293 int connector_type,
294 struct amdgpu_i2c_bus_rec *i2c_bus,
295 uint16_t connector_object_id,
296 struct amdgpu_hpd *hpd,
297 struct amdgpu_router *router);
298
299
300};
301
302struct amdgpu_framebuffer {
303 struct drm_framebuffer base;
304
305 /* caching for later use */
306 uint64_t address;
307};
308
309struct amdgpu_fbdev {
310 struct drm_fb_helper helper;
311 struct amdgpu_framebuffer rfb;
312 struct list_head fbdev_list;
313 struct amdgpu_device *adev;
314};
315
316struct amdgpu_mode_info {
317 struct atom_context *atom_context;
318 struct card_info *atom_card_info;
319 bool mode_config_initialized;
320 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
321 struct drm_plane *planes[AMDGPU_MAX_PLANES];
322 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
323 /* DVI-I properties */
324 struct drm_property *coherent_mode_property;
325 /* DAC enable load detect */
326 struct drm_property *load_detect_property;
327 /* underscan */
328 struct drm_property *underscan_property;
329 struct drm_property *underscan_hborder_property;
330 struct drm_property *underscan_vborder_property;
331 /* audio */
332 struct drm_property *audio_property;
333 /* FMT dithering */
334 struct drm_property *dither_property;
335 /* Adaptive Backlight Modulation (power feature) */
336 struct drm_property *abm_level_property;
337 /* hardcoded DFP edid from BIOS */
338 struct edid *bios_hardcoded_edid;
339 int bios_hardcoded_edid_size;
340
341 /* pointer to fbdev info structure */
342 struct amdgpu_fbdev *rfbdev;
343 /* firmware flags */
344 u16 firmware_flags;
345 /* pointer to backlight encoder */
346 struct amdgpu_encoder *bl_encoder;
347 u8 bl_level; /* saved backlight level */
348 struct amdgpu_audio audio; /* audio stuff */
349 int num_crtc; /* number of crtcs */
350 int num_hpd; /* number of hpd pins */
351 int num_dig; /* number of dig blocks */
352 int disp_priority;
353 const struct amdgpu_display_funcs *funcs;
354 const enum drm_plane_type *plane_type;
355};
356
357#define AMDGPU_MAX_BL_LEVEL 0xFF
358
359#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
360
361struct amdgpu_backlight_privdata {
362 struct amdgpu_encoder *encoder;
363 uint8_t negative;
364};
365
366#endif
367
368struct amdgpu_atom_ss {
369 uint16_t percentage;
370 uint16_t percentage_divider;
371 uint8_t type;
372 uint16_t step;
373 uint8_t delay;
374 uint8_t range;
375 uint8_t refdiv;
376 /* asic_ss */
377 uint16_t rate;
378 uint16_t amount;
379};
380
381struct amdgpu_crtc {
382 struct drm_crtc base;
383 int crtc_id;
384 bool enabled;
385 bool can_tile;
386 uint32_t crtc_offset;
387 struct drm_gem_object *cursor_bo;
388 uint64_t cursor_addr;
389 int cursor_x;
390 int cursor_y;
391 int cursor_hot_x;
392 int cursor_hot_y;
393 int cursor_width;
394 int cursor_height;
395 int max_cursor_width;
396 int max_cursor_height;
397 enum amdgpu_rmx_type rmx_type;
398 u8 h_border;
399 u8 v_border;
400 fixed20_12 vsc;
401 fixed20_12 hsc;
402 struct drm_display_mode native_mode;
403 u32 pll_id;
404 /* page flipping */
405 struct amdgpu_flip_work *pflip_works;
406 enum amdgpu_flip_status pflip_status;
407 int deferred_flip_completion;
408 /* parameters access from DM IRQ handler */
409 struct dm_irq_params dm_irq_params;
410 /* pll sharing */
411 struct amdgpu_atom_ss ss;
412 bool ss_enabled;
413 u32 adjusted_clock;
414 int bpc;
415 u32 pll_reference_div;
416 u32 pll_post_div;
417 u32 pll_flags;
418 struct drm_encoder *encoder;
419 struct drm_connector *connector;
420 /* for dpm */
421 u32 line_time;
422 u32 wm_low;
423 u32 wm_high;
424 u32 lb_vblank_lead_lines;
425 struct drm_display_mode hw_mode;
426 /* for virtual dce */
427 struct hrtimer vblank_timer;
428 enum amdgpu_interrupt_state vsync_timer_enabled;
429
430 int otg_inst;
431 struct drm_pending_vblank_event *event;
432};
433
434struct amdgpu_encoder_atom_dig {
435 bool linkb;
436 /* atom dig */
437 bool coherent_mode;
438 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
439 /* atom lvds/edp */
440 uint32_t lcd_misc;
441 uint16_t panel_pwr_delay;
442 uint32_t lcd_ss_id;
443 /* panel mode */
444 struct drm_display_mode native_mode;
445 struct backlight_device *bl_dev;
446 int dpms_mode;
447 uint8_t backlight_level;
448 int panel_mode;
449 struct amdgpu_afmt *afmt;
450};
451
452struct amdgpu_encoder {
453 struct drm_encoder base;
454 uint32_t encoder_enum;
455 uint32_t encoder_id;
456 uint32_t devices;
457 uint32_t active_device;
458 uint32_t flags;
459 uint32_t pixel_clock;
460 enum amdgpu_rmx_type rmx_type;
461 enum amdgpu_underscan_type underscan_type;
462 uint32_t underscan_hborder;
463 uint32_t underscan_vborder;
464 struct drm_display_mode native_mode;
465 void *enc_priv;
466 int audio_polling_active;
467 bool is_ext_encoder;
468 u16 caps;
469};
470
471struct amdgpu_connector_atom_dig {
472 /* displayport */
473 u8 dpcd[DP_RECEIVER_CAP_SIZE];
474 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
475 u8 dp_sink_type;
476 int dp_clock;
477 int dp_lane_count;
478 bool edp_on;
479};
480
481struct amdgpu_gpio_rec {
482 bool valid;
483 u8 id;
484 u32 reg;
485 u32 mask;
486 u32 shift;
487};
488
489struct amdgpu_hpd {
490 enum amdgpu_hpd_id hpd;
491 u8 plugged_state;
492 struct amdgpu_gpio_rec gpio;
493};
494
495struct amdgpu_router {
496 u32 router_id;
497 struct amdgpu_i2c_bus_rec i2c_info;
498 u8 i2c_addr;
499 /* i2c mux */
500 bool ddc_valid;
501 u8 ddc_mux_type;
502 u8 ddc_mux_control_pin;
503 u8 ddc_mux_state;
504 /* clock/data mux */
505 bool cd_valid;
506 u8 cd_mux_type;
507 u8 cd_mux_control_pin;
508 u8 cd_mux_state;
509};
510
511enum amdgpu_connector_audio {
512 AMDGPU_AUDIO_DISABLE = 0,
513 AMDGPU_AUDIO_ENABLE = 1,
514 AMDGPU_AUDIO_AUTO = 2
515};
516
517enum amdgpu_connector_dither {
518 AMDGPU_FMT_DITHER_DISABLE = 0,
519 AMDGPU_FMT_DITHER_ENABLE = 1,
520};
521
522struct amdgpu_dm_dp_aux {
523 struct drm_dp_aux aux;
524 struct ddc_service *ddc_service;
525};
526
527struct amdgpu_i2c_adapter {
528 struct i2c_adapter base;
529
530 struct ddc_service *ddc_service;
531};
532
533#define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
534
535struct amdgpu_connector {
536 struct drm_connector base;
537 uint32_t connector_id;
538 uint32_t devices;
539 struct amdgpu_i2c_chan *ddc_bus;
540 /* some systems have an hdmi and vga port with a shared ddc line */
541 bool shared_ddc;
542 bool use_digital;
543 /* we need to mind the EDID between detect
544 and get modes due to analog/digital/tvencoder */
545 struct edid *edid;
546 void *con_priv;
547 bool dac_load_detect;
548 bool detected_by_load; /* if the connection status was determined by load */
549 uint16_t connector_object_id;
550 struct amdgpu_hpd hpd;
551 struct amdgpu_router router;
552 struct amdgpu_i2c_chan *router_bus;
553 enum amdgpu_connector_audio audio;
554 enum amdgpu_connector_dither dither;
555 unsigned pixelclock_for_modeset;
556};
557
558/* TODO: start to use this struct and remove same field from base one */
559struct amdgpu_mst_connector {
560 struct amdgpu_connector base;
561
562 struct drm_dp_mst_topology_mgr mst_mgr;
563 struct amdgpu_dm_dp_aux dm_dp_aux;
564 struct drm_dp_mst_port *port;
565 struct amdgpu_connector *mst_port;
566 bool is_mst_connector;
567 struct amdgpu_encoder *mst_encoder;
568};
569
570#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
571 ((em) == ATOM_ENCODER_MODE_DP_MST))
572
573/* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
574#define DRM_SCANOUTPOS_VALID (1 << 0)
575#define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
576#define DRM_SCANOUTPOS_ACCURATE (1 << 2)
577#define USE_REAL_VBLANKSTART (1 << 30)
578#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
579
580void amdgpu_link_encoder_connector(struct drm_device *dev);
581
582struct drm_connector *
583amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
584struct drm_connector *
585amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
586bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
587 u32 pixel_clock);
588
589u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
590struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
591
592bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
593 bool use_aux);
594
595void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
596
597int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
598 unsigned int pipe, unsigned int flags, int *vpos,
599 int *hpos, ktime_t *stime, ktime_t *etime,
600 const struct drm_display_mode *mode);
601
602int amdgpu_display_framebuffer_init(struct drm_device *dev,
603 struct amdgpu_framebuffer *rfb,
604 const struct drm_mode_fb_cmd2 *mode_cmd,
605 struct drm_gem_object *obj);
606
607int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
608
609void amdgpu_enc_destroy(struct drm_encoder *encoder);
610void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
611bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
612 const struct drm_display_mode *mode,
613 struct drm_display_mode *adjusted_mode);
614void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
615 struct drm_display_mode *adjusted_mode);
616int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
617
618bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
619 bool in_vblank_irq, int *vpos,
620 int *hpos, ktime_t *stime, ktime_t *etime,
621 const struct drm_display_mode *mode);
622
623/* fbdev layer */
624int amdgpu_fbdev_init(struct amdgpu_device *adev);
625void amdgpu_fbdev_fini(struct amdgpu_device *adev);
626void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
627int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
628bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
629
630int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
631
632/* amdgpu_display.c */
633void amdgpu_display_print_display_setup(struct drm_device *dev);
634int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
635int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
636 struct drm_modeset_acquire_ctx *ctx);
637int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
638 struct drm_framebuffer *fb,
639 struct drm_pending_vblank_event *event,
640 uint32_t page_flip_flags, uint32_t target,
641 struct drm_modeset_acquire_ctx *ctx);
642extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
643
644#endif