tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 BayLibre, SAS
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Amlogic Meson DWMAC Ethernet controller
9
10maintainers:
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13
14# We need a select here so we don't match all nodes with 'snps,dwmac'
15select:
16 properties:
17 compatible:
18 contains:
19 enum:
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
24 - amlogic,meson-axg-dwmac
25 - amlogic,meson-g12a-dwmac
26 required:
27 - compatible
28
29allOf:
30 - $ref: "snps,dwmac.yaml#"
31 - if:
32 properties:
33 compatible:
34 contains:
35 enum:
36 - amlogic,meson8b-dwmac
37 - amlogic,meson8m2-dwmac
38 - amlogic,meson-gxbb-dwmac
39 - amlogic,meson-axg-dwmac
40 - amlogic,meson-g12a-dwmac
41
42 then:
43 properties:
44 clocks:
45 minItems: 3
46 maxItems: 4
47 items:
48 - description: GMAC main clock
49 - description: First parent clock of the internal mux
50 - description: Second parent clock of the internal mux
51 - description: The clock which drives the timing adjustment logic
52
53 clock-names:
54 minItems: 3
55 maxItems: 4
56 items:
57 - const: stmmaceth
58 - const: clkin0
59 - const: clkin1
60 - const: timing-adjustment
61
62 amlogic,tx-delay-ns:
63 $ref: /schemas/types.yaml#definitions/uint32
64 description:
65 The internal RGMII TX clock delay (provided by this driver) in
66 nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
67 When phy-mode is set to "rgmii" then the TX delay should be
68 explicitly configured. When not configured a fallback of 2ns is
69 used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
70 the TX clock delay is already provided by the PHY. In that case
71 this property should be set to 0ns (which disables the TX clock
72 delay in the MAC to prevent the clock from going off because both
73 PHY and MAC are adding a delay).
74 Any configuration is ignored when the phy-mode is set to "rmii".
75
76 amlogic,rx-delay-ns:
77 enum:
78 - 0
79 - 2
80 default: 0
81 description:
82 The internal RGMII RX clock delay (provided by this IP block) in
83 nanoseconds. When phy-mode is set to "rgmii" then the RX delay
84 should be explicitly configured. When the phy-mode is set to
85 either "rgmii-id" or "rgmii-rxid" the RX clock delay is already
86 provided by the PHY. Any configuration is ignored when the
87 phy-mode is set to "rmii".
88
89properties:
90 compatible:
91 additionalItems: true
92 maxItems: 3
93 items:
94 - enum:
95 - amlogic,meson6-dwmac
96 - amlogic,meson8b-dwmac
97 - amlogic,meson8m2-dwmac
98 - amlogic,meson-gxbb-dwmac
99 - amlogic,meson-axg-dwmac
100 - amlogic,meson-g12a-dwmac
101 contains:
102 enum:
103 - snps,dwmac-3.70a
104 - snps,dwmac
105
106 reg:
107 items:
108 - description:
109 The first register range should be the one of the DWMAC controller
110 - description:
111 The second range is is for the Amlogic specific configuration
112 (for example the PRG_ETHERNET register range on Meson8b and newer)
113
114required:
115 - compatible
116 - reg
117 - interrupts
118 - interrupt-names
119 - clocks
120 - clock-names
121 - phy-mode
122
123unevaluatedProperties: false
124
125examples:
126 - |
127 ethmac: ethernet@c9410000 {
128 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
129 reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
130 interrupts = <8>;
131 interrupt-names = "macirq";
132 clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
133 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
134 phy-mode = "rgmii";
135 };