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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2019 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13#ifndef __FIRMWARE_ZYNQMP_H__
14#define __FIRMWARE_ZYNQMP_H__
15
16#define ZYNQMP_PM_VERSION_MAJOR 1
17#define ZYNQMP_PM_VERSION_MINOR 0
18
19#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
21
22#define ZYNQMP_TZ_VERSION_MAJOR 1
23#define ZYNQMP_TZ_VERSION_MINOR 0
24
25#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
27
28/* SMC SIP service Call Function Identifier Prefix */
29#define PM_SIP_SVC 0xC2000000
30#define PM_GET_TRUSTZONE_VERSION 0xa03
31#define PM_SET_SUSPEND_MODE 0xa02
32#define GET_CALLBACK_DATA 0xa01
33
34/* Number of 32bits values in payload */
35#define PAYLOAD_ARG_CNT 4U
36
37/* Number of arguments for a callback */
38#define CB_ARG_CNT 4
39
40/* Payload size (consists of callback API ID + arguments) */
41#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
42
43#define ZYNQMP_PM_MAX_QOS 100U
44
45#define GSS_NUM_REGS (4)
46
47/* Node capabilities */
48#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
49#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
50#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
51#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
52
53/* Feature check status */
54#define PM_FEATURE_INVALID -1
55#define PM_FEATURE_UNCHECKED 0
56
57/*
58 * Firmware FPGA Manager flags
59 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
60 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
61 */
62#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
63#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
64
65enum pm_api_id {
66 PM_GET_API_VERSION = 1,
67 PM_SYSTEM_SHUTDOWN = 12,
68 PM_REQUEST_NODE = 13,
69 PM_RELEASE_NODE,
70 PM_SET_REQUIREMENT,
71 PM_RESET_ASSERT = 17,
72 PM_RESET_GET_STATUS,
73 PM_PM_INIT_FINALIZE = 21,
74 PM_FPGA_LOAD,
75 PM_FPGA_GET_STATUS,
76 PM_GET_CHIPID = 24,
77 PM_IOCTL = 34,
78 PM_QUERY_DATA,
79 PM_CLOCK_ENABLE,
80 PM_CLOCK_DISABLE,
81 PM_CLOCK_GETSTATE,
82 PM_CLOCK_SETDIVIDER,
83 PM_CLOCK_GETDIVIDER,
84 PM_CLOCK_SETRATE,
85 PM_CLOCK_GETRATE,
86 PM_CLOCK_SETPARENT,
87 PM_CLOCK_GETPARENT,
88 PM_SECURE_AES = 47,
89 PM_FEATURE_CHECK = 63,
90 PM_API_MAX,
91};
92
93/* PMU-FW return status codes */
94enum pm_ret_status {
95 XST_PM_SUCCESS = 0,
96 XST_PM_NO_FEATURE = 19,
97 XST_PM_INTERNAL = 2000,
98 XST_PM_CONFLICT,
99 XST_PM_NO_ACCESS,
100 XST_PM_INVALID_NODE,
101 XST_PM_DOUBLE_REQ,
102 XST_PM_ABORT_SUSPEND,
103 XST_PM_MULT_USER = 2008,
104};
105
106enum pm_ioctl_id {
107 IOCTL_SD_DLL_RESET = 6,
108 IOCTL_SET_SD_TAPDELAY,
109 IOCTL_SET_PLL_FRAC_MODE,
110 IOCTL_GET_PLL_FRAC_MODE,
111 IOCTL_SET_PLL_FRAC_DATA,
112 IOCTL_GET_PLL_FRAC_DATA,
113 IOCTL_WRITE_GGS = 12,
114 IOCTL_READ_GGS = 13,
115 IOCTL_WRITE_PGGS = 14,
116 IOCTL_READ_PGGS = 15,
117 /* Set healthy bit value */
118 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
119};
120
121enum pm_query_id {
122 PM_QID_INVALID,
123 PM_QID_CLOCK_GET_NAME,
124 PM_QID_CLOCK_GET_TOPOLOGY,
125 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
126 PM_QID_CLOCK_GET_PARENTS,
127 PM_QID_CLOCK_GET_ATTRIBUTES,
128 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
129 PM_QID_CLOCK_GET_MAX_DIVISOR,
130};
131
132enum zynqmp_pm_reset_action {
133 PM_RESET_ACTION_RELEASE,
134 PM_RESET_ACTION_ASSERT,
135 PM_RESET_ACTION_PULSE,
136};
137
138enum zynqmp_pm_reset {
139 ZYNQMP_PM_RESET_START = 1000,
140 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
141 ZYNQMP_PM_RESET_PCIE_BRIDGE,
142 ZYNQMP_PM_RESET_PCIE_CTRL,
143 ZYNQMP_PM_RESET_DP,
144 ZYNQMP_PM_RESET_SWDT_CRF,
145 ZYNQMP_PM_RESET_AFI_FM5,
146 ZYNQMP_PM_RESET_AFI_FM4,
147 ZYNQMP_PM_RESET_AFI_FM3,
148 ZYNQMP_PM_RESET_AFI_FM2,
149 ZYNQMP_PM_RESET_AFI_FM1,
150 ZYNQMP_PM_RESET_AFI_FM0,
151 ZYNQMP_PM_RESET_GDMA,
152 ZYNQMP_PM_RESET_GPU_PP1,
153 ZYNQMP_PM_RESET_GPU_PP0,
154 ZYNQMP_PM_RESET_GPU,
155 ZYNQMP_PM_RESET_GT,
156 ZYNQMP_PM_RESET_SATA,
157 ZYNQMP_PM_RESET_ACPU3_PWRON,
158 ZYNQMP_PM_RESET_ACPU2_PWRON,
159 ZYNQMP_PM_RESET_ACPU1_PWRON,
160 ZYNQMP_PM_RESET_ACPU0_PWRON,
161 ZYNQMP_PM_RESET_APU_L2,
162 ZYNQMP_PM_RESET_ACPU3,
163 ZYNQMP_PM_RESET_ACPU2,
164 ZYNQMP_PM_RESET_ACPU1,
165 ZYNQMP_PM_RESET_ACPU0,
166 ZYNQMP_PM_RESET_DDR,
167 ZYNQMP_PM_RESET_APM_FPD,
168 ZYNQMP_PM_RESET_SOFT,
169 ZYNQMP_PM_RESET_GEM0,
170 ZYNQMP_PM_RESET_GEM1,
171 ZYNQMP_PM_RESET_GEM2,
172 ZYNQMP_PM_RESET_GEM3,
173 ZYNQMP_PM_RESET_QSPI,
174 ZYNQMP_PM_RESET_UART0,
175 ZYNQMP_PM_RESET_UART1,
176 ZYNQMP_PM_RESET_SPI0,
177 ZYNQMP_PM_RESET_SPI1,
178 ZYNQMP_PM_RESET_SDIO0,
179 ZYNQMP_PM_RESET_SDIO1,
180 ZYNQMP_PM_RESET_CAN0,
181 ZYNQMP_PM_RESET_CAN1,
182 ZYNQMP_PM_RESET_I2C0,
183 ZYNQMP_PM_RESET_I2C1,
184 ZYNQMP_PM_RESET_TTC0,
185 ZYNQMP_PM_RESET_TTC1,
186 ZYNQMP_PM_RESET_TTC2,
187 ZYNQMP_PM_RESET_TTC3,
188 ZYNQMP_PM_RESET_SWDT_CRL,
189 ZYNQMP_PM_RESET_NAND,
190 ZYNQMP_PM_RESET_ADMA,
191 ZYNQMP_PM_RESET_GPIO,
192 ZYNQMP_PM_RESET_IOU_CC,
193 ZYNQMP_PM_RESET_TIMESTAMP,
194 ZYNQMP_PM_RESET_RPU_R50,
195 ZYNQMP_PM_RESET_RPU_R51,
196 ZYNQMP_PM_RESET_RPU_AMBA,
197 ZYNQMP_PM_RESET_OCM,
198 ZYNQMP_PM_RESET_RPU_PGE,
199 ZYNQMP_PM_RESET_USB0_CORERESET,
200 ZYNQMP_PM_RESET_USB1_CORERESET,
201 ZYNQMP_PM_RESET_USB0_HIBERRESET,
202 ZYNQMP_PM_RESET_USB1_HIBERRESET,
203 ZYNQMP_PM_RESET_USB0_APB,
204 ZYNQMP_PM_RESET_USB1_APB,
205 ZYNQMP_PM_RESET_IPI,
206 ZYNQMP_PM_RESET_APM_LPD,
207 ZYNQMP_PM_RESET_RTC,
208 ZYNQMP_PM_RESET_SYSMON,
209 ZYNQMP_PM_RESET_AFI_FM6,
210 ZYNQMP_PM_RESET_LPD_SWDT,
211 ZYNQMP_PM_RESET_FPD,
212 ZYNQMP_PM_RESET_RPU_DBG1,
213 ZYNQMP_PM_RESET_RPU_DBG0,
214 ZYNQMP_PM_RESET_DBG_LPD,
215 ZYNQMP_PM_RESET_DBG_FPD,
216 ZYNQMP_PM_RESET_APLL,
217 ZYNQMP_PM_RESET_DPLL,
218 ZYNQMP_PM_RESET_VPLL,
219 ZYNQMP_PM_RESET_IOPLL,
220 ZYNQMP_PM_RESET_RPLL,
221 ZYNQMP_PM_RESET_GPO3_PL_0,
222 ZYNQMP_PM_RESET_GPO3_PL_1,
223 ZYNQMP_PM_RESET_GPO3_PL_2,
224 ZYNQMP_PM_RESET_GPO3_PL_3,
225 ZYNQMP_PM_RESET_GPO3_PL_4,
226 ZYNQMP_PM_RESET_GPO3_PL_5,
227 ZYNQMP_PM_RESET_GPO3_PL_6,
228 ZYNQMP_PM_RESET_GPO3_PL_7,
229 ZYNQMP_PM_RESET_GPO3_PL_8,
230 ZYNQMP_PM_RESET_GPO3_PL_9,
231 ZYNQMP_PM_RESET_GPO3_PL_10,
232 ZYNQMP_PM_RESET_GPO3_PL_11,
233 ZYNQMP_PM_RESET_GPO3_PL_12,
234 ZYNQMP_PM_RESET_GPO3_PL_13,
235 ZYNQMP_PM_RESET_GPO3_PL_14,
236 ZYNQMP_PM_RESET_GPO3_PL_15,
237 ZYNQMP_PM_RESET_GPO3_PL_16,
238 ZYNQMP_PM_RESET_GPO3_PL_17,
239 ZYNQMP_PM_RESET_GPO3_PL_18,
240 ZYNQMP_PM_RESET_GPO3_PL_19,
241 ZYNQMP_PM_RESET_GPO3_PL_20,
242 ZYNQMP_PM_RESET_GPO3_PL_21,
243 ZYNQMP_PM_RESET_GPO3_PL_22,
244 ZYNQMP_PM_RESET_GPO3_PL_23,
245 ZYNQMP_PM_RESET_GPO3_PL_24,
246 ZYNQMP_PM_RESET_GPO3_PL_25,
247 ZYNQMP_PM_RESET_GPO3_PL_26,
248 ZYNQMP_PM_RESET_GPO3_PL_27,
249 ZYNQMP_PM_RESET_GPO3_PL_28,
250 ZYNQMP_PM_RESET_GPO3_PL_29,
251 ZYNQMP_PM_RESET_GPO3_PL_30,
252 ZYNQMP_PM_RESET_GPO3_PL_31,
253 ZYNQMP_PM_RESET_RPU_LS,
254 ZYNQMP_PM_RESET_PS_ONLY,
255 ZYNQMP_PM_RESET_PL,
256 ZYNQMP_PM_RESET_PS_PL0,
257 ZYNQMP_PM_RESET_PS_PL1,
258 ZYNQMP_PM_RESET_PS_PL2,
259 ZYNQMP_PM_RESET_PS_PL3,
260 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
261};
262
263enum zynqmp_pm_suspend_reason {
264 SUSPEND_POWER_REQUEST = 201,
265 SUSPEND_ALERT,
266 SUSPEND_SYSTEM_SHUTDOWN,
267};
268
269enum zynqmp_pm_request_ack {
270 ZYNQMP_PM_REQUEST_ACK_NO = 1,
271 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
272 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
273};
274
275enum pm_node_id {
276 NODE_SD_0 = 39,
277 NODE_SD_1,
278};
279
280enum tap_delay_type {
281 PM_TAPDELAY_INPUT = 0,
282 PM_TAPDELAY_OUTPUT,
283};
284
285enum dll_reset_type {
286 PM_DLL_RESET_ASSERT,
287 PM_DLL_RESET_RELEASE,
288 PM_DLL_RESET_PULSE,
289};
290
291enum zynqmp_pm_shutdown_type {
292 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
293 ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
294 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
295};
296
297enum zynqmp_pm_shutdown_subtype {
298 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
299 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
300 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
301};
302
303/**
304 * struct zynqmp_pm_query_data - PM query data
305 * @qid: query ID
306 * @arg1: Argument 1 of query data
307 * @arg2: Argument 2 of query data
308 * @arg3: Argument 3 of query data
309 */
310struct zynqmp_pm_query_data {
311 u32 qid;
312 u32 arg1;
313 u32 arg2;
314 u32 arg3;
315};
316
317
318int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
319 u32 arg2, u32 arg3, u32 *ret_payload);
320
321#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
322int zynqmp_pm_get_api_version(u32 *version);
323int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
324int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
325int zynqmp_pm_clock_enable(u32 clock_id);
326int zynqmp_pm_clock_disable(u32 clock_id);
327int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
328int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
329int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
330int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
331int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
332int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
333int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
334int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
335int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
336int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
337int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
338int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
339int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
340int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
341 const enum zynqmp_pm_reset_action assert_flag);
342int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
343int zynqmp_pm_init_finalize(void);
344int zynqmp_pm_set_suspend_mode(u32 mode);
345int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
346 const u32 qos, const enum zynqmp_pm_request_ack ack);
347int zynqmp_pm_release_node(const u32 node);
348int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
349 const u32 qos,
350 const enum zynqmp_pm_request_ack ack);
351int zynqmp_pm_aes_engine(const u64 address, u32 *out);
352int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
353int zynqmp_pm_fpga_get_status(u32 *value);
354int zynqmp_pm_write_ggs(u32 index, u32 value);
355int zynqmp_pm_read_ggs(u32 index, u32 *value);
356int zynqmp_pm_write_pggs(u32 index, u32 value);
357int zynqmp_pm_read_pggs(u32 index, u32 *value);
358int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
359int zynqmp_pm_set_boot_health_status(u32 value);
360#else
361static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
362{
363 return ERR_PTR(-ENODEV);
364}
365static inline int zynqmp_pm_get_api_version(u32 *version)
366{
367 return -ENODEV;
368}
369static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
370{
371 return -ENODEV;
372}
373static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
374 u32 *out)
375{
376 return -ENODEV;
377}
378static inline int zynqmp_pm_clock_enable(u32 clock_id)
379{
380 return -ENODEV;
381}
382static inline int zynqmp_pm_clock_disable(u32 clock_id)
383{
384 return -ENODEV;
385}
386static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
387{
388 return -ENODEV;
389}
390static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
391{
392 return -ENODEV;
393}
394static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
395{
396 return -ENODEV;
397}
398static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
399{
400 return -ENODEV;
401}
402static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
403{
404 return -ENODEV;
405}
406static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
407{
408 return -ENODEV;
409}
410static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
411{
412 return -ENODEV;
413}
414static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
415{
416 return -ENODEV;
417}
418static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
419{
420 return -ENODEV;
421}
422static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
423{
424 return -ENODEV;
425}
426static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
427{
428 return -ENODEV;
429}
430static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
431{
432 return -ENODEV;
433}
434static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
435{
436 return -ENODEV;
437}
438static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
439 const enum zynqmp_pm_reset_action assert_flag)
440{
441 return -ENODEV;
442}
443static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
444 u32 *status)
445{
446 return -ENODEV;
447}
448static inline int zynqmp_pm_init_finalize(void)
449{
450 return -ENODEV;
451}
452static inline int zynqmp_pm_set_suspend_mode(u32 mode)
453{
454 return -ENODEV;
455}
456static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
457 const u32 qos,
458 const enum zynqmp_pm_request_ack ack)
459{
460 return -ENODEV;
461}
462static inline int zynqmp_pm_release_node(const u32 node)
463{
464 return -ENODEV;
465}
466static inline int zynqmp_pm_set_requirement(const u32 node,
467 const u32 capabilities,
468 const u32 qos,
469 const enum zynqmp_pm_request_ack ack)
470{
471 return -ENODEV;
472}
473static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
474{
475 return -ENODEV;
476}
477static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
478 const u32 flags)
479{
480 return -ENODEV;
481}
482static inline int zynqmp_pm_fpga_get_status(u32 *value)
483{
484 return -ENODEV;
485}
486static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
487{
488 return -ENODEV;
489}
490static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
491{
492 return -ENODEV;
493}
494static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
495{
496 return -ENODEV;
497}
498static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
499{
500 return -ENODEV;
501}
502static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
503{
504 return -ENODEV;
505}
506static inline int zynqmp_pm_set_boot_health_status(u32 value)
507{
508 return -ENODEV;
509}
510#endif
511
512#endif /* __FIRMWARE_ZYNQMP_H__ */