Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
71
72/* insert a value to a struct */
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 MLX5_SET(typ, p, fld[idx], v); \
85} while (0)
86
87#define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 << __mlx5_dw_bit_off(typ, fld))); \
93} while (0)
94
95#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97__mlx5_mask(typ, fld))
98
99#define MLX5_GET_PR(typ, p, fld) ({ \
100 u32 ___t = MLX5_GET(typ, p, fld); \
101 pr_debug(#fld " = 0x%x\n", ___t); \
102 ___t; \
103})
104
105#define __MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108} while (0)
109
110#define MLX5_SET64(typ, p, fld, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld, v); \
113} while (0)
114
115#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 __MLX5_SET64(typ, p, fld[idx], v); \
118} while (0)
119
120#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET64_PR(typ, p, fld) ({ \
123 u64 ___t = MLX5_GET64(typ, p, fld); \
124 pr_debug(#fld " = 0x%llx\n", ___t); \
125 ___t; \
126})
127
128#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130__mlx5_mask16(typ, fld))
131
132#define MLX5_SET16(typ, p, fld, v) do { \
133 u16 _v = v; \
134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 << __mlx5_16_bit_off(typ, fld))); \
139} while (0)
140
141/* Big endian getters */
142#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 __mlx5_64_off(typ, fld)))
144
145#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
146 type_t tmp; \
147 switch (sizeof(tmp)) { \
148 case sizeof(u8): \
149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
150 break; \
151 case sizeof(u16): \
152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 break; \
154 case sizeof(u32): \
155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 break; \
157 case sizeof(u64): \
158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 break; \
160 } \
161 tmp; \
162 })
163
164enum mlx5_inline_modes {
165 MLX5_INLINE_MODE_NONE,
166 MLX5_INLINE_MODE_L2,
167 MLX5_INLINE_MODE_IP,
168 MLX5_INLINE_MODE_TCP_UDP,
169};
170
171enum {
172 MLX5_MAX_COMMANDS = 32,
173 MLX5_CMD_DATA_BLOCK_SIZE = 512,
174 MLX5_PCI_CMD_XPORT = 7,
175 MLX5_MKEY_BSF_OCTO_SIZE = 4,
176 MLX5_MAX_PSVS = 4,
177};
178
179enum {
180 MLX5_EXTENDED_UD_AV = 0x80000000,
181};
182
183enum {
184 MLX5_CQ_STATE_ARMED = 9,
185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
186 MLX5_CQ_STATE_FIRED = 0xa,
187};
188
189enum {
190 MLX5_STAT_RATE_OFFSET = 5,
191};
192
193enum {
194 MLX5_INLINE_SEG = 0x80000000,
195};
196
197enum {
198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199};
200
201enum {
202 MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 MLX5_MAX_LOG_PKEY_TABLE = 5,
204};
205
206enum {
207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208};
209
210enum {
211 MLX5_PFAULT_SUBTYPE_WQE = 0,
212 MLX5_PFAULT_SUBTYPE_RDMA = 1,
213};
214
215enum wqe_page_fault_type {
216 MLX5_WQE_PF_TYPE_RMP = 0,
217 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
218 MLX5_WQE_PF_TYPE_RESP = 2,
219 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
220};
221
222enum {
223 MLX5_PERM_LOCAL_READ = 1 << 2,
224 MLX5_PERM_LOCAL_WRITE = 1 << 3,
225 MLX5_PERM_REMOTE_READ = 1 << 4,
226 MLX5_PERM_REMOTE_WRITE = 1 << 5,
227 MLX5_PERM_ATOMIC = 1 << 6,
228 MLX5_PERM_UMR_EN = 1 << 7,
229};
230
231enum {
232 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
233 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
234 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
235 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
236 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
237};
238
239enum {
240 MLX5_EN_RD = (u64)1,
241 MLX5_EN_WR = (u64)2
242};
243
244enum {
245 MLX5_ADAPTER_PAGE_SHIFT = 12,
246 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
247};
248
249enum {
250 MLX5_BFREGS_PER_UAR = 4,
251 MLX5_MAX_UARS = 1 << 8,
252 MLX5_NON_FP_BFREGS_PER_UAR = 2,
253 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
254 MLX5_NON_FP_BFREGS_PER_UAR,
255 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
256 MLX5_NON_FP_BFREGS_PER_UAR,
257 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
258 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
259 MLX5_MIN_DYN_BFREGS = 512,
260 MLX5_MAX_DYN_BFREGS = 1024,
261};
262
263enum {
264 MLX5_MKEY_MASK_LEN = 1ull << 0,
265 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
266 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
267 MLX5_MKEY_MASK_PD = 1ull << 7,
268 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
269 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
270 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
271 MLX5_MKEY_MASK_KEY = 1ull << 13,
272 MLX5_MKEY_MASK_QPN = 1ull << 14,
273 MLX5_MKEY_MASK_LR = 1ull << 17,
274 MLX5_MKEY_MASK_LW = 1ull << 18,
275 MLX5_MKEY_MASK_RR = 1ull << 19,
276 MLX5_MKEY_MASK_RW = 1ull << 20,
277 MLX5_MKEY_MASK_A = 1ull << 21,
278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
279 MLX5_MKEY_MASK_FREE = 1ull << 29,
280};
281
282enum {
283 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
284
285 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
286 MLX5_UMR_CHECK_FREE = (2 << 5),
287
288 MLX5_UMR_INLINE = (1 << 7),
289};
290
291#define MLX5_UMR_MTT_ALIGNMENT 0x40
292#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
293#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
294
295#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
296
297enum {
298 MLX5_EVENT_QUEUE_TYPE_QP = 0,
299 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
300 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
301 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
302};
303
304/* mlx5 components can subscribe to any one of these events via
305 * mlx5_eq_notifier_register API.
306 */
307enum mlx5_event {
308 /* Special value to subscribe to any event */
309 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
310 /* HW events enum start: comp events are not subscribable */
311 MLX5_EVENT_TYPE_COMP = 0x0,
312 /* HW Async events enum start: subscribable events */
313 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
314 MLX5_EVENT_TYPE_COMM_EST = 0x02,
315 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
316 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
317 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
318
319 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
320 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
321 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
322 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
323 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
324 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
325
326 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
327 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
328 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
329 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
330 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
331 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
332 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
333 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
334 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
335
336 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
337 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
338
339 MLX5_EVENT_TYPE_CMD = 0x0a,
340 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
341
342 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
343 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
344
345 MLX5_EVENT_TYPE_HOST_PARAMS_CHANGE = 0xe,
346
347 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
348
349 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
350 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
351
352 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
353
354 MLX5_EVENT_TYPE_MAX = MLX5_EVENT_TYPE_DEVICE_TRACER + 1,
355};
356
357enum {
358 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
359 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
360};
361
362enum {
363 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
364};
365
366enum {
367 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
368 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
369 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
370 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
371 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
372 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
373 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
374};
375
376enum {
377 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
378 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
379 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
380 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
381 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
382 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
383 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
384 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
385 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
386 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
387 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
388 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
389};
390
391enum {
392 MLX5_ROCE_VERSION_1 = 0,
393 MLX5_ROCE_VERSION_2 = 2,
394};
395
396enum {
397 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
398 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
399};
400
401enum {
402 MLX5_ROCE_L3_TYPE_IPV4 = 0,
403 MLX5_ROCE_L3_TYPE_IPV6 = 1,
404};
405
406enum {
407 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
408 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
409};
410
411enum {
412 MLX5_OPCODE_NOP = 0x00,
413 MLX5_OPCODE_SEND_INVAL = 0x01,
414 MLX5_OPCODE_RDMA_WRITE = 0x08,
415 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
416 MLX5_OPCODE_SEND = 0x0a,
417 MLX5_OPCODE_SEND_IMM = 0x0b,
418 MLX5_OPCODE_LSO = 0x0e,
419 MLX5_OPCODE_RDMA_READ = 0x10,
420 MLX5_OPCODE_ATOMIC_CS = 0x11,
421 MLX5_OPCODE_ATOMIC_FA = 0x12,
422 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
423 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
424 MLX5_OPCODE_BIND_MW = 0x18,
425 MLX5_OPCODE_CONFIG_CMD = 0x1f,
426 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
427
428 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
429 MLX5_RECV_OPCODE_SEND = 0x01,
430 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
431 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
432
433 MLX5_CQE_OPCODE_ERROR = 0x1e,
434 MLX5_CQE_OPCODE_RESIZE = 0x16,
435
436 MLX5_OPCODE_SET_PSV = 0x20,
437 MLX5_OPCODE_GET_PSV = 0x21,
438 MLX5_OPCODE_CHECK_PSV = 0x22,
439 MLX5_OPCODE_RGET_PSV = 0x26,
440 MLX5_OPCODE_RCHECK_PSV = 0x27,
441
442 MLX5_OPCODE_UMR = 0x25,
443
444};
445
446enum {
447 MLX5_SET_PORT_RESET_QKEY = 0,
448 MLX5_SET_PORT_GUID0 = 16,
449 MLX5_SET_PORT_NODE_GUID = 17,
450 MLX5_SET_PORT_SYS_GUID = 18,
451 MLX5_SET_PORT_GID_TABLE = 19,
452 MLX5_SET_PORT_PKEY_TABLE = 20,
453};
454
455enum {
456 MLX5_BW_NO_LIMIT = 0,
457 MLX5_100_MBPS_UNIT = 3,
458 MLX5_GBPS_UNIT = 4,
459};
460
461enum {
462 MLX5_MAX_PAGE_SHIFT = 31
463};
464
465enum {
466 MLX5_CAP_OFF_CMDIF_CSUM = 46,
467};
468
469enum {
470 /*
471 * Max wqe size for rdma read is 512 bytes, so this
472 * limits our max_sge_rd as the wqe needs to fit:
473 * - ctrl segment (16 bytes)
474 * - rdma segment (16 bytes)
475 * - scatter elements (16 bytes each)
476 */
477 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
478};
479
480enum mlx5_odp_transport_cap_bits {
481 MLX5_ODP_SUPPORT_SEND = 1 << 31,
482 MLX5_ODP_SUPPORT_RECV = 1 << 30,
483 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
484 MLX5_ODP_SUPPORT_READ = 1 << 28,
485};
486
487struct mlx5_odp_caps {
488 char reserved[0x10];
489 struct {
490 __be32 rc_odp_caps;
491 __be32 uc_odp_caps;
492 __be32 ud_odp_caps;
493 } per_transport_caps;
494 char reserved2[0xe4];
495};
496
497struct mlx5_cmd_layout {
498 u8 type;
499 u8 rsvd0[3];
500 __be32 inlen;
501 __be64 in_ptr;
502 __be32 in[4];
503 __be32 out[4];
504 __be64 out_ptr;
505 __be32 outlen;
506 u8 token;
507 u8 sig;
508 u8 rsvd1;
509 u8 status_own;
510};
511
512struct health_buffer {
513 __be32 assert_var[5];
514 __be32 rsvd0[3];
515 __be32 assert_exit_ptr;
516 __be32 assert_callra;
517 __be32 rsvd1[2];
518 __be32 fw_ver;
519 __be32 hw_id;
520 __be32 rsvd2;
521 u8 irisc_index;
522 u8 synd;
523 __be16 ext_synd;
524};
525
526enum mlx5_cmd_addr_l_sz_offset {
527 MLX5_NIC_IFC_OFFSET = 8,
528};
529
530struct mlx5_init_seg {
531 __be32 fw_rev;
532 __be32 cmdif_rev_fw_sub;
533 __be32 rsvd0[2];
534 __be32 cmdq_addr_h;
535 __be32 cmdq_addr_l_sz;
536 __be32 cmd_dbell;
537 __be32 rsvd1[120];
538 __be32 initializing;
539 struct health_buffer health;
540 __be32 rsvd2[880];
541 __be32 internal_timer_h;
542 __be32 internal_timer_l;
543 __be32 rsvd3[2];
544 __be32 health_counter;
545 __be32 rsvd4[1019];
546 __be64 ieee1588_clk;
547 __be32 ieee1588_clk_type;
548 __be32 clr_intx;
549};
550
551struct mlx5_eqe_comp {
552 __be32 reserved[6];
553 __be32 cqn;
554};
555
556struct mlx5_eqe_qp_srq {
557 __be32 reserved1[5];
558 u8 type;
559 u8 reserved2[3];
560 __be32 qp_srq_n;
561};
562
563struct mlx5_eqe_cq_err {
564 __be32 cqn;
565 u8 reserved1[7];
566 u8 syndrome;
567};
568
569struct mlx5_eqe_port_state {
570 u8 reserved0[8];
571 u8 port;
572};
573
574struct mlx5_eqe_gpio {
575 __be32 reserved0[2];
576 __be64 gpio_event;
577};
578
579struct mlx5_eqe_congestion {
580 u8 type;
581 u8 rsvd0;
582 u8 congestion_level;
583};
584
585struct mlx5_eqe_stall_vl {
586 u8 rsvd0[3];
587 u8 port_vl;
588};
589
590struct mlx5_eqe_cmd {
591 __be32 vector;
592 __be32 rsvd[6];
593};
594
595struct mlx5_eqe_page_req {
596 __be16 ec_function;
597 __be16 func_id;
598 __be32 num_pages;
599 __be32 rsvd1[5];
600};
601
602struct mlx5_eqe_page_fault {
603 __be32 bytes_committed;
604 union {
605 struct {
606 u16 reserved1;
607 __be16 wqe_index;
608 u16 reserved2;
609 __be16 packet_length;
610 __be32 token;
611 u8 reserved4[8];
612 __be32 pftype_wq;
613 } __packed wqe;
614 struct {
615 __be32 r_key;
616 u16 reserved1;
617 __be16 packet_length;
618 __be32 rdma_op_len;
619 __be64 rdma_va;
620 __be32 pftype_token;
621 } __packed rdma;
622 } __packed;
623} __packed;
624
625struct mlx5_eqe_vport_change {
626 u8 rsvd0[2];
627 __be16 vport_num;
628 __be32 rsvd1[6];
629} __packed;
630
631struct mlx5_eqe_port_module {
632 u8 reserved_at_0[1];
633 u8 module;
634 u8 reserved_at_2[1];
635 u8 module_status;
636 u8 reserved_at_4[2];
637 u8 error_type;
638} __packed;
639
640struct mlx5_eqe_pps {
641 u8 rsvd0[3];
642 u8 pin;
643 u8 rsvd1[4];
644 union {
645 struct {
646 __be32 time_sec;
647 __be32 time_nsec;
648 };
649 struct {
650 __be64 time_stamp;
651 };
652 };
653 u8 rsvd2[12];
654} __packed;
655
656struct mlx5_eqe_dct {
657 __be32 reserved[6];
658 __be32 dctn;
659};
660
661struct mlx5_eqe_temp_warning {
662 __be64 sensor_warning_msb;
663 __be64 sensor_warning_lsb;
664} __packed;
665
666union ev_data {
667 __be32 raw[7];
668 struct mlx5_eqe_cmd cmd;
669 struct mlx5_eqe_comp comp;
670 struct mlx5_eqe_qp_srq qp_srq;
671 struct mlx5_eqe_cq_err cq_err;
672 struct mlx5_eqe_port_state port;
673 struct mlx5_eqe_gpio gpio;
674 struct mlx5_eqe_congestion cong;
675 struct mlx5_eqe_stall_vl stall_vl;
676 struct mlx5_eqe_page_req req_pages;
677 struct mlx5_eqe_page_fault page_fault;
678 struct mlx5_eqe_vport_change vport_change;
679 struct mlx5_eqe_port_module port_module;
680 struct mlx5_eqe_pps pps;
681 struct mlx5_eqe_dct dct;
682 struct mlx5_eqe_temp_warning temp_warning;
683} __packed;
684
685struct mlx5_eqe {
686 u8 rsvd0;
687 u8 type;
688 u8 rsvd1;
689 u8 sub_type;
690 __be32 rsvd2[7];
691 union ev_data data;
692 __be16 rsvd3;
693 u8 signature;
694 u8 owner;
695} __packed;
696
697struct mlx5_cmd_prot_block {
698 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
699 u8 rsvd0[48];
700 __be64 next;
701 __be32 block_num;
702 u8 rsvd1;
703 u8 token;
704 u8 ctrl_sig;
705 u8 sig;
706};
707
708enum {
709 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
710};
711
712struct mlx5_err_cqe {
713 u8 rsvd0[32];
714 __be32 srqn;
715 u8 rsvd1[18];
716 u8 vendor_err_synd;
717 u8 syndrome;
718 __be32 s_wqe_opcode_qpn;
719 __be16 wqe_counter;
720 u8 signature;
721 u8 op_own;
722};
723
724struct mlx5_cqe64 {
725 u8 outer_l3_tunneled;
726 u8 rsvd0;
727 __be16 wqe_id;
728 u8 lro_tcppsh_abort_dupack;
729 u8 lro_min_ttl;
730 __be16 lro_tcp_win;
731 __be32 lro_ack_seq_num;
732 __be32 rss_hash_result;
733 u8 rss_hash_type;
734 u8 ml_path;
735 u8 rsvd20[2];
736 __be16 check_sum;
737 __be16 slid;
738 __be32 flags_rqpn;
739 u8 hds_ip_ext;
740 u8 l4_l3_hdr_type;
741 __be16 vlan_info;
742 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
743 __be32 imm_inval_pkey;
744 u8 rsvd40[4];
745 __be32 byte_cnt;
746 __be32 timestamp_h;
747 __be32 timestamp_l;
748 __be32 sop_drop_qpn;
749 __be16 wqe_counter;
750 u8 signature;
751 u8 op_own;
752};
753
754struct mlx5_mini_cqe8 {
755 union {
756 __be32 rx_hash_result;
757 struct {
758 __be16 checksum;
759 __be16 rsvd;
760 };
761 struct {
762 __be16 wqe_counter;
763 u8 s_wqe_opcode;
764 u8 reserved;
765 } s_wqe_info;
766 };
767 __be32 byte_cnt;
768};
769
770enum {
771 MLX5_NO_INLINE_DATA,
772 MLX5_INLINE_DATA32_SEG,
773 MLX5_INLINE_DATA64_SEG,
774 MLX5_COMPRESSED,
775};
776
777enum {
778 MLX5_CQE_FORMAT_CSUM = 0x1,
779};
780
781#define MLX5_MINI_CQE_ARRAY_SIZE 8
782
783static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
784{
785 return (cqe->op_own >> 2) & 0x3;
786}
787
788static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
789{
790 return cqe->op_own >> 4;
791}
792
793static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
794{
795 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
796}
797
798static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
799{
800 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
801}
802
803static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
804{
805 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
806}
807
808static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
809{
810 return cqe->outer_l3_tunneled & 0x1;
811}
812
813static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
814{
815 return cqe->l4_l3_hdr_type & 0x1;
816}
817
818static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
819{
820 u32 hi, lo;
821
822 hi = be32_to_cpu(cqe->timestamp_h);
823 lo = be32_to_cpu(cqe->timestamp_l);
824
825 return (u64)lo | ((u64)hi << 32);
826}
827
828#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
829#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
830
831struct mpwrq_cqe_bc {
832 __be16 filler_consumed_strides;
833 __be16 byte_cnt;
834};
835
836static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
837{
838 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
839
840 return be16_to_cpu(bc->byte_cnt);
841}
842
843static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
844{
845 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
846}
847
848static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
849{
850 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
851
852 return mpwrq_get_cqe_bc_consumed_strides(bc);
853}
854
855static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
856{
857 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
858
859 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
860}
861
862static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
863{
864 return be16_to_cpu(cqe->wqe_counter);
865}
866
867enum {
868 CQE_L4_HDR_TYPE_NONE = 0x0,
869 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
870 CQE_L4_HDR_TYPE_UDP = 0x2,
871 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
872 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
873};
874
875enum {
876 CQE_RSS_HTYPE_IP = 0x3 << 2,
877 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
878 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
879 */
880 CQE_RSS_HTYPE_L4 = 0x3 << 6,
881 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
882 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
883 */
884};
885
886enum {
887 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
888 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
889 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
890};
891
892enum {
893 CQE_L2_OK = 1 << 0,
894 CQE_L3_OK = 1 << 1,
895 CQE_L4_OK = 1 << 2,
896};
897
898struct mlx5_sig_err_cqe {
899 u8 rsvd0[16];
900 __be32 expected_trans_sig;
901 __be32 actual_trans_sig;
902 __be32 expected_reftag;
903 __be32 actual_reftag;
904 __be16 syndrome;
905 u8 rsvd22[2];
906 __be32 mkey;
907 __be64 err_offset;
908 u8 rsvd30[8];
909 __be32 qpn;
910 u8 rsvd38[2];
911 u8 signature;
912 u8 op_own;
913};
914
915struct mlx5_wqe_srq_next_seg {
916 u8 rsvd0[2];
917 __be16 next_wqe_index;
918 u8 signature;
919 u8 rsvd1[11];
920};
921
922union mlx5_ext_cqe {
923 struct ib_grh grh;
924 u8 inl[64];
925};
926
927struct mlx5_cqe128 {
928 union mlx5_ext_cqe inl_grh;
929 struct mlx5_cqe64 cqe64;
930};
931
932enum {
933 MLX5_MKEY_STATUS_FREE = 1 << 6,
934};
935
936enum {
937 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
938 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
939 MLX5_MKEY_BSF_EN = 1 << 30,
940 MLX5_MKEY_LEN64 = 1 << 31,
941};
942
943struct mlx5_mkey_seg {
944 /* This is a two bit field occupying bits 31-30.
945 * bit 31 is always 0,
946 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
947 */
948 u8 status;
949 u8 pcie_control;
950 u8 flags;
951 u8 version;
952 __be32 qpn_mkey7_0;
953 u8 rsvd1[4];
954 __be32 flags_pd;
955 __be64 start_addr;
956 __be64 len;
957 __be32 bsfs_octo_size;
958 u8 rsvd2[16];
959 __be32 xlt_oct_size;
960 u8 rsvd3[3];
961 u8 log2_page_size;
962 u8 rsvd4[4];
963};
964
965#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
966
967enum {
968 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
969};
970
971enum {
972 VPORT_STATE_DOWN = 0x0,
973 VPORT_STATE_UP = 0x1,
974};
975
976enum {
977 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
978 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
979 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
980};
981
982enum {
983 MLX5_L3_PROT_TYPE_IPV4 = 0,
984 MLX5_L3_PROT_TYPE_IPV6 = 1,
985};
986
987enum {
988 MLX5_L4_PROT_TYPE_TCP = 0,
989 MLX5_L4_PROT_TYPE_UDP = 1,
990};
991
992enum {
993 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
994 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
995 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
996 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
997 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
998};
999
1000enum {
1001 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1002 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1003 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1004
1005};
1006
1007enum {
1008 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1009 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1010};
1011
1012enum {
1013 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1014 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1015 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1016};
1017
1018enum mlx5_list_type {
1019 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1020 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1021 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1022};
1023
1024enum {
1025 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1026 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1027};
1028
1029enum mlx5_wol_mode {
1030 MLX5_WOL_DISABLE = 0,
1031 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1032 MLX5_WOL_MAGIC = 1 << 2,
1033 MLX5_WOL_ARP = 1 << 3,
1034 MLX5_WOL_BROADCAST = 1 << 4,
1035 MLX5_WOL_MULTICAST = 1 << 5,
1036 MLX5_WOL_UNICAST = 1 << 6,
1037 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1038};
1039
1040enum mlx5_mpls_supported_fields {
1041 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1042 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1043 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1044 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1045};
1046
1047enum mlx5_flex_parser_protos {
1048 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1049 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1050};
1051
1052/* MLX5 DEV CAPs */
1053
1054/* TODO: EAT.ME */
1055enum mlx5_cap_mode {
1056 HCA_CAP_OPMOD_GET_MAX = 0,
1057 HCA_CAP_OPMOD_GET_CUR = 1,
1058};
1059
1060enum mlx5_cap_type {
1061 MLX5_CAP_GENERAL = 0,
1062 MLX5_CAP_ETHERNET_OFFLOADS,
1063 MLX5_CAP_ODP,
1064 MLX5_CAP_ATOMIC,
1065 MLX5_CAP_ROCE,
1066 MLX5_CAP_IPOIB_OFFLOADS,
1067 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1068 MLX5_CAP_FLOW_TABLE,
1069 MLX5_CAP_ESWITCH_FLOW_TABLE,
1070 MLX5_CAP_ESWITCH,
1071 MLX5_CAP_RESERVED,
1072 MLX5_CAP_VECTOR_CALC,
1073 MLX5_CAP_QOS,
1074 MLX5_CAP_DEBUG,
1075 MLX5_CAP_RESERVED_14,
1076 MLX5_CAP_DEV_MEM,
1077 /* NUM OF CAP Types */
1078 MLX5_CAP_NUM
1079};
1080
1081enum mlx5_pcam_reg_groups {
1082 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1083};
1084
1085enum mlx5_pcam_feature_groups {
1086 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1087};
1088
1089enum mlx5_mcam_reg_groups {
1090 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1091};
1092
1093enum mlx5_mcam_feature_groups {
1094 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1095};
1096
1097enum mlx5_qcam_reg_groups {
1098 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1099};
1100
1101enum mlx5_qcam_feature_groups {
1102 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1103};
1104
1105/* GET Dev Caps macros */
1106#define MLX5_CAP_GEN(mdev, cap) \
1107 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1108
1109#define MLX5_CAP_GEN_64(mdev, cap) \
1110 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1111
1112#define MLX5_CAP_GEN_MAX(mdev, cap) \
1113 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1114
1115#define MLX5_CAP_ETH(mdev, cap) \
1116 MLX5_GET(per_protocol_networking_offload_caps,\
1117 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1118
1119#define MLX5_CAP_ETH_MAX(mdev, cap) \
1120 MLX5_GET(per_protocol_networking_offload_caps,\
1121 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1122
1123#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1124 MLX5_GET(per_protocol_networking_offload_caps,\
1125 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1126
1127#define MLX5_CAP_ROCE(mdev, cap) \
1128 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1129
1130#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1131 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1132
1133#define MLX5_CAP_ATOMIC(mdev, cap) \
1134 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1135
1136#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1137 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1138
1139#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1140 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1141
1142#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1143 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1144
1145#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1146 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1147
1148#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1149 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1150
1151#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1152 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1153
1154#define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \
1155 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1156
1157#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1158 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1159
1160#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1161 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1162
1163#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1164 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1165
1166#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1167 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1168
1169#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1170 MLX5_GET(flow_table_eswitch_cap, \
1171 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1172
1173#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1174 MLX5_GET(flow_table_eswitch_cap, \
1175 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1176
1177#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1178 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1179
1180#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1181 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1182
1183#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1184 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1185
1186#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1187 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1188
1189#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1190 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1191
1192#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1193 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1194
1195#define MLX5_CAP_ESW(mdev, cap) \
1196 MLX5_GET(e_switch_cap, \
1197 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1198
1199#define MLX5_CAP_ESW_MAX(mdev, cap) \
1200 MLX5_GET(e_switch_cap, \
1201 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1202
1203#define MLX5_CAP_ODP(mdev, cap)\
1204 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1205
1206#define MLX5_CAP_ODP_MAX(mdev, cap)\
1207 MLX5_GET(odp_cap, mdev->caps.hca_max[MLX5_CAP_ODP], cap)
1208
1209#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1210 MLX5_GET(vector_calc_cap, \
1211 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1212
1213#define MLX5_CAP_QOS(mdev, cap)\
1214 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1215
1216#define MLX5_CAP_DEBUG(mdev, cap)\
1217 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1218
1219#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1220 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1221
1222#define MLX5_CAP_PCAM_REG(mdev, reg) \
1223 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1224
1225#define MLX5_CAP_MCAM_REG(mdev, reg) \
1226 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1227
1228#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1229 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1230
1231#define MLX5_CAP_QCAM_REG(mdev, fld) \
1232 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1233
1234#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1235 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1236
1237#define MLX5_CAP_FPGA(mdev, cap) \
1238 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1239
1240#define MLX5_CAP64_FPGA(mdev, cap) \
1241 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1242
1243#define MLX5_CAP_DEV_MEM(mdev, cap)\
1244 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1245
1246#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1247 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1248
1249enum {
1250 MLX5_CMD_STAT_OK = 0x0,
1251 MLX5_CMD_STAT_INT_ERR = 0x1,
1252 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1253 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1254 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1255 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1256 MLX5_CMD_STAT_RES_BUSY = 0x6,
1257 MLX5_CMD_STAT_LIM_ERR = 0x8,
1258 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1259 MLX5_CMD_STAT_IX_ERR = 0xa,
1260 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1261 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1262 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1263 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1264 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1265 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1266};
1267
1268enum {
1269 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1270 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1271 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1272 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1273 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1274 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1275 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1276 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1277 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1278 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1279};
1280
1281enum {
1282 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1283};
1284
1285static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1286{
1287 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1288 return 0;
1289 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1290}
1291
1292#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1293#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1294#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1295#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1296 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1297 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1298
1299#endif /* MLX5_DEVICE_H */