tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/module.h>
7#include <linux/of.h>
8#include <linux/platform_device.h>
9#include <linux/pinctrl/pinctrl.h>
10
11#include "pinctrl-msm.h"
12
13#define FUNCTION(fname) \
14 [msm_mux_##fname] = { \
15 .name = #fname, \
16 .groups = fname##_groups, \
17 .ngroups = ARRAY_SIZE(fname##_groups), \
18 }
19
20#define NORTH 0x00500000
21#define SOUTH 0x00900000
22#define EAST 0x00100000
23#define REG_SIZE 0x1000
24#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
25 { \
26 .name = "gpio" #id, \
27 .pins = gpio##id##_pins, \
28 .npins = ARRAY_SIZE(gpio##id##_pins), \
29 .funcs = (int[]){ \
30 msm_mux_gpio, /* gpio mode */ \
31 msm_mux_##f1, \
32 msm_mux_##f2, \
33 msm_mux_##f3, \
34 msm_mux_##f4, \
35 msm_mux_##f5, \
36 msm_mux_##f6, \
37 msm_mux_##f7, \
38 msm_mux_##f8, \
39 msm_mux_##f9, \
40 msm_mux_##f10 \
41 }, \
42 .nfuncs = 11, \
43 .ctl_reg = base + REG_SIZE * id, \
44 .io_reg = base + 0x4 + REG_SIZE * id, \
45 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
46 .intr_status_reg = base + 0xc + REG_SIZE * id, \
47 .intr_target_reg = base + 0x8 + REG_SIZE * id, \
48 .mux_bit = 2, \
49 .pull_bit = 0, \
50 .drv_bit = 6, \
51 .oe_bit = 9, \
52 .in_bit = 0, \
53 .out_bit = 1, \
54 .intr_enable_bit = 0, \
55 .intr_status_bit = 0, \
56 .intr_target_bit = 5, \
57 .intr_target_kpss_val = 3, \
58 .intr_raw_status_bit = 4, \
59 .intr_polarity_bit = 1, \
60 .intr_detection_bit = 2, \
61 .intr_detection_width = 2, \
62 }
63
64#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
65 { \
66 .name = #pg_name, \
67 .pins = pg_name##_pins, \
68 .npins = ARRAY_SIZE(pg_name##_pins), \
69 .ctl_reg = ctl, \
70 .io_reg = 0, \
71 .intr_cfg_reg = 0, \
72 .intr_status_reg = 0, \
73 .intr_target_reg = 0, \
74 .mux_bit = -1, \
75 .pull_bit = pull, \
76 .drv_bit = drv, \
77 .oe_bit = -1, \
78 .in_bit = -1, \
79 .out_bit = -1, \
80 .intr_enable_bit = -1, \
81 .intr_status_bit = -1, \
82 .intr_target_bit = -1, \
83 .intr_raw_status_bit = -1, \
84 .intr_polarity_bit = -1, \
85 .intr_detection_bit = -1, \
86 .intr_detection_width = -1, \
87 }
88
89#define UFS_RESET(pg_name, offset) \
90 { \
91 .name = #pg_name, \
92 .pins = pg_name##_pins, \
93 .npins = ARRAY_SIZE(pg_name##_pins), \
94 .ctl_reg = offset, \
95 .io_reg = offset + 0x4, \
96 .intr_cfg_reg = 0, \
97 .intr_status_reg = 0, \
98 .intr_target_reg = 0, \
99 .mux_bit = -1, \
100 .pull_bit = 3, \
101 .drv_bit = 0, \
102 .oe_bit = -1, \
103 .in_bit = -1, \
104 .out_bit = 0, \
105 .intr_enable_bit = -1, \
106 .intr_status_bit = -1, \
107 .intr_target_bit = -1, \
108 .intr_raw_status_bit = -1, \
109 .intr_polarity_bit = -1, \
110 .intr_detection_bit = -1, \
111 .intr_detection_width = -1, \
112 }
113static const struct pinctrl_pin_desc sdm845_pins[] = {
114 PINCTRL_PIN(0, "GPIO_0"),
115 PINCTRL_PIN(1, "GPIO_1"),
116 PINCTRL_PIN(2, "GPIO_2"),
117 PINCTRL_PIN(3, "GPIO_3"),
118 PINCTRL_PIN(4, "GPIO_4"),
119 PINCTRL_PIN(5, "GPIO_5"),
120 PINCTRL_PIN(6, "GPIO_6"),
121 PINCTRL_PIN(7, "GPIO_7"),
122 PINCTRL_PIN(8, "GPIO_8"),
123 PINCTRL_PIN(9, "GPIO_9"),
124 PINCTRL_PIN(10, "GPIO_10"),
125 PINCTRL_PIN(11, "GPIO_11"),
126 PINCTRL_PIN(12, "GPIO_12"),
127 PINCTRL_PIN(13, "GPIO_13"),
128 PINCTRL_PIN(14, "GPIO_14"),
129 PINCTRL_PIN(15, "GPIO_15"),
130 PINCTRL_PIN(16, "GPIO_16"),
131 PINCTRL_PIN(17, "GPIO_17"),
132 PINCTRL_PIN(18, "GPIO_18"),
133 PINCTRL_PIN(19, "GPIO_19"),
134 PINCTRL_PIN(20, "GPIO_20"),
135 PINCTRL_PIN(21, "GPIO_21"),
136 PINCTRL_PIN(22, "GPIO_22"),
137 PINCTRL_PIN(23, "GPIO_23"),
138 PINCTRL_PIN(24, "GPIO_24"),
139 PINCTRL_PIN(25, "GPIO_25"),
140 PINCTRL_PIN(26, "GPIO_26"),
141 PINCTRL_PIN(27, "GPIO_27"),
142 PINCTRL_PIN(28, "GPIO_28"),
143 PINCTRL_PIN(29, "GPIO_29"),
144 PINCTRL_PIN(30, "GPIO_30"),
145 PINCTRL_PIN(31, "GPIO_31"),
146 PINCTRL_PIN(32, "GPIO_32"),
147 PINCTRL_PIN(33, "GPIO_33"),
148 PINCTRL_PIN(34, "GPIO_34"),
149 PINCTRL_PIN(35, "GPIO_35"),
150 PINCTRL_PIN(36, "GPIO_36"),
151 PINCTRL_PIN(37, "GPIO_37"),
152 PINCTRL_PIN(38, "GPIO_38"),
153 PINCTRL_PIN(39, "GPIO_39"),
154 PINCTRL_PIN(40, "GPIO_40"),
155 PINCTRL_PIN(41, "GPIO_41"),
156 PINCTRL_PIN(42, "GPIO_42"),
157 PINCTRL_PIN(43, "GPIO_43"),
158 PINCTRL_PIN(44, "GPIO_44"),
159 PINCTRL_PIN(45, "GPIO_45"),
160 PINCTRL_PIN(46, "GPIO_46"),
161 PINCTRL_PIN(47, "GPIO_47"),
162 PINCTRL_PIN(48, "GPIO_48"),
163 PINCTRL_PIN(49, "GPIO_49"),
164 PINCTRL_PIN(50, "GPIO_50"),
165 PINCTRL_PIN(51, "GPIO_51"),
166 PINCTRL_PIN(52, "GPIO_52"),
167 PINCTRL_PIN(53, "GPIO_53"),
168 PINCTRL_PIN(54, "GPIO_54"),
169 PINCTRL_PIN(55, "GPIO_55"),
170 PINCTRL_PIN(56, "GPIO_56"),
171 PINCTRL_PIN(57, "GPIO_57"),
172 PINCTRL_PIN(58, "GPIO_58"),
173 PINCTRL_PIN(59, "GPIO_59"),
174 PINCTRL_PIN(60, "GPIO_60"),
175 PINCTRL_PIN(61, "GPIO_61"),
176 PINCTRL_PIN(62, "GPIO_62"),
177 PINCTRL_PIN(63, "GPIO_63"),
178 PINCTRL_PIN(64, "GPIO_64"),
179 PINCTRL_PIN(65, "GPIO_65"),
180 PINCTRL_PIN(66, "GPIO_66"),
181 PINCTRL_PIN(67, "GPIO_67"),
182 PINCTRL_PIN(68, "GPIO_68"),
183 PINCTRL_PIN(69, "GPIO_69"),
184 PINCTRL_PIN(70, "GPIO_70"),
185 PINCTRL_PIN(71, "GPIO_71"),
186 PINCTRL_PIN(72, "GPIO_72"),
187 PINCTRL_PIN(73, "GPIO_73"),
188 PINCTRL_PIN(74, "GPIO_74"),
189 PINCTRL_PIN(75, "GPIO_75"),
190 PINCTRL_PIN(76, "GPIO_76"),
191 PINCTRL_PIN(77, "GPIO_77"),
192 PINCTRL_PIN(78, "GPIO_78"),
193 PINCTRL_PIN(79, "GPIO_79"),
194 PINCTRL_PIN(80, "GPIO_80"),
195 PINCTRL_PIN(81, "GPIO_81"),
196 PINCTRL_PIN(82, "GPIO_82"),
197 PINCTRL_PIN(83, "GPIO_83"),
198 PINCTRL_PIN(84, "GPIO_84"),
199 PINCTRL_PIN(85, "GPIO_85"),
200 PINCTRL_PIN(86, "GPIO_86"),
201 PINCTRL_PIN(87, "GPIO_87"),
202 PINCTRL_PIN(88, "GPIO_88"),
203 PINCTRL_PIN(89, "GPIO_89"),
204 PINCTRL_PIN(90, "GPIO_90"),
205 PINCTRL_PIN(91, "GPIO_91"),
206 PINCTRL_PIN(92, "GPIO_92"),
207 PINCTRL_PIN(93, "GPIO_93"),
208 PINCTRL_PIN(94, "GPIO_94"),
209 PINCTRL_PIN(95, "GPIO_95"),
210 PINCTRL_PIN(96, "GPIO_96"),
211 PINCTRL_PIN(97, "GPIO_97"),
212 PINCTRL_PIN(98, "GPIO_98"),
213 PINCTRL_PIN(99, "GPIO_99"),
214 PINCTRL_PIN(100, "GPIO_100"),
215 PINCTRL_PIN(101, "GPIO_101"),
216 PINCTRL_PIN(102, "GPIO_102"),
217 PINCTRL_PIN(103, "GPIO_103"),
218 PINCTRL_PIN(104, "GPIO_104"),
219 PINCTRL_PIN(105, "GPIO_105"),
220 PINCTRL_PIN(106, "GPIO_106"),
221 PINCTRL_PIN(107, "GPIO_107"),
222 PINCTRL_PIN(108, "GPIO_108"),
223 PINCTRL_PIN(109, "GPIO_109"),
224 PINCTRL_PIN(110, "GPIO_110"),
225 PINCTRL_PIN(111, "GPIO_111"),
226 PINCTRL_PIN(112, "GPIO_112"),
227 PINCTRL_PIN(113, "GPIO_113"),
228 PINCTRL_PIN(114, "GPIO_114"),
229 PINCTRL_PIN(115, "GPIO_115"),
230 PINCTRL_PIN(116, "GPIO_116"),
231 PINCTRL_PIN(117, "GPIO_117"),
232 PINCTRL_PIN(118, "GPIO_118"),
233 PINCTRL_PIN(119, "GPIO_119"),
234 PINCTRL_PIN(120, "GPIO_120"),
235 PINCTRL_PIN(121, "GPIO_121"),
236 PINCTRL_PIN(122, "GPIO_122"),
237 PINCTRL_PIN(123, "GPIO_123"),
238 PINCTRL_PIN(124, "GPIO_124"),
239 PINCTRL_PIN(125, "GPIO_125"),
240 PINCTRL_PIN(126, "GPIO_126"),
241 PINCTRL_PIN(127, "GPIO_127"),
242 PINCTRL_PIN(128, "GPIO_128"),
243 PINCTRL_PIN(129, "GPIO_129"),
244 PINCTRL_PIN(130, "GPIO_130"),
245 PINCTRL_PIN(131, "GPIO_131"),
246 PINCTRL_PIN(132, "GPIO_132"),
247 PINCTRL_PIN(133, "GPIO_133"),
248 PINCTRL_PIN(134, "GPIO_134"),
249 PINCTRL_PIN(135, "GPIO_135"),
250 PINCTRL_PIN(136, "GPIO_136"),
251 PINCTRL_PIN(137, "GPIO_137"),
252 PINCTRL_PIN(138, "GPIO_138"),
253 PINCTRL_PIN(139, "GPIO_139"),
254 PINCTRL_PIN(140, "GPIO_140"),
255 PINCTRL_PIN(141, "GPIO_141"),
256 PINCTRL_PIN(142, "GPIO_142"),
257 PINCTRL_PIN(143, "GPIO_143"),
258 PINCTRL_PIN(144, "GPIO_144"),
259 PINCTRL_PIN(145, "GPIO_145"),
260 PINCTRL_PIN(146, "GPIO_146"),
261 PINCTRL_PIN(147, "GPIO_147"),
262 PINCTRL_PIN(148, "GPIO_148"),
263 PINCTRL_PIN(149, "GPIO_149"),
264 PINCTRL_PIN(150, "SDC2_CLK"),
265 PINCTRL_PIN(151, "SDC2_CMD"),
266 PINCTRL_PIN(152, "SDC2_DATA"),
267 PINCTRL_PIN(153, "UFS_RESET"),
268};
269
270#define DECLARE_MSM_GPIO_PINS(pin) \
271 static const unsigned int gpio##pin##_pins[] = { pin }
272DECLARE_MSM_GPIO_PINS(0);
273DECLARE_MSM_GPIO_PINS(1);
274DECLARE_MSM_GPIO_PINS(2);
275DECLARE_MSM_GPIO_PINS(3);
276DECLARE_MSM_GPIO_PINS(4);
277DECLARE_MSM_GPIO_PINS(5);
278DECLARE_MSM_GPIO_PINS(6);
279DECLARE_MSM_GPIO_PINS(7);
280DECLARE_MSM_GPIO_PINS(8);
281DECLARE_MSM_GPIO_PINS(9);
282DECLARE_MSM_GPIO_PINS(10);
283DECLARE_MSM_GPIO_PINS(11);
284DECLARE_MSM_GPIO_PINS(12);
285DECLARE_MSM_GPIO_PINS(13);
286DECLARE_MSM_GPIO_PINS(14);
287DECLARE_MSM_GPIO_PINS(15);
288DECLARE_MSM_GPIO_PINS(16);
289DECLARE_MSM_GPIO_PINS(17);
290DECLARE_MSM_GPIO_PINS(18);
291DECLARE_MSM_GPIO_PINS(19);
292DECLARE_MSM_GPIO_PINS(20);
293DECLARE_MSM_GPIO_PINS(21);
294DECLARE_MSM_GPIO_PINS(22);
295DECLARE_MSM_GPIO_PINS(23);
296DECLARE_MSM_GPIO_PINS(24);
297DECLARE_MSM_GPIO_PINS(25);
298DECLARE_MSM_GPIO_PINS(26);
299DECLARE_MSM_GPIO_PINS(27);
300DECLARE_MSM_GPIO_PINS(28);
301DECLARE_MSM_GPIO_PINS(29);
302DECLARE_MSM_GPIO_PINS(30);
303DECLARE_MSM_GPIO_PINS(31);
304DECLARE_MSM_GPIO_PINS(32);
305DECLARE_MSM_GPIO_PINS(33);
306DECLARE_MSM_GPIO_PINS(34);
307DECLARE_MSM_GPIO_PINS(35);
308DECLARE_MSM_GPIO_PINS(36);
309DECLARE_MSM_GPIO_PINS(37);
310DECLARE_MSM_GPIO_PINS(38);
311DECLARE_MSM_GPIO_PINS(39);
312DECLARE_MSM_GPIO_PINS(40);
313DECLARE_MSM_GPIO_PINS(41);
314DECLARE_MSM_GPIO_PINS(42);
315DECLARE_MSM_GPIO_PINS(43);
316DECLARE_MSM_GPIO_PINS(44);
317DECLARE_MSM_GPIO_PINS(45);
318DECLARE_MSM_GPIO_PINS(46);
319DECLARE_MSM_GPIO_PINS(47);
320DECLARE_MSM_GPIO_PINS(48);
321DECLARE_MSM_GPIO_PINS(49);
322DECLARE_MSM_GPIO_PINS(50);
323DECLARE_MSM_GPIO_PINS(51);
324DECLARE_MSM_GPIO_PINS(52);
325DECLARE_MSM_GPIO_PINS(53);
326DECLARE_MSM_GPIO_PINS(54);
327DECLARE_MSM_GPIO_PINS(55);
328DECLARE_MSM_GPIO_PINS(56);
329DECLARE_MSM_GPIO_PINS(57);
330DECLARE_MSM_GPIO_PINS(58);
331DECLARE_MSM_GPIO_PINS(59);
332DECLARE_MSM_GPIO_PINS(60);
333DECLARE_MSM_GPIO_PINS(61);
334DECLARE_MSM_GPIO_PINS(62);
335DECLARE_MSM_GPIO_PINS(63);
336DECLARE_MSM_GPIO_PINS(64);
337DECLARE_MSM_GPIO_PINS(65);
338DECLARE_MSM_GPIO_PINS(66);
339DECLARE_MSM_GPIO_PINS(67);
340DECLARE_MSM_GPIO_PINS(68);
341DECLARE_MSM_GPIO_PINS(69);
342DECLARE_MSM_GPIO_PINS(70);
343DECLARE_MSM_GPIO_PINS(71);
344DECLARE_MSM_GPIO_PINS(72);
345DECLARE_MSM_GPIO_PINS(73);
346DECLARE_MSM_GPIO_PINS(74);
347DECLARE_MSM_GPIO_PINS(75);
348DECLARE_MSM_GPIO_PINS(76);
349DECLARE_MSM_GPIO_PINS(77);
350DECLARE_MSM_GPIO_PINS(78);
351DECLARE_MSM_GPIO_PINS(79);
352DECLARE_MSM_GPIO_PINS(80);
353DECLARE_MSM_GPIO_PINS(81);
354DECLARE_MSM_GPIO_PINS(82);
355DECLARE_MSM_GPIO_PINS(83);
356DECLARE_MSM_GPIO_PINS(84);
357DECLARE_MSM_GPIO_PINS(85);
358DECLARE_MSM_GPIO_PINS(86);
359DECLARE_MSM_GPIO_PINS(87);
360DECLARE_MSM_GPIO_PINS(88);
361DECLARE_MSM_GPIO_PINS(89);
362DECLARE_MSM_GPIO_PINS(90);
363DECLARE_MSM_GPIO_PINS(91);
364DECLARE_MSM_GPIO_PINS(92);
365DECLARE_MSM_GPIO_PINS(93);
366DECLARE_MSM_GPIO_PINS(94);
367DECLARE_MSM_GPIO_PINS(95);
368DECLARE_MSM_GPIO_PINS(96);
369DECLARE_MSM_GPIO_PINS(97);
370DECLARE_MSM_GPIO_PINS(98);
371DECLARE_MSM_GPIO_PINS(99);
372DECLARE_MSM_GPIO_PINS(100);
373DECLARE_MSM_GPIO_PINS(101);
374DECLARE_MSM_GPIO_PINS(102);
375DECLARE_MSM_GPIO_PINS(103);
376DECLARE_MSM_GPIO_PINS(104);
377DECLARE_MSM_GPIO_PINS(105);
378DECLARE_MSM_GPIO_PINS(106);
379DECLARE_MSM_GPIO_PINS(107);
380DECLARE_MSM_GPIO_PINS(108);
381DECLARE_MSM_GPIO_PINS(109);
382DECLARE_MSM_GPIO_PINS(110);
383DECLARE_MSM_GPIO_PINS(111);
384DECLARE_MSM_GPIO_PINS(112);
385DECLARE_MSM_GPIO_PINS(113);
386DECLARE_MSM_GPIO_PINS(114);
387DECLARE_MSM_GPIO_PINS(115);
388DECLARE_MSM_GPIO_PINS(116);
389DECLARE_MSM_GPIO_PINS(117);
390DECLARE_MSM_GPIO_PINS(118);
391DECLARE_MSM_GPIO_PINS(119);
392DECLARE_MSM_GPIO_PINS(120);
393DECLARE_MSM_GPIO_PINS(121);
394DECLARE_MSM_GPIO_PINS(122);
395DECLARE_MSM_GPIO_PINS(123);
396DECLARE_MSM_GPIO_PINS(124);
397DECLARE_MSM_GPIO_PINS(125);
398DECLARE_MSM_GPIO_PINS(126);
399DECLARE_MSM_GPIO_PINS(127);
400DECLARE_MSM_GPIO_PINS(128);
401DECLARE_MSM_GPIO_PINS(129);
402DECLARE_MSM_GPIO_PINS(130);
403DECLARE_MSM_GPIO_PINS(131);
404DECLARE_MSM_GPIO_PINS(132);
405DECLARE_MSM_GPIO_PINS(133);
406DECLARE_MSM_GPIO_PINS(134);
407DECLARE_MSM_GPIO_PINS(135);
408DECLARE_MSM_GPIO_PINS(136);
409DECLARE_MSM_GPIO_PINS(137);
410DECLARE_MSM_GPIO_PINS(138);
411DECLARE_MSM_GPIO_PINS(139);
412DECLARE_MSM_GPIO_PINS(140);
413DECLARE_MSM_GPIO_PINS(141);
414DECLARE_MSM_GPIO_PINS(142);
415DECLARE_MSM_GPIO_PINS(143);
416DECLARE_MSM_GPIO_PINS(144);
417DECLARE_MSM_GPIO_PINS(145);
418DECLARE_MSM_GPIO_PINS(146);
419DECLARE_MSM_GPIO_PINS(147);
420DECLARE_MSM_GPIO_PINS(148);
421DECLARE_MSM_GPIO_PINS(149);
422
423static const unsigned int sdc2_clk_pins[] = { 150 };
424static const unsigned int sdc2_cmd_pins[] = { 151 };
425static const unsigned int sdc2_data_pins[] = { 152 };
426static const unsigned int ufs_reset_pins[] = { 153 };
427
428enum sdm845_functions {
429 msm_mux_gpio,
430 msm_mux_adsp_ext,
431 msm_mux_agera_pll,
432 msm_mux_atest_char,
433 msm_mux_atest_tsens,
434 msm_mux_atest_tsens2,
435 msm_mux_atest_usb1,
436 msm_mux_atest_usb10,
437 msm_mux_atest_usb11,
438 msm_mux_atest_usb12,
439 msm_mux_atest_usb13,
440 msm_mux_atest_usb2,
441 msm_mux_atest_usb20,
442 msm_mux_atest_usb21,
443 msm_mux_atest_usb22,
444 msm_mux_atest_usb23,
445 msm_mux_audio_ref,
446 msm_mux_btfm_slimbus,
447 msm_mux_cam_mclk,
448 msm_mux_cci_async,
449 msm_mux_cci_i2c,
450 msm_mux_cci_timer0,
451 msm_mux_cci_timer1,
452 msm_mux_cci_timer2,
453 msm_mux_cci_timer3,
454 msm_mux_cci_timer4,
455 msm_mux_cri_trng,
456 msm_mux_cri_trng0,
457 msm_mux_cri_trng1,
458 msm_mux_dbg_out,
459 msm_mux_ddr_bist,
460 msm_mux_ddr_pxi0,
461 msm_mux_ddr_pxi1,
462 msm_mux_ddr_pxi2,
463 msm_mux_ddr_pxi3,
464 msm_mux_edp_hot,
465 msm_mux_edp_lcd,
466 msm_mux_gcc_gp1,
467 msm_mux_gcc_gp2,
468 msm_mux_gcc_gp3,
469 msm_mux_jitter_bist,
470 msm_mux_ldo_en,
471 msm_mux_ldo_update,
472 msm_mux_lpass_slimbus,
473 msm_mux_m_voc,
474 msm_mux_mdp_vsync,
475 msm_mux_mdp_vsync0,
476 msm_mux_mdp_vsync1,
477 msm_mux_mdp_vsync2,
478 msm_mux_mdp_vsync3,
479 msm_mux_mss_lte,
480 msm_mux_nav_pps,
481 msm_mux_pa_indicator,
482 msm_mux_pci_e0,
483 msm_mux_pci_e1,
484 msm_mux_phase_flag,
485 msm_mux_pll_bist,
486 msm_mux_pll_bypassnl,
487 msm_mux_pll_reset,
488 msm_mux_pri_mi2s,
489 msm_mux_pri_mi2s_ws,
490 msm_mux_prng_rosc,
491 msm_mux_qdss_cti,
492 msm_mux_qdss,
493 msm_mux_qlink_enable,
494 msm_mux_qlink_request,
495 msm_mux_qspi_clk,
496 msm_mux_qspi_cs,
497 msm_mux_qspi_data,
498 msm_mux_qua_mi2s,
499 msm_mux_qup0,
500 msm_mux_qup1,
501 msm_mux_qup10,
502 msm_mux_qup11,
503 msm_mux_qup12,
504 msm_mux_qup13,
505 msm_mux_qup14,
506 msm_mux_qup15,
507 msm_mux_qup2,
508 msm_mux_qup3,
509 msm_mux_qup4,
510 msm_mux_qup5,
511 msm_mux_qup6,
512 msm_mux_qup7,
513 msm_mux_qup8,
514 msm_mux_qup9,
515 msm_mux_qup_l4,
516 msm_mux_qup_l5,
517 msm_mux_qup_l6,
518 msm_mux_sd_write,
519 msm_mux_sdc4_clk,
520 msm_mux_sdc4_cmd,
521 msm_mux_sdc4_data,
522 msm_mux_sec_mi2s,
523 msm_mux_sp_cmu,
524 msm_mux_spkr_i2s,
525 msm_mux_ter_mi2s,
526 msm_mux_tgu_ch0,
527 msm_mux_tgu_ch1,
528 msm_mux_tgu_ch2,
529 msm_mux_tgu_ch3,
530 msm_mux_tsense_pwm1,
531 msm_mux_tsense_pwm2,
532 msm_mux_tsif1_clk,
533 msm_mux_tsif1_data,
534 msm_mux_tsif1_en,
535 msm_mux_tsif1_error,
536 msm_mux_tsif1_sync,
537 msm_mux_tsif2_clk,
538 msm_mux_tsif2_data,
539 msm_mux_tsif2_en,
540 msm_mux_tsif2_error,
541 msm_mux_tsif2_sync,
542 msm_mux_uim1_clk,
543 msm_mux_uim1_data,
544 msm_mux_uim1_present,
545 msm_mux_uim1_reset,
546 msm_mux_uim2_clk,
547 msm_mux_uim2_data,
548 msm_mux_uim2_present,
549 msm_mux_uim2_reset,
550 msm_mux_uim_batt,
551 msm_mux_usb_phy,
552 msm_mux_vfr_1,
553 msm_mux_vsense_trigger,
554 msm_mux_wlan1_adc0,
555 msm_mux_wlan1_adc1,
556 msm_mux_wlan2_adc0,
557 msm_mux_wlan2_adc1,
558 msm_mux__,
559};
560
561static const char * const ddr_pxi3_groups[] = {
562 "gpio12", "gpio13",
563};
564static const char * const cam_mclk_groups[] = {
565 "gpio13", "gpio14", "gpio15", "gpio16",
566};
567static const char * const pll_bypassnl_groups[] = {
568 "gpio13",
569};
570static const char * const qdss_groups[] = {
571 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
572 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
573 "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
574 "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
575 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
576 "gpio123", "gpio124",
577};
578static const char * const pll_reset_groups[] = {
579 "gpio14",
580};
581static const char * const cci_i2c_groups[] = {
582 "gpio17", "gpio18", "gpio19", "gpio20",
583};
584static const char * const qup1_groups[] = {
585 "gpio17", "gpio18", "gpio19", "gpio20",
586};
587static const char * const cci_timer0_groups[] = {
588 "gpio21",
589};
590static const char * const gcc_gp2_groups[] = {
591 "gpio21", "gpio58",
592};
593static const char * const cci_timer1_groups[] = {
594 "gpio22",
595};
596static const char * const gcc_gp3_groups[] = {
597 "gpio22", "gpio59",
598};
599static const char * const cci_timer2_groups[] = {
600 "gpio23",
601};
602static const char * const cci_timer3_groups[] = {
603 "gpio24",
604};
605static const char * const cci_async_groups[] = {
606 "gpio24", "gpio25", "gpio26",
607};
608static const char * const cci_timer4_groups[] = {
609 "gpio25",
610};
611static const char * const qup2_groups[] = {
612 "gpio27", "gpio28", "gpio29", "gpio30",
613};
614static const char * const phase_flag_groups[] = {
615 "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
616 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
617 "gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90",
618 "gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138",
619 "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
620};
621static const char * const qup11_groups[] = {
622 "gpio31", "gpio32", "gpio33", "gpio34",
623};
624static const char * const qup14_groups[] = {
625 "gpio31", "gpio32", "gpio33", "gpio34",
626};
627static const char * const pci_e0_groups[] = {
628 "gpio35", "gpio36",
629};
630static const char * const jitter_bist_groups[] = {
631 "gpio35",
632};
633static const char * const pll_bist_groups[] = {
634 "gpio36",
635};
636static const char * const atest_tsens_groups[] = {
637 "gpio36",
638};
639static const char * const agera_pll_groups[] = {
640 "gpio37",
641};
642static const char * const usb_phy_groups[] = {
643 "gpio38",
644};
645static const char * const lpass_slimbus_groups[] = {
646 "gpio39", "gpio70", "gpio71", "gpio72",
647};
648static const char * const sd_write_groups[] = {
649 "gpio40",
650};
651static const char * const tsif1_error_groups[] = {
652 "gpio40",
653};
654static const char * const qup3_groups[] = {
655 "gpio41", "gpio42", "gpio43", "gpio44",
656};
657static const char * const qup6_groups[] = {
658 "gpio45", "gpio46", "gpio47", "gpio48",
659};
660static const char * const qup12_groups[] = {
661 "gpio49", "gpio50", "gpio51", "gpio52",
662};
663static const char * const qup10_groups[] = {
664 "gpio53", "gpio54", "gpio55", "gpio56",
665};
666static const char * const qua_mi2s_groups[] = {
667 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
668};
669static const char * const gcc_gp1_groups[] = {
670 "gpio57", "gpio78",
671};
672static const char * const cri_trng0_groups[] = {
673 "gpio60",
674};
675static const char * const cri_trng1_groups[] = {
676 "gpio61",
677};
678static const char * const cri_trng_groups[] = {
679 "gpio62",
680};
681static const char * const pri_mi2s_groups[] = {
682 "gpio64", "gpio65", "gpio67", "gpio68",
683};
684static const char * const sp_cmu_groups[] = {
685 "gpio64",
686};
687static const char * const qup8_groups[] = {
688 "gpio65", "gpio66", "gpio67", "gpio68",
689};
690static const char * const pri_mi2s_ws_groups[] = {
691 "gpio66",
692};
693static const char * const spkr_i2s_groups[] = {
694 "gpio69", "gpio70", "gpio71", "gpio72",
695};
696static const char * const audio_ref_groups[] = {
697 "gpio69",
698};
699static const char * const tsense_pwm1_groups[] = {
700 "gpio71",
701};
702static const char * const tsense_pwm2_groups[] = {
703 "gpio71",
704};
705static const char * const btfm_slimbus_groups[] = {
706 "gpio73", "gpio74",
707};
708static const char * const atest_usb2_groups[] = {
709 "gpio73",
710};
711static const char * const ter_mi2s_groups[] = {
712 "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
713};
714static const char * const atest_usb23_groups[] = {
715 "gpio74",
716};
717static const char * const atest_usb22_groups[] = {
718 "gpio75",
719};
720static const char * const atest_usb21_groups[] = {
721 "gpio76",
722};
723static const char * const atest_usb20_groups[] = {
724 "gpio77",
725};
726static const char * const sec_mi2s_groups[] = {
727 "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
728};
729static const char * const qup15_groups[] = {
730 "gpio81", "gpio82", "gpio83", "gpio84",
731};
732static const char * const qup5_groups[] = {
733 "gpio85", "gpio86", "gpio87", "gpio88",
734};
735static const char * const tsif1_clk_groups[] = {
736 "gpio89",
737};
738static const char * const qup4_groups[] = {
739 "gpio89", "gpio90", "gpio91", "gpio92",
740};
741static const char * const qspi_cs_groups[] = {
742 "gpio89", "gpio90",
743};
744static const char * const tgu_ch3_groups[] = {
745 "gpio89",
746};
747static const char * const tsif1_en_groups[] = {
748 "gpio90",
749};
750static const char * const mdp_vsync0_groups[] = {
751 "gpio90",
752};
753static const char * const mdp_vsync1_groups[] = {
754 "gpio90",
755};
756static const char * const mdp_vsync2_groups[] = {
757 "gpio90",
758};
759static const char * const mdp_vsync3_groups[] = {
760 "gpio90",
761};
762static const char * const tgu_ch0_groups[] = {
763 "gpio90",
764};
765static const char * const tsif1_data_groups[] = {
766 "gpio91",
767};
768static const char * const sdc4_cmd_groups[] = {
769 "gpio91",
770};
771static const char * const qspi_data_groups[] = {
772 "gpio91", "gpio92", "gpio93", "gpio94",
773};
774static const char * const tgu_ch1_groups[] = {
775 "gpio91",
776};
777static const char * const tsif2_error_groups[] = {
778 "gpio92",
779};
780static const char * const sdc4_data_groups[] = {
781 "gpio92",
782 "gpio94",
783 "gpio95",
784 "gpio96",
785};
786static const char * const vfr_1_groups[] = {
787 "gpio92",
788};
789static const char * const tgu_ch2_groups[] = {
790 "gpio92",
791};
792static const char * const tsif2_clk_groups[] = {
793 "gpio93",
794};
795static const char * const sdc4_clk_groups[] = {
796 "gpio93",
797};
798static const char * const qup7_groups[] = {
799 "gpio93", "gpio94", "gpio95", "gpio96",
800};
801static const char * const tsif2_en_groups[] = {
802 "gpio94",
803};
804static const char * const tsif2_data_groups[] = {
805 "gpio95",
806};
807static const char * const qspi_clk_groups[] = {
808 "gpio95",
809};
810static const char * const tsif2_sync_groups[] = {
811 "gpio96",
812};
813static const char * const ldo_en_groups[] = {
814 "gpio97",
815};
816static const char * const ldo_update_groups[] = {
817 "gpio98",
818};
819static const char * const pci_e1_groups[] = {
820 "gpio102", "gpio103",
821};
822static const char * const prng_rosc_groups[] = {
823 "gpio102",
824};
825static const char * const uim2_data_groups[] = {
826 "gpio105",
827};
828static const char * const qup13_groups[] = {
829 "gpio105", "gpio106", "gpio107", "gpio108",
830};
831static const char * const uim2_clk_groups[] = {
832 "gpio106",
833};
834static const char * const uim2_reset_groups[] = {
835 "gpio107",
836};
837static const char * const uim2_present_groups[] = {
838 "gpio108",
839};
840static const char * const uim1_data_groups[] = {
841 "gpio109",
842};
843static const char * const uim1_clk_groups[] = {
844 "gpio110",
845};
846static const char * const uim1_reset_groups[] = {
847 "gpio111",
848};
849static const char * const uim1_present_groups[] = {
850 "gpio112",
851};
852static const char * const uim_batt_groups[] = {
853 "gpio113",
854};
855static const char * const edp_hot_groups[] = {
856 "gpio113",
857};
858static const char * const nav_pps_groups[] = {
859 "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
860 "gpio129", "gpio129", "gpio143", "gpio143",
861};
862static const char * const atest_char_groups[] = {
863 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
864};
865static const char * const adsp_ext_groups[] = {
866 "gpio118",
867};
868static const char * const qlink_request_groups[] = {
869 "gpio130",
870};
871static const char * const qlink_enable_groups[] = {
872 "gpio131",
873};
874static const char * const pa_indicator_groups[] = {
875 "gpio135",
876};
877static const char * const mss_lte_groups[] = {
878 "gpio144", "gpio145",
879};
880static const char * const qup0_groups[] = {
881 "gpio0", "gpio1", "gpio2", "gpio3",
882};
883static const char * const gpio_groups[] = {
884 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
885 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
886 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
887 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
888 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
889 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
890 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
891 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
892 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
893 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
894 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
895 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
896 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
897 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
898 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
899 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
900 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
901 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
902 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
903 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
904 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
905 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
906 "gpio147", "gpio148", "gpio149",
907};
908static const char * const qup9_groups[] = {
909 "gpio4", "gpio5", "gpio6", "gpio7",
910};
911static const char * const qdss_cti_groups[] = {
912 "gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90",
913 "gpio91",
914};
915static const char * const ddr_pxi0_groups[] = {
916 "gpio6", "gpio7",
917};
918static const char * const ddr_bist_groups[] = {
919 "gpio7", "gpio8", "gpio9", "gpio10",
920};
921static const char * const atest_tsens2_groups[] = {
922 "gpio7",
923};
924static const char * const vsense_trigger_groups[] = {
925 "gpio7",
926};
927static const char * const atest_usb1_groups[] = {
928 "gpio7",
929};
930static const char * const qup_l4_groups[] = {
931 "gpio8", "gpio35", "gpio105", "gpio123",
932};
933static const char * const wlan1_adc1_groups[] = {
934 "gpio8",
935};
936static const char * const atest_usb13_groups[] = {
937 "gpio8",
938};
939static const char * const ddr_pxi1_groups[] = {
940 "gpio8", "gpio9",
941};
942static const char * const qup_l5_groups[] = {
943 "gpio9", "gpio36", "gpio106", "gpio124",
944};
945static const char * const wlan1_adc0_groups[] = {
946 "gpio9",
947};
948static const char * const atest_usb12_groups[] = {
949 "gpio9",
950};
951static const char * const mdp_vsync_groups[] = {
952 "gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
953};
954static const char * const qup_l6_groups[] = {
955 "gpio10", "gpio37", "gpio107", "gpio125",
956};
957static const char * const wlan2_adc1_groups[] = {
958 "gpio10",
959};
960static const char * const atest_usb11_groups[] = {
961 "gpio10",
962};
963static const char * const ddr_pxi2_groups[] = {
964 "gpio10", "gpio11",
965};
966static const char * const edp_lcd_groups[] = {
967 "gpio11",
968};
969static const char * const dbg_out_groups[] = {
970 "gpio11",
971};
972static const char * const wlan2_adc0_groups[] = {
973 "gpio11",
974};
975static const char * const atest_usb10_groups[] = {
976 "gpio11",
977};
978static const char * const m_voc_groups[] = {
979 "gpio12",
980};
981static const char * const tsif1_sync_groups[] = {
982 "gpio12",
983};
984
985static const struct msm_function sdm845_functions[] = {
986 FUNCTION(gpio),
987 FUNCTION(adsp_ext),
988 FUNCTION(agera_pll),
989 FUNCTION(atest_char),
990 FUNCTION(atest_tsens),
991 FUNCTION(atest_tsens2),
992 FUNCTION(atest_usb1),
993 FUNCTION(atest_usb10),
994 FUNCTION(atest_usb11),
995 FUNCTION(atest_usb12),
996 FUNCTION(atest_usb13),
997 FUNCTION(atest_usb2),
998 FUNCTION(atest_usb20),
999 FUNCTION(atest_usb21),
1000 FUNCTION(atest_usb22),
1001 FUNCTION(atest_usb23),
1002 FUNCTION(audio_ref),
1003 FUNCTION(btfm_slimbus),
1004 FUNCTION(cam_mclk),
1005 FUNCTION(cci_async),
1006 FUNCTION(cci_i2c),
1007 FUNCTION(cci_timer0),
1008 FUNCTION(cci_timer1),
1009 FUNCTION(cci_timer2),
1010 FUNCTION(cci_timer3),
1011 FUNCTION(cci_timer4),
1012 FUNCTION(cri_trng),
1013 FUNCTION(cri_trng0),
1014 FUNCTION(cri_trng1),
1015 FUNCTION(dbg_out),
1016 FUNCTION(ddr_bist),
1017 FUNCTION(ddr_pxi0),
1018 FUNCTION(ddr_pxi1),
1019 FUNCTION(ddr_pxi2),
1020 FUNCTION(ddr_pxi3),
1021 FUNCTION(edp_hot),
1022 FUNCTION(edp_lcd),
1023 FUNCTION(gcc_gp1),
1024 FUNCTION(gcc_gp2),
1025 FUNCTION(gcc_gp3),
1026 FUNCTION(jitter_bist),
1027 FUNCTION(ldo_en),
1028 FUNCTION(ldo_update),
1029 FUNCTION(lpass_slimbus),
1030 FUNCTION(m_voc),
1031 FUNCTION(mdp_vsync),
1032 FUNCTION(mdp_vsync0),
1033 FUNCTION(mdp_vsync1),
1034 FUNCTION(mdp_vsync2),
1035 FUNCTION(mdp_vsync3),
1036 FUNCTION(mss_lte),
1037 FUNCTION(nav_pps),
1038 FUNCTION(pa_indicator),
1039 FUNCTION(pci_e0),
1040 FUNCTION(pci_e1),
1041 FUNCTION(phase_flag),
1042 FUNCTION(pll_bist),
1043 FUNCTION(pll_bypassnl),
1044 FUNCTION(pll_reset),
1045 FUNCTION(pri_mi2s),
1046 FUNCTION(pri_mi2s_ws),
1047 FUNCTION(prng_rosc),
1048 FUNCTION(qdss_cti),
1049 FUNCTION(qdss),
1050 FUNCTION(qlink_enable),
1051 FUNCTION(qlink_request),
1052 FUNCTION(qspi_clk),
1053 FUNCTION(qspi_cs),
1054 FUNCTION(qspi_data),
1055 FUNCTION(qua_mi2s),
1056 FUNCTION(qup0),
1057 FUNCTION(qup1),
1058 FUNCTION(qup10),
1059 FUNCTION(qup11),
1060 FUNCTION(qup12),
1061 FUNCTION(qup13),
1062 FUNCTION(qup14),
1063 FUNCTION(qup15),
1064 FUNCTION(qup2),
1065 FUNCTION(qup3),
1066 FUNCTION(qup4),
1067 FUNCTION(qup5),
1068 FUNCTION(qup6),
1069 FUNCTION(qup7),
1070 FUNCTION(qup8),
1071 FUNCTION(qup9),
1072 FUNCTION(qup_l4),
1073 FUNCTION(qup_l5),
1074 FUNCTION(qup_l6),
1075 FUNCTION(sd_write),
1076 FUNCTION(sdc4_clk),
1077 FUNCTION(sdc4_cmd),
1078 FUNCTION(sdc4_data),
1079 FUNCTION(sec_mi2s),
1080 FUNCTION(sp_cmu),
1081 FUNCTION(spkr_i2s),
1082 FUNCTION(ter_mi2s),
1083 FUNCTION(tgu_ch0),
1084 FUNCTION(tgu_ch1),
1085 FUNCTION(tgu_ch2),
1086 FUNCTION(tgu_ch3),
1087 FUNCTION(tsense_pwm1),
1088 FUNCTION(tsense_pwm2),
1089 FUNCTION(tsif1_clk),
1090 FUNCTION(tsif1_data),
1091 FUNCTION(tsif1_en),
1092 FUNCTION(tsif1_error),
1093 FUNCTION(tsif1_sync),
1094 FUNCTION(tsif2_clk),
1095 FUNCTION(tsif2_data),
1096 FUNCTION(tsif2_en),
1097 FUNCTION(tsif2_error),
1098 FUNCTION(tsif2_sync),
1099 FUNCTION(uim1_clk),
1100 FUNCTION(uim1_data),
1101 FUNCTION(uim1_present),
1102 FUNCTION(uim1_reset),
1103 FUNCTION(uim2_clk),
1104 FUNCTION(uim2_data),
1105 FUNCTION(uim2_present),
1106 FUNCTION(uim2_reset),
1107 FUNCTION(uim_batt),
1108 FUNCTION(usb_phy),
1109 FUNCTION(vfr_1),
1110 FUNCTION(vsense_trigger),
1111 FUNCTION(wlan1_adc0),
1112 FUNCTION(wlan1_adc1),
1113 FUNCTION(wlan2_adc0),
1114 FUNCTION(wlan2_adc1),
1115};
1116
1117/* Every pin is maintained as a single group, and missing or non-existing pin
1118 * would be maintained as dummy group to synchronize pin group index with
1119 * pin descriptor registered with pinctrl core.
1120 * Clients would not be able to request these dummy pin groups.
1121 */
1122static const struct msm_pingroup sdm845_groups[] = {
1123 PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _),
1124 PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _),
1125 PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _),
1126 PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _),
1127 PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1128 PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1129 PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _),
1130 PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
1131 PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1132 PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _),
1133 PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _),
1134 PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _),
1135 PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _),
1136 PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _),
1137 PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _),
1138 PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1139 PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1140 PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _),
1141 PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1142 PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1143 PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1144 PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _),
1145 PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _),
1146 PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _),
1147 PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _),
1148 PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _),
1149 PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _),
1150 PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1151 PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1152 PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _),
1153 PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _),
1154 PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1155 PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1156 PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1157 PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1158 PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _),
1159 PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _),
1160 PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _),
1161 PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _),
1162 PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _),
1163 PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _),
1164 PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1165 PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1166 PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1167 PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1168 PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _),
1169 PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _),
1170 PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _),
1171 PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _),
1172 PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1173 PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1174 PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _),
1175 PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _),
1176 PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1177 PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _),
1178 PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1179 PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1180 PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _),
1181 PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _),
1182 PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _),
1183 PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _),
1184 PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _),
1185 PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _),
1186 PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _),
1187 PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _),
1188 PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1189 PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _),
1190 PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1191 PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1192 PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _),
1193 PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1194 PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1195 PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1196 PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _),
1197 PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _),
1198 PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _),
1199 PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _),
1200 PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _),
1201 PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _),
1202 PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _),
1203 PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _),
1204 PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1205 PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1206 PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1207 PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _),
1208 PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _),
1209 PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _),
1210 PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _),
1211 PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _),
1212 PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _),
1213 PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1,
1214 mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
1215 PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _),
1216 PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _),
1217 PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _),
1218 PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _),
1219 PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _),
1220 PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _),
1221 PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _),
1222 PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
1223 PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1224 PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1225 PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _),
1226 PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _),
1227 PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _),
1228 PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _),
1229 PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _),
1230 PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _),
1231 PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _),
1232 PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _),
1233 PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _),
1234 PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _),
1235 PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _),
1236 PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _),
1237 PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _),
1238 PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1239 PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1240 PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _),
1241 PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1242 PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _),
1243 PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1244 PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1245 PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1246 PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _),
1247 PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _),
1248 PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _),
1249 PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _),
1250 PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _),
1251 PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _),
1252 PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1253 PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1254 PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _),
1255 PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _),
1256 PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _),
1257 PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _),
1258 PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _),
1259 PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _),
1260 PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _),
1261 PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1262 PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1263 PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1264 PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1265 PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1266 PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1267 PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _),
1268 PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1269 PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1270 PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _),
1271 PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
1272 PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
1273 PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
1274 SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
1275 SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
1276 SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
1277 UFS_RESET(ufs_reset, 0x99f000),
1278};
1279
1280static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
1281 .pins = sdm845_pins,
1282 .npins = ARRAY_SIZE(sdm845_pins),
1283 .functions = sdm845_functions,
1284 .nfunctions = ARRAY_SIZE(sdm845_functions),
1285 .groups = sdm845_groups,
1286 .ngroups = ARRAY_SIZE(sdm845_groups),
1287 .ngpios = 150,
1288};
1289
1290static int sdm845_pinctrl_probe(struct platform_device *pdev)
1291{
1292 return msm_pinctrl_probe(pdev, &sdm845_pinctrl);
1293}
1294
1295static const struct of_device_id sdm845_pinctrl_of_match[] = {
1296 { .compatible = "qcom,sdm845-pinctrl", },
1297 { },
1298};
1299
1300static struct platform_driver sdm845_pinctrl_driver = {
1301 .driver = {
1302 .name = "sdm845-pinctrl",
1303 .pm = &msm_pinctrl_dev_pm_ops,
1304 .of_match_table = sdm845_pinctrl_of_match,
1305 },
1306 .probe = sdm845_pinctrl_probe,
1307 .remove = msm_pinctrl_remove,
1308};
1309
1310static int __init sdm845_pinctrl_init(void)
1311{
1312 return platform_driver_register(&sdm845_pinctrl_driver);
1313}
1314arch_initcall(sdm845_pinctrl_init);
1315
1316static void __exit sdm845_pinctrl_exit(void)
1317{
1318 platform_driver_unregister(&sdm845_pinctrl_driver);
1319}
1320module_exit(sdm845_pinctrl_exit);
1321
1322MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");
1323MODULE_LICENSE("GPL v2");
1324MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);