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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DM_PP_SMU_IF__H
27#define DM_PP_SMU_IF__H
28
29/*
30 * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
31 */
32
33enum pp_smu_ver {
34 /*
35 * PP_SMU_INTERFACE_X should be interpreted as the interface defined
36 * starting from X, where X is some family of ASICs. This is as
37 * opposed to interfaces used only for X. There will be some degree
38 * of interface sharing between families of ASIcs.
39 */
40 PP_SMU_UNSUPPORTED,
41 PP_SMU_VER_RV,
42 PP_SMU_VER_MAX
43};
44
45struct pp_smu {
46 enum pp_smu_ver ver;
47 const void *pp;
48
49 /*
50 * interim extra handle for backwards compatibility
51 * as some existing functionality not yet implemented
52 * by ppsmu
53 */
54 const void *dm;
55};
56
57struct pp_smu_wm_set_range {
58 unsigned int wm_inst;
59 uint32_t min_fill_clk_mhz;
60 uint32_t max_fill_clk_mhz;
61 uint32_t min_drain_clk_mhz;
62 uint32_t max_drain_clk_mhz;
63};
64
65#define MAX_WATERMARK_SETS 4
66
67struct pp_smu_wm_range_sets {
68 unsigned int num_reader_wm_sets;
69 struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS];
70
71 unsigned int num_writer_wm_sets;
72 struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS];
73};
74
75struct pp_smu_display_requirement_rv {
76 /* PPSMC_MSG_SetDisplayCount: count
77 * 0 triggers S0i2 optimization
78 */
79 unsigned int display_count;
80
81 /* PPSMC_MSG_SetHardMinFclkByFreq: mhz
82 * FCLK will vary with DPM, but never below requested hard min
83 */
84 unsigned int hard_min_fclk_mhz;
85
86 /* PPSMC_MSG_SetHardMinDcefclkByFreq: mhz
87 * fixed clock at requested freq, either from FCH bypass or DFS
88 */
89 unsigned int hard_min_dcefclk_mhz;
90
91 /* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
92 * when DF is in cstate, dcf clock is further divided down
93 * to just above given frequency
94 */
95 unsigned int min_deep_sleep_dcefclk_mhz;
96};
97
98struct pp_smu_funcs_rv {
99 struct pp_smu pp_smu;
100
101 /* PPSMC_MSG_SetDisplayCount
102 * 0 triggers S0i2 optimization
103 */
104 void (*set_display_count)(struct pp_smu *pp, int count);
105
106 /* reader and writer WM's are sent together as part of one table*/
107 /*
108 * PPSMC_MSG_SetDriverDramAddrHigh
109 * PPSMC_MSG_SetDriverDramAddrLow
110 * PPSMC_MSG_TransferTableDram2Smu
111 *
112 * */
113 void (*set_wm_ranges)(struct pp_smu *pp,
114 struct pp_smu_wm_range_sets *ranges);
115
116 /* PPSMC_MSG_SetHardMinDcfclkByFreq
117 * fixed clock at requested freq, either from FCH bypass or DFS
118 */
119 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
120
121 /* PPSMC_MSG_SetMinDeepSleepDcfclk
122 * when DF is in cstate, dcf clock is further divided down
123 * to just above given frequency
124 */
125 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
126
127 /* PPSMC_MSG_SetHardMinFclkByFreq
128 * FCLK will vary with DPM, but never below requested hard min
129 */
130 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
131
132 /* PPSMC_MSG_SetHardMinSocclkByFreq
133 * Needed for DWB support
134 */
135 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
136
137 /* PME w/a */
138 void (*set_pme_wa_enable)(struct pp_smu *pp);
139
140 /*
141 * Legacy functions. Used for backwards comp. with existing
142 * PPlib code.
143 */
144 void (*set_display_requirement)(struct pp_smu *pp,
145 struct pp_smu_display_requirement_rv *req);
146};
147
148struct pp_smu_funcs {
149 struct pp_smu ctx;
150 union {
151 struct pp_smu_funcs_rv rv_funcs;
152 };
153};
154
155#endif /* DM_PP_SMU_IF__H */