Linux kernel mirror (for testing)
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linux
1/*
2 * arch/xtensa/kernel/setup.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Kevin Chea
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16 */
17
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/mm.h>
21#include <linux/proc_fs.h>
22#include <linux/screen_info.h>
23#include <linux/kernel.h>
24#include <linux/percpu.h>
25#include <linux/cpu.h>
26#include <linux/of.h>
27#include <linux/of_fdt.h>
28
29#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30# include <linux/console.h>
31#endif
32
33#ifdef CONFIG_PROC_FS
34# include <linux/seq_file.h>
35#endif
36
37#include <asm/bootparam.h>
38#include <asm/kasan.h>
39#include <asm/mmu_context.h>
40#include <asm/pgtable.h>
41#include <asm/processor.h>
42#include <asm/timex.h>
43#include <asm/platform.h>
44#include <asm/page.h>
45#include <asm/setup.h>
46#include <asm/param.h>
47#include <asm/smp.h>
48#include <asm/sysmem.h>
49
50#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
51struct screen_info screen_info = {
52 .orig_x = 0,
53 .orig_y = 24,
54 .orig_video_cols = 80,
55 .orig_video_lines = 24,
56 .orig_video_isVGA = 1,
57 .orig_video_points = 16,
58};
59#endif
60
61#ifdef CONFIG_BLK_DEV_INITRD
62extern unsigned long initrd_start;
63extern unsigned long initrd_end;
64int initrd_is_mapped = 0;
65extern int initrd_below_start_ok;
66#endif
67
68#ifdef CONFIG_OF
69void *dtb_start = __dtb_start;
70#endif
71
72extern unsigned long loops_per_jiffy;
73
74/* Command line specified as configuration option. */
75
76static char __initdata command_line[COMMAND_LINE_SIZE];
77
78#ifdef CONFIG_CMDLINE_BOOL
79static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
80#endif
81
82#ifdef CONFIG_PARSE_BOOTPARAM
83/*
84 * Boot parameter parsing.
85 *
86 * The Xtensa port uses a list of variable-sized tags to pass data to
87 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
88 * to be recognised. The list is terminated with a zero-sized
89 * BP_TAG_LAST tag.
90 */
91
92typedef struct tagtable {
93 u32 tag;
94 int (*parse)(const bp_tag_t*);
95} tagtable_t;
96
97#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
98 __attribute__((used, section(".taglist"))) = { tag, fn }
99
100/* parse current tag */
101
102static int __init parse_tag_mem(const bp_tag_t *tag)
103{
104 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
105
106 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
107 return -1;
108
109 return memblock_add(mi->start, mi->end - mi->start);
110}
111
112__tagtable(BP_TAG_MEMORY, parse_tag_mem);
113
114#ifdef CONFIG_BLK_DEV_INITRD
115
116static int __init parse_tag_initrd(const bp_tag_t* tag)
117{
118 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
119
120 initrd_start = (unsigned long)__va(mi->start);
121 initrd_end = (unsigned long)__va(mi->end);
122
123 return 0;
124}
125
126__tagtable(BP_TAG_INITRD, parse_tag_initrd);
127
128#endif /* CONFIG_BLK_DEV_INITRD */
129
130#ifdef CONFIG_OF
131
132static int __init parse_tag_fdt(const bp_tag_t *tag)
133{
134 dtb_start = __va(tag->data[0]);
135 return 0;
136}
137
138__tagtable(BP_TAG_FDT, parse_tag_fdt);
139
140#endif /* CONFIG_OF */
141
142static int __init parse_tag_cmdline(const bp_tag_t* tag)
143{
144 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
145 return 0;
146}
147
148__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
149
150static int __init parse_bootparam(const bp_tag_t* tag)
151{
152 extern tagtable_t __tagtable_begin, __tagtable_end;
153 tagtable_t *t;
154
155 /* Boot parameters must start with a BP_TAG_FIRST tag. */
156
157 if (tag->id != BP_TAG_FIRST) {
158 pr_warn("Invalid boot parameters!\n");
159 return 0;
160 }
161
162 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
163
164 /* Parse all tags. */
165
166 while (tag != NULL && tag->id != BP_TAG_LAST) {
167 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
168 if (tag->id == t->tag) {
169 t->parse(tag);
170 break;
171 }
172 }
173 if (t == &__tagtable_end)
174 pr_warn("Ignoring tag 0x%08x\n", tag->id);
175 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
176 }
177
178 return 0;
179}
180#else
181static int __init parse_bootparam(const bp_tag_t *tag)
182{
183 pr_info("Ignoring boot parameters at %p\n", tag);
184 return 0;
185}
186#endif
187
188#ifdef CONFIG_OF
189
190#if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
191unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
192EXPORT_SYMBOL(xtensa_kio_paddr);
193
194static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
195 int depth, void *data)
196{
197 const __be32 *ranges;
198 int len;
199
200 if (depth > 1)
201 return 0;
202
203 if (!of_flat_dt_is_compatible(node, "simple-bus"))
204 return 0;
205
206 ranges = of_get_flat_dt_prop(node, "ranges", &len);
207 if (!ranges)
208 return 1;
209 if (len == 0)
210 return 1;
211
212 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
213 /* round down to nearest 256MB boundary */
214 xtensa_kio_paddr &= 0xf0000000;
215
216 init_kio();
217
218 return 1;
219}
220#else
221static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
222 int depth, void *data)
223{
224 return 1;
225}
226#endif
227
228void __init early_init_devtree(void *params)
229{
230 early_init_dt_scan(params);
231 of_scan_flat_dt(xtensa_dt_io_area, NULL);
232
233 if (!command_line[0])
234 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
235}
236
237#endif /* CONFIG_OF */
238
239/*
240 * Initialize architecture. (Early stage)
241 */
242
243void __init init_arch(bp_tag_t *bp_start)
244{
245 /* Initialize MMU. */
246
247 init_mmu();
248
249 /* Initialize initial KASAN shadow map */
250
251 kasan_early_init();
252
253 /* Parse boot parameters */
254
255 if (bp_start)
256 parse_bootparam(bp_start);
257
258#ifdef CONFIG_OF
259 early_init_devtree(dtb_start);
260#endif
261
262#ifdef CONFIG_CMDLINE_BOOL
263 if (!command_line[0])
264 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
265#endif
266
267 /* Early hook for platforms */
268
269 platform_init(bp_start);
270}
271
272/*
273 * Initialize system. Setup memory and reserve regions.
274 */
275
276extern char _end[];
277extern char _stext[];
278extern char _WindowVectors_text_start;
279extern char _WindowVectors_text_end;
280extern char _DebugInterruptVector_text_start;
281extern char _DebugInterruptVector_text_end;
282extern char _KernelExceptionVector_text_start;
283extern char _KernelExceptionVector_text_end;
284extern char _UserExceptionVector_text_start;
285extern char _UserExceptionVector_text_end;
286extern char _DoubleExceptionVector_text_start;
287extern char _DoubleExceptionVector_text_end;
288#if XCHAL_EXCM_LEVEL >= 2
289extern char _Level2InterruptVector_text_start;
290extern char _Level2InterruptVector_text_end;
291#endif
292#if XCHAL_EXCM_LEVEL >= 3
293extern char _Level3InterruptVector_text_start;
294extern char _Level3InterruptVector_text_end;
295#endif
296#if XCHAL_EXCM_LEVEL >= 4
297extern char _Level4InterruptVector_text_start;
298extern char _Level4InterruptVector_text_end;
299#endif
300#if XCHAL_EXCM_LEVEL >= 5
301extern char _Level5InterruptVector_text_start;
302extern char _Level5InterruptVector_text_end;
303#endif
304#if XCHAL_EXCM_LEVEL >= 6
305extern char _Level6InterruptVector_text_start;
306extern char _Level6InterruptVector_text_end;
307#endif
308#ifdef CONFIG_SMP
309extern char _SecondaryResetVector_text_start;
310extern char _SecondaryResetVector_text_end;
311#endif
312
313static inline int mem_reserve(unsigned long start, unsigned long end)
314{
315 return memblock_reserve(start, end - start);
316}
317
318void __init setup_arch(char **cmdline_p)
319{
320 pr_info("config ID: %08x:%08x\n",
321 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
322 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
323 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
324 pr_info("built for config ID: %08x:%08x\n",
325 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
326
327 *cmdline_p = command_line;
328 platform_setup(cmdline_p);
329 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
330
331 /* Reserve some memory regions */
332
333#ifdef CONFIG_BLK_DEV_INITRD
334 if (initrd_start < initrd_end) {
335 initrd_is_mapped = mem_reserve(__pa(initrd_start),
336 __pa(initrd_end)) == 0;
337 initrd_below_start_ok = 1;
338 } else {
339 initrd_start = 0;
340 }
341#endif
342
343 mem_reserve(__pa(_stext), __pa(_end));
344
345#ifdef CONFIG_VECTORS_OFFSET
346 mem_reserve(__pa(&_WindowVectors_text_start),
347 __pa(&_WindowVectors_text_end));
348
349 mem_reserve(__pa(&_DebugInterruptVector_text_start),
350 __pa(&_DebugInterruptVector_text_end));
351
352 mem_reserve(__pa(&_KernelExceptionVector_text_start),
353 __pa(&_KernelExceptionVector_text_end));
354
355 mem_reserve(__pa(&_UserExceptionVector_text_start),
356 __pa(&_UserExceptionVector_text_end));
357
358 mem_reserve(__pa(&_DoubleExceptionVector_text_start),
359 __pa(&_DoubleExceptionVector_text_end));
360
361#if XCHAL_EXCM_LEVEL >= 2
362 mem_reserve(__pa(&_Level2InterruptVector_text_start),
363 __pa(&_Level2InterruptVector_text_end));
364#endif
365#if XCHAL_EXCM_LEVEL >= 3
366 mem_reserve(__pa(&_Level3InterruptVector_text_start),
367 __pa(&_Level3InterruptVector_text_end));
368#endif
369#if XCHAL_EXCM_LEVEL >= 4
370 mem_reserve(__pa(&_Level4InterruptVector_text_start),
371 __pa(&_Level4InterruptVector_text_end));
372#endif
373#if XCHAL_EXCM_LEVEL >= 5
374 mem_reserve(__pa(&_Level5InterruptVector_text_start),
375 __pa(&_Level5InterruptVector_text_end));
376#endif
377#if XCHAL_EXCM_LEVEL >= 6
378 mem_reserve(__pa(&_Level6InterruptVector_text_start),
379 __pa(&_Level6InterruptVector_text_end));
380#endif
381
382#endif /* CONFIG_VECTORS_OFFSET */
383
384#ifdef CONFIG_SMP
385 mem_reserve(__pa(&_SecondaryResetVector_text_start),
386 __pa(&_SecondaryResetVector_text_end));
387#endif
388 parse_early_param();
389 bootmem_init();
390 kasan_init();
391 unflatten_and_copy_device_tree();
392
393#ifdef CONFIG_SMP
394 smp_init_cpus();
395#endif
396
397 paging_init();
398 zones_init();
399
400#ifdef CONFIG_VT
401# if defined(CONFIG_VGA_CONSOLE)
402 conswitchp = &vga_con;
403# elif defined(CONFIG_DUMMY_CONSOLE)
404 conswitchp = &dummy_con;
405# endif
406#endif
407
408#ifdef CONFIG_PCI
409 platform_pcibios_init();
410#endif
411}
412
413static DEFINE_PER_CPU(struct cpu, cpu_data);
414
415static int __init topology_init(void)
416{
417 int i;
418
419 for_each_possible_cpu(i) {
420 struct cpu *cpu = &per_cpu(cpu_data, i);
421 cpu->hotpluggable = !!i;
422 register_cpu(cpu, i);
423 }
424
425 return 0;
426}
427subsys_initcall(topology_init);
428
429void cpu_reset(void)
430{
431#if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
432 local_irq_disable();
433 /*
434 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
435 * be flushed.
436 * Way 4 is not currently used by linux.
437 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
438 * Way 5 shall be flushed and way 6 shall be set to identity mapping
439 * on MMUv3.
440 */
441 local_flush_tlb_all();
442 invalidate_page_directory();
443#if XCHAL_HAVE_SPANNING_WAY
444 /* MMU v3 */
445 {
446 unsigned long vaddr = (unsigned long)cpu_reset;
447 unsigned long paddr = __pa(vaddr);
448 unsigned long tmpaddr = vaddr + SZ_512M;
449 unsigned long tmp0, tmp1, tmp2, tmp3;
450
451 /*
452 * Find a place for the temporary mapping. It must not be
453 * in the same 512MB region with vaddr or paddr, otherwise
454 * there may be multihit exception either on entry to the
455 * temporary mapping, or on entry to the identity mapping.
456 * (512MB is the biggest page size supported by TLB.)
457 */
458 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
459 tmpaddr += SZ_512M;
460
461 /* Invalidate mapping in the selected temporary area */
462 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
463 invalidate_itlb_entry(itlb_probe(tmpaddr));
464 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
465 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
466
467 /*
468 * Map two consecutive pages starting at the physical address
469 * of this function to the temporary mapping area.
470 */
471 write_itlb_entry(__pte((paddr & PAGE_MASK) |
472 _PAGE_HW_VALID |
473 _PAGE_HW_EXEC |
474 _PAGE_CA_BYPASS),
475 tmpaddr & PAGE_MASK);
476 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
477 _PAGE_HW_VALID |
478 _PAGE_HW_EXEC |
479 _PAGE_CA_BYPASS),
480 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
481
482 /* Reinitialize TLB */
483 __asm__ __volatile__ ("movi %0, 1f\n\t"
484 "movi %3, 2f\n\t"
485 "add %0, %0, %4\n\t"
486 "add %3, %3, %5\n\t"
487 "jx %0\n"
488 /*
489 * No literal, data or stack access
490 * below this point
491 */
492 "1:\n\t"
493 /* Initialize *tlbcfg */
494 "movi %0, 0\n\t"
495 "wsr %0, itlbcfg\n\t"
496 "wsr %0, dtlbcfg\n\t"
497 /* Invalidate TLB way 5 */
498 "movi %0, 4\n\t"
499 "movi %1, 5\n"
500 "1:\n\t"
501 "iitlb %1\n\t"
502 "idtlb %1\n\t"
503 "add %1, %1, %6\n\t"
504 "addi %0, %0, -1\n\t"
505 "bnez %0, 1b\n\t"
506 /* Initialize TLB way 6 */
507 "movi %0, 7\n\t"
508 "addi %1, %9, 3\n\t"
509 "addi %2, %9, 6\n"
510 "1:\n\t"
511 "witlb %1, %2\n\t"
512 "wdtlb %1, %2\n\t"
513 "add %1, %1, %7\n\t"
514 "add %2, %2, %7\n\t"
515 "addi %0, %0, -1\n\t"
516 "bnez %0, 1b\n\t"
517 /* Jump to identity mapping */
518 "jx %3\n"
519 "2:\n\t"
520 /* Complete way 6 initialization */
521 "witlb %1, %2\n\t"
522 "wdtlb %1, %2\n\t"
523 /* Invalidate temporary mapping */
524 "sub %0, %9, %7\n\t"
525 "iitlb %0\n\t"
526 "add %0, %0, %8\n\t"
527 "iitlb %0"
528 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
529 "=&a"(tmp3)
530 : "a"(tmpaddr - vaddr),
531 "a"(paddr - vaddr),
532 "a"(SZ_128M), "a"(SZ_512M),
533 "a"(PAGE_SIZE),
534 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
535 : "memory");
536 }
537#endif
538#endif
539 __asm__ __volatile__ ("movi a2, 0\n\t"
540 "wsr a2, icountlevel\n\t"
541 "movi a2, 0\n\t"
542 "wsr a2, icount\n\t"
543#if XCHAL_NUM_IBREAK > 0
544 "wsr a2, ibreakenable\n\t"
545#endif
546#if XCHAL_HAVE_LOOPS
547 "wsr a2, lcount\n\t"
548#endif
549 "movi a2, 0x1f\n\t"
550 "wsr a2, ps\n\t"
551 "isync\n\t"
552 "jx %0\n\t"
553 :
554 : "a" (XCHAL_RESET_VECTOR_VADDR)
555 : "a2");
556 for (;;)
557 ;
558}
559
560void machine_restart(char * cmd)
561{
562 platform_restart();
563}
564
565void machine_halt(void)
566{
567 platform_halt();
568 while (1);
569}
570
571void machine_power_off(void)
572{
573 platform_power_off();
574 while (1);
575}
576#ifdef CONFIG_PROC_FS
577
578/*
579 * Display some core information through /proc/cpuinfo.
580 */
581
582static int
583c_show(struct seq_file *f, void *slot)
584{
585 /* high-level stuff */
586 seq_printf(f, "CPU count\t: %u\n"
587 "CPU list\t: %*pbl\n"
588 "vendor_id\t: Tensilica\n"
589 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
590 "core ID\t\t: " XCHAL_CORE_ID "\n"
591 "build ID\t: 0x%x\n"
592 "config ID\t: %08x:%08x\n"
593 "byte order\t: %s\n"
594 "cpu MHz\t\t: %lu.%02lu\n"
595 "bogomips\t: %lu.%02lu\n",
596 num_online_cpus(),
597 cpumask_pr_args(cpu_online_mask),
598 XCHAL_BUILD_UNIQUE_ID,
599 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
600 XCHAL_HAVE_BE ? "big" : "little",
601 ccount_freq/1000000,
602 (ccount_freq/10000) % 100,
603 loops_per_jiffy/(500000/HZ),
604 (loops_per_jiffy/(5000/HZ)) % 100);
605 seq_puts(f, "flags\t\t: "
606#if XCHAL_HAVE_NMI
607 "nmi "
608#endif
609#if XCHAL_HAVE_DEBUG
610 "debug "
611# if XCHAL_HAVE_OCD
612 "ocd "
613# endif
614#endif
615#if XCHAL_HAVE_DENSITY
616 "density "
617#endif
618#if XCHAL_HAVE_BOOLEANS
619 "boolean "
620#endif
621#if XCHAL_HAVE_LOOPS
622 "loop "
623#endif
624#if XCHAL_HAVE_NSA
625 "nsa "
626#endif
627#if XCHAL_HAVE_MINMAX
628 "minmax "
629#endif
630#if XCHAL_HAVE_SEXT
631 "sext "
632#endif
633#if XCHAL_HAVE_CLAMPS
634 "clamps "
635#endif
636#if XCHAL_HAVE_MAC16
637 "mac16 "
638#endif
639#if XCHAL_HAVE_MUL16
640 "mul16 "
641#endif
642#if XCHAL_HAVE_MUL32
643 "mul32 "
644#endif
645#if XCHAL_HAVE_MUL32_HIGH
646 "mul32h "
647#endif
648#if XCHAL_HAVE_FP
649 "fpu "
650#endif
651#if XCHAL_HAVE_S32C1I
652 "s32c1i "
653#endif
654 "\n");
655
656 /* Registers. */
657 seq_printf(f,"physical aregs\t: %d\n"
658 "misc regs\t: %d\n"
659 "ibreak\t\t: %d\n"
660 "dbreak\t\t: %d\n",
661 XCHAL_NUM_AREGS,
662 XCHAL_NUM_MISC_REGS,
663 XCHAL_NUM_IBREAK,
664 XCHAL_NUM_DBREAK);
665
666
667 /* Interrupt. */
668 seq_printf(f,"num ints\t: %d\n"
669 "ext ints\t: %d\n"
670 "int levels\t: %d\n"
671 "timers\t\t: %d\n"
672 "debug level\t: %d\n",
673 XCHAL_NUM_INTERRUPTS,
674 XCHAL_NUM_EXTINTERRUPTS,
675 XCHAL_NUM_INTLEVELS,
676 XCHAL_NUM_TIMERS,
677 XCHAL_DEBUGLEVEL);
678
679 /* Cache */
680 seq_printf(f,"icache line size: %d\n"
681 "icache ways\t: %d\n"
682 "icache size\t: %d\n"
683 "icache flags\t: "
684#if XCHAL_ICACHE_LINE_LOCKABLE
685 "lock "
686#endif
687 "\n"
688 "dcache line size: %d\n"
689 "dcache ways\t: %d\n"
690 "dcache size\t: %d\n"
691 "dcache flags\t: "
692#if XCHAL_DCACHE_IS_WRITEBACK
693 "writeback "
694#endif
695#if XCHAL_DCACHE_LINE_LOCKABLE
696 "lock "
697#endif
698 "\n",
699 XCHAL_ICACHE_LINESIZE,
700 XCHAL_ICACHE_WAYS,
701 XCHAL_ICACHE_SIZE,
702 XCHAL_DCACHE_LINESIZE,
703 XCHAL_DCACHE_WAYS,
704 XCHAL_DCACHE_SIZE);
705
706 return 0;
707}
708
709/*
710 * We show only CPU #0 info.
711 */
712static void *
713c_start(struct seq_file *f, loff_t *pos)
714{
715 return (*pos == 0) ? (void *)1 : NULL;
716}
717
718static void *
719c_next(struct seq_file *f, void *v, loff_t *pos)
720{
721 return NULL;
722}
723
724static void
725c_stop(struct seq_file *f, void *v)
726{
727}
728
729const struct seq_operations cpuinfo_op =
730{
731 .start = c_start,
732 .next = c_next,
733 .stop = c_stop,
734 .show = c_show,
735};
736
737#endif /* CONFIG_PROC_FS */