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1#ifndef _ASM_POWERPC_PROCESSOR_H
2#define _ASM_POWERPC_PROCESSOR_H
3
4/*
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <asm/reg.h>
14
15#ifdef CONFIG_VSX
16#define TS_FPRWIDTH 2
17
18#ifdef __BIG_ENDIAN__
19#define TS_FPROFFSET 0
20#define TS_VSRLOWOFFSET 1
21#else
22#define TS_FPROFFSET 1
23#define TS_VSRLOWOFFSET 0
24#endif
25
26#else
27#define TS_FPRWIDTH 1
28#define TS_FPROFFSET 0
29#endif
30
31#ifdef CONFIG_PPC64
32/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
33#define PPR_PRIORITY 3
34#ifdef __ASSEMBLY__
35#define DEFAULT_PPR (PPR_PRIORITY << 50)
36#else
37#define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
38#endif /* __ASSEMBLY__ */
39#endif /* CONFIG_PPC64 */
40
41#ifndef __ASSEMBLY__
42#include <linux/types.h>
43#include <linux/thread_info.h>
44#include <asm/ptrace.h>
45#include <asm/hw_breakpoint.h>
46
47/* We do _not_ want to define new machine types at all, those must die
48 * in favor of using the device-tree
49 * -- BenH.
50 */
51
52/* PREP sub-platform types. Unused */
53#define _PREP_Motorola 0x01 /* motorola prep */
54#define _PREP_Firm 0x02 /* firmworks prep */
55#define _PREP_IBM 0x00 /* ibm prep */
56#define _PREP_Bull 0x03 /* bull prep */
57
58/* CHRP sub-platform types. These are arbitrary */
59#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
60#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
61#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
62#define _CHRP_briq 0x07 /* TotalImpact's briQ */
63
64#if defined(__KERNEL__) && defined(CONFIG_PPC32)
65
66extern int _chrp_type;
67
68#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
69
70/* Macros for adjusting thread priority (hardware multi-threading) */
71#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
72#define HMT_low() asm volatile("or 1,1,1 # low priority")
73#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
74#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
75#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
76#define HMT_high() asm volatile("or 3,3,3 # high priority")
77
78#ifdef __KERNEL__
79
80#ifdef CONFIG_PPC64
81#include <asm/task_size_64.h>
82#else
83#include <asm/task_size_32.h>
84#endif
85
86struct task_struct;
87void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
88void release_thread(struct task_struct *);
89
90typedef struct {
91 unsigned long seg;
92} mm_segment_t;
93
94#define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
95#define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
96
97/* FP and VSX 0-31 register set */
98struct thread_fp_state {
99 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
100 u64 fpscr; /* Floating point status */
101};
102
103/* Complete AltiVec register set including VSCR */
104struct thread_vr_state {
105 vector128 vr[32] __attribute__((aligned(16)));
106 vector128 vscr __attribute__((aligned(16)));
107};
108
109struct debug_reg {
110#ifdef CONFIG_PPC_ADV_DEBUG_REGS
111 /*
112 * The following help to manage the use of Debug Control Registers
113 * om the BookE platforms.
114 */
115 uint32_t dbcr0;
116 uint32_t dbcr1;
117#ifdef CONFIG_BOOKE
118 uint32_t dbcr2;
119#endif
120 /*
121 * The stored value of the DBSR register will be the value at the
122 * last debug interrupt. This register can only be read from the
123 * user (will never be written to) and has value while helping to
124 * describe the reason for the last debug trap. Torez
125 */
126 uint32_t dbsr;
127 /*
128 * The following will contain addresses used by debug applications
129 * to help trace and trap on particular address locations.
130 * The bits in the Debug Control Registers above help define which
131 * of the following registers will contain valid data and/or addresses.
132 */
133 unsigned long iac1;
134 unsigned long iac2;
135#if CONFIG_PPC_ADV_DEBUG_IACS > 2
136 unsigned long iac3;
137 unsigned long iac4;
138#endif
139 unsigned long dac1;
140 unsigned long dac2;
141#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
142 unsigned long dvc1;
143 unsigned long dvc2;
144#endif
145#endif
146};
147
148struct thread_struct {
149 unsigned long ksp; /* Kernel stack pointer */
150
151#ifdef CONFIG_PPC64
152 unsigned long ksp_vsid;
153#endif
154 struct pt_regs *regs; /* Pointer to saved register state */
155 mm_segment_t addr_limit; /* for get_fs() validation */
156#ifdef CONFIG_BOOKE
157 /* BookE base exception scratch space; align on cacheline */
158 unsigned long normsave[8] ____cacheline_aligned;
159#endif
160#ifdef CONFIG_PPC32
161 void *pgdir; /* root of page-table tree */
162 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
163#ifdef CONFIG_PPC_RTAS
164 unsigned long rtas_sp; /* stack pointer for when in RTAS */
165#endif
166#endif
167 /* Debug Registers */
168 struct debug_reg debug;
169 struct thread_fp_state fp_state;
170 struct thread_fp_state *fp_save_area;
171 int fpexc_mode; /* floating-point exception mode */
172 unsigned int align_ctl; /* alignment handling control */
173#ifdef CONFIG_HAVE_HW_BREAKPOINT
174 struct perf_event *ptrace_bps[HBP_NUM];
175 /*
176 * Helps identify source of single-step exception and subsequent
177 * hw-breakpoint enablement
178 */
179 struct perf_event *last_hit_ubp;
180#endif /* CONFIG_HAVE_HW_BREAKPOINT */
181 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
182 unsigned long trap_nr; /* last trap # on this thread */
183 u8 load_slb; /* Ages out SLB preload cache entries */
184 u8 load_fp;
185#ifdef CONFIG_ALTIVEC
186 u8 load_vec;
187 struct thread_vr_state vr_state;
188 struct thread_vr_state *vr_save_area;
189 unsigned long vrsave;
190 int used_vr; /* set if process has used altivec */
191#endif /* CONFIG_ALTIVEC */
192#ifdef CONFIG_VSX
193 /* VSR status */
194 int used_vsr; /* set if process has used VSX */
195#endif /* CONFIG_VSX */
196#ifdef CONFIG_SPE
197 unsigned long evr[32]; /* upper 32-bits of SPE regs */
198 u64 acc; /* Accumulator */
199 unsigned long spefscr; /* SPE & eFP status */
200 unsigned long spefscr_last; /* SPEFSCR value on last prctl
201 call or trap return */
202 int used_spe; /* set if process has used spe */
203#endif /* CONFIG_SPE */
204#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
205 u8 load_tm;
206 u64 tm_tfhar; /* Transaction fail handler addr */
207 u64 tm_texasr; /* Transaction exception & summary */
208 u64 tm_tfiar; /* Transaction fail instr address reg */
209 struct pt_regs ckpt_regs; /* Checkpointed registers */
210
211 unsigned long tm_tar;
212 unsigned long tm_ppr;
213 unsigned long tm_dscr;
214
215 /*
216 * Checkpointed FP and VSX 0-31 register set.
217 *
218 * When a transaction is active/signalled/scheduled etc., *regs is the
219 * most recent set of/speculated GPRs with ckpt_regs being the older
220 * checkpointed regs to which we roll back if transaction aborts.
221 *
222 * These are analogous to how ckpt_regs and pt_regs work
223 */
224 struct thread_fp_state ckfp_state; /* Checkpointed FP state */
225 struct thread_vr_state ckvr_state; /* Checkpointed VR state */
226 unsigned long ckvrsave; /* Checkpointed VRSAVE */
227#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
228#ifdef CONFIG_PPC_MEM_KEYS
229 unsigned long amr;
230 unsigned long iamr;
231 unsigned long uamor;
232#endif
233#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
234 void* kvm_shadow_vcpu; /* KVM internal data */
235#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
236#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
237 struct kvm_vcpu *kvm_vcpu;
238#endif
239#ifdef CONFIG_PPC64
240 unsigned long dscr;
241 unsigned long fscr;
242 /*
243 * This member element dscr_inherit indicates that the process
244 * has explicitly attempted and changed the DSCR register value
245 * for itself. Hence kernel wont use the default CPU DSCR value
246 * contained in the PACA structure anymore during process context
247 * switch. Once this variable is set, this behaviour will also be
248 * inherited to all the children of this process from that point
249 * onwards.
250 */
251 int dscr_inherit;
252 unsigned long tidr;
253#endif
254#ifdef CONFIG_PPC_BOOK3S_64
255 unsigned long tar;
256 unsigned long ebbrr;
257 unsigned long ebbhr;
258 unsigned long bescr;
259 unsigned long siar;
260 unsigned long sdar;
261 unsigned long sier;
262 unsigned long mmcr2;
263 unsigned mmcr0;
264
265 unsigned used_ebb;
266 unsigned int used_vas;
267#endif
268};
269
270#define ARCH_MIN_TASKALIGN 16
271
272#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
273#define INIT_SP_LIMIT ((unsigned long)&init_stack)
274
275#ifdef CONFIG_SPE
276#define SPEFSCR_INIT \
277 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
278 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
279#else
280#define SPEFSCR_INIT
281#endif
282
283#ifdef CONFIG_PPC32
284#define INIT_THREAD { \
285 .ksp = INIT_SP, \
286 .ksp_limit = INIT_SP_LIMIT, \
287 .addr_limit = KERNEL_DS, \
288 .pgdir = swapper_pg_dir, \
289 .fpexc_mode = MSR_FE0 | MSR_FE1, \
290 SPEFSCR_INIT \
291}
292#else
293#define INIT_THREAD { \
294 .ksp = INIT_SP, \
295 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
296 .addr_limit = KERNEL_DS, \
297 .fpexc_mode = 0, \
298 .fscr = FSCR_TAR | FSCR_EBB \
299}
300#endif
301
302#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.regs)
303
304unsigned long get_wchan(struct task_struct *p);
305
306#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
307#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
308
309/* Get/set floating-point exception mode */
310#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
311#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
312
313extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
314extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
315
316#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
317#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
318
319extern int get_endian(struct task_struct *tsk, unsigned long adr);
320extern int set_endian(struct task_struct *tsk, unsigned int val);
321
322#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
323#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
324
325extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
326extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
327
328extern void load_fp_state(struct thread_fp_state *fp);
329extern void store_fp_state(struct thread_fp_state *fp);
330extern void load_vr_state(struct thread_vr_state *vr);
331extern void store_vr_state(struct thread_vr_state *vr);
332
333static inline unsigned int __unpack_fe01(unsigned long msr_bits)
334{
335 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
336}
337
338static inline unsigned long __pack_fe01(unsigned int fpmode)
339{
340 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
341}
342
343#ifdef CONFIG_PPC64
344#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
345
346#define spin_begin() HMT_low()
347
348#define spin_cpu_relax() barrier()
349
350#define spin_cpu_yield() spin_cpu_relax()
351
352#define spin_end() HMT_medium()
353
354#define spin_until_cond(cond) \
355do { \
356 if (unlikely(!(cond))) { \
357 spin_begin(); \
358 do { \
359 spin_cpu_relax(); \
360 } while (!(cond)); \
361 spin_end(); \
362 } \
363} while (0)
364
365#else
366#define cpu_relax() barrier()
367#endif
368
369/* Check that a certain kernel stack pointer is valid in task_struct p */
370int validate_sp(unsigned long sp, struct task_struct *p,
371 unsigned long nbytes);
372
373/*
374 * Prefetch macros.
375 */
376#define ARCH_HAS_PREFETCH
377#define ARCH_HAS_PREFETCHW
378#define ARCH_HAS_SPINLOCK_PREFETCH
379
380static inline void prefetch(const void *x)
381{
382 if (unlikely(!x))
383 return;
384
385 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
386}
387
388static inline void prefetchw(const void *x)
389{
390 if (unlikely(!x))
391 return;
392
393 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
394}
395
396#define spin_lock_prefetch(x) prefetchw(x)
397
398#define HAVE_ARCH_PICK_MMAP_LAYOUT
399
400#ifdef CONFIG_PPC64
401static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
402{
403 if (is_32)
404 return sp & 0x0ffffffffUL;
405 return sp;
406}
407#else
408static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
409{
410 return sp;
411}
412#endif
413
414extern unsigned long cpuidle_disable;
415enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
416
417extern int powersave_nap; /* set if nap mode can be used in idle loop */
418extern unsigned long power7_idle_insn(unsigned long type); /* PNV_THREAD_NAP/etc*/
419extern void power7_idle_type(unsigned long type);
420extern unsigned long power9_idle_stop(unsigned long psscr_val);
421extern unsigned long power9_offline_stop(unsigned long psscr_val);
422extern void power9_idle_type(unsigned long stop_psscr_val,
423 unsigned long stop_psscr_mask);
424
425extern void flush_instruction_cache(void);
426extern void hard_reset_now(void);
427extern void poweroff_now(void);
428extern int fix_alignment(struct pt_regs *);
429extern void cvt_fd(float *from, double *to);
430extern void cvt_df(double *from, float *to);
431extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
432
433#ifdef CONFIG_PPC64
434/*
435 * We handle most unaligned accesses in hardware. On the other hand
436 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
437 * powers of 2 writes until it reaches sufficient alignment).
438 *
439 * Based on this we disable the IP header alignment in network drivers.
440 */
441#define NET_IP_ALIGN 0
442#endif
443
444#endif /* __KERNEL__ */
445#endif /* __ASSEMBLY__ */
446#endif /* _ASM_POWERPC_PROCESSOR_H */