Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1comment "Processor Features"
2
3config CPU_BIG_ENDIAN
4 def_bool !CPU_LITTLE_ENDIAN
5
6config CPU_LITTLE_ENDIAN
7 bool "Little endian"
8 default y
9
10config FPU
11 bool "FPU support"
12 default n
13 help
14 If FPU ISA is used in user space, this configuration shall be Y to
15 enable required support in kerenl such as fpu context switch and
16 fpu exception handler.
17
18 If no FPU ISA is used in user space, say N.
19
20config LAZY_FPU
21 bool "lazy FPU support"
22 depends on FPU
23 default y
24 help
25 Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can
26 enhance system performance by reducing the context switch
27 frequency of the FPU register.
28
29 For nomal case, say Y.
30
31config SUPPORT_DENORMAL_ARITHMETIC
32 bool "Denormal arithmetic support"
33 depends on FPU
34 default n
35 help
36 Say Y here to enable arithmetic of denormalized number. Enabling
37 this feature can enhance the precision for tininess number.
38 However, performance loss in float pointe calculations is
39 possibly significant due to additional FPU exception.
40
41 If the calculated tolerance for tininess number is not critical,
42 say N to prevent performance loss.
43
44config HWZOL
45 bool "hardware zero overhead loop support"
46 depends on CPU_D10 || CPU_D15
47 default n
48 help
49 A set of Zero-Overhead Loop mechanism is provided to reduce the
50 instruction fetch and execution overhead of loop-control instructions.
51 It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
52 You don't need to save these registers if you can make sure your user
53 program doesn't use these registers.
54
55 If unsure, say N.
56
57config CPU_CACHE_ALIASING
58 bool "Aliasing cache"
59 depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
60 default y
61 help
62 If this CPU is using VIPT data cache and its cache way size is larger
63 than page size, say Y. If it is using PIPT data cache, say N.
64
65 If unsure, say Y.
66
67choice
68 prompt "minimum CPU type"
69 default CPU_V3
70 help
71 The data cache of N15/D15 is implemented as PIPT and it will not cause
72 the cache aliasing issue. The rest cpus(N13, N10 and D10) are
73 implemented as VIPT data cache. It may cause the cache aliasing issue
74 if its cache way size is larger than page size. You can specify the
75 CPU type direcly or choose CPU_V3 if unsure.
76
77 A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
78 A kernel built for N15 is able to run on N15 or D15.
79 A kernel built for D10 is able to run on D10 or D15.
80 A kernel built for D15 is able to run on D15.
81 A kernel built for N13 is able to run on N15, N13 or D15.
82
83config CPU_N15
84 bool "AndesCore N15"
85config CPU_N13
86 bool "AndesCore N13"
87 select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
88config CPU_N10
89 bool "AndesCore N10"
90 select CPU_CACHE_ALIASING
91config CPU_D15
92 bool "AndesCore D15"
93config CPU_D10
94 bool "AndesCore D10"
95 select CPU_CACHE_ALIASING
96config CPU_V3
97 bool "AndesCore v3 compatible"
98 select CPU_CACHE_ALIASING
99endchoice
100choice
101 prompt "Paging -- page size "
102 default ANDES_PAGE_SIZE_4KB
103config ANDES_PAGE_SIZE_4KB
104 bool "use 4KB page size"
105config ANDES_PAGE_SIZE_8KB
106 bool "use 8KB page size"
107endchoice
108
109config CPU_ICACHE_DISABLE
110 bool "Disable I-Cache"
111 help
112 Say Y here to disable the processor instruction cache. Unless
113 you have a reason not to or are unsure, say N.
114
115config CPU_DCACHE_DISABLE
116 bool "Disable D-Cache"
117 help
118 Say Y here to disable the processor data cache. Unless
119 you have a reason not to or are unsure, say N.
120
121config CPU_DCACHE_WRITETHROUGH
122 bool "Force write through D-cache"
123 depends on !CPU_DCACHE_DISABLE
124 help
125 Say Y here to use the data cache in writethrough mode. Unless you
126 specifically require this or are unsure, say N.
127
128config WBNA
129 bool "WBNA"
130 default n
131 help
132 Say Y here to enable write-back memory with no-write-allocation policy.
133
134config ALIGNMENT_TRAP
135 bool "Kernel support unaligned access handling by sw"
136 depends on PROC_FS
137 default n
138 help
139 Andes processors cannot load/store information which is not
140 naturally aligned on the bus, i.e., a 4 byte load must start at an
141 address divisible by 4. On 32-bit Andes processors, these non-aligned
142 load/store instructions will be emulated in software if you say Y
143 here, which has a severe performance impact. With an IP-only
144 configuration it is safe to say N, otherwise say Y.
145
146config HW_SUPPORT_UNALIGNMENT_ACCESS
147 bool "Kernel support unaligned access handling by hw"
148 depends on !ALIGNMENT_TRAP
149 default n
150 help
151 Andes processors load/store world/half-word instructions can access
152 unaligned memory locations without generating the Data Alignment
153 Check exceptions. With an IP-only configuration it is safe to say N,
154 otherwise say Y.
155
156config HIGHMEM
157 bool "High Memory Support"
158 depends on MMU && !CPU_CACHE_ALIASING
159 help
160 The address space of Andes processors is only 4 Gigabytes large
161 and it has to accommodate user address space, kernel address
162 space as well as some memory mapped IO. That means that, if you
163 have a large amount of physical memory and/or IO, not all of the
164 memory can be "permanently mapped" by the kernel. The physical
165 memory that is not permanently mapped is called "high memory".
166
167 Depending on the selected kernel/user memory split, minimum
168 vmalloc space and actual amount of RAM, you may not need this
169 option which should result in a slightly faster kernel.
170
171 If unsure, say N.
172
173config CACHE_L2
174 bool "Support L2 cache"
175 default y
176 help
177 Say Y here to enable L2 cache if your SoC are integrated with L2CC.
178 If unsure, say N.
179
180config HW_PRE
181 bool "Enable hardware prefetcher"
182 default y
183 help
184 Say Y here to enable hardware prefetcher feature.
185 Only when CPU_VER.REV >= 0x09 can support.
186
187menu "Memory configuration"
188
189choice
190 prompt "Memory split"
191 depends on MMU
192 default VMSPLIT_3G_OPT
193 help
194 Select the desired split between kernel and user memory.
195
196 If you are not absolutely sure what you are doing, leave this
197 option alone!
198
199 config VMSPLIT_3G
200 bool "3G/1G user/kernel split"
201 config VMSPLIT_3G_OPT
202 bool "3G/1G user/kernel split (for full 1G low memory)"
203 config VMSPLIT_2G
204 bool "2G/2G user/kernel split"
205 config VMSPLIT_1G
206 bool "1G/3G user/kernel split"
207endchoice
208
209config PAGE_OFFSET
210 hex
211 default 0x40000000 if VMSPLIT_1G
212 default 0x80000000 if VMSPLIT_2G
213 default 0xB0000000 if VMSPLIT_3G_OPT
214 default 0xC0000000
215
216endmenu