tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright (C) 2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ASM_ESR_H
19#define __ASM_ESR_H
20
21#include <asm/memory.h>
22#include <asm/sysreg.h>
23
24#define ESR_ELx_EC_UNKNOWN (0x00)
25#define ESR_ELx_EC_WFx (0x01)
26/* Unallocated EC: 0x02 */
27#define ESR_ELx_EC_CP15_32 (0x03)
28#define ESR_ELx_EC_CP15_64 (0x04)
29#define ESR_ELx_EC_CP14_MR (0x05)
30#define ESR_ELx_EC_CP14_LS (0x06)
31#define ESR_ELx_EC_FP_ASIMD (0x07)
32#define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
33#define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
34/* Unallocated EC: 0x0A - 0x0B */
35#define ESR_ELx_EC_CP14_64 (0x0C)
36/* Unallocated EC: 0x0d */
37#define ESR_ELx_EC_ILL (0x0E)
38/* Unallocated EC: 0x0F - 0x10 */
39#define ESR_ELx_EC_SVC32 (0x11)
40#define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
41#define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
42/* Unallocated EC: 0x14 */
43#define ESR_ELx_EC_SVC64 (0x15)
44#define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
45#define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
46#define ESR_ELx_EC_SYS64 (0x18)
47#define ESR_ELx_EC_SVE (0x19)
48/* Unallocated EC: 0x1A - 0x1E */
49#define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
50#define ESR_ELx_EC_IABT_LOW (0x20)
51#define ESR_ELx_EC_IABT_CUR (0x21)
52#define ESR_ELx_EC_PC_ALIGN (0x22)
53/* Unallocated EC: 0x23 */
54#define ESR_ELx_EC_DABT_LOW (0x24)
55#define ESR_ELx_EC_DABT_CUR (0x25)
56#define ESR_ELx_EC_SP_ALIGN (0x26)
57/* Unallocated EC: 0x27 */
58#define ESR_ELx_EC_FP_EXC32 (0x28)
59/* Unallocated EC: 0x29 - 0x2B */
60#define ESR_ELx_EC_FP_EXC64 (0x2C)
61/* Unallocated EC: 0x2D - 0x2E */
62#define ESR_ELx_EC_SERROR (0x2F)
63#define ESR_ELx_EC_BREAKPT_LOW (0x30)
64#define ESR_ELx_EC_BREAKPT_CUR (0x31)
65#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
66#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
67#define ESR_ELx_EC_WATCHPT_LOW (0x34)
68#define ESR_ELx_EC_WATCHPT_CUR (0x35)
69/* Unallocated EC: 0x36 - 0x37 */
70#define ESR_ELx_EC_BKPT32 (0x38)
71/* Unallocated EC: 0x39 */
72#define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
73/* Unallocted EC: 0x3B */
74#define ESR_ELx_EC_BRK64 (0x3C)
75/* Unallocated EC: 0x3D - 0x3F */
76#define ESR_ELx_EC_MAX (0x3F)
77
78#define ESR_ELx_EC_SHIFT (26)
79#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
80#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
81
82#define ESR_ELx_IL_SHIFT (25)
83#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
84#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
85
86/* ISS field definitions shared by different classes */
87#define ESR_ELx_WNR_SHIFT (6)
88#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
89
90/* Asynchronous Error Type */
91#define ESR_ELx_IDS_SHIFT (24)
92#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
93#define ESR_ELx_AET_SHIFT (10)
94#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
95
96#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
97#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
98#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
99#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
100#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
101
102/* Shared ISS field definitions for Data/Instruction aborts */
103#define ESR_ELx_SET_SHIFT (11)
104#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
105#define ESR_ELx_FnV_SHIFT (10)
106#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
107#define ESR_ELx_EA_SHIFT (9)
108#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
109#define ESR_ELx_S1PTW_SHIFT (7)
110#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
111
112/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
113#define ESR_ELx_FSC (0x3F)
114#define ESR_ELx_FSC_TYPE (0x3C)
115#define ESR_ELx_FSC_EXTABT (0x10)
116#define ESR_ELx_FSC_SERROR (0x11)
117#define ESR_ELx_FSC_ACCESS (0x08)
118#define ESR_ELx_FSC_FAULT (0x04)
119#define ESR_ELx_FSC_PERM (0x0C)
120
121/* ISS field definitions for Data Aborts */
122#define ESR_ELx_ISV_SHIFT (24)
123#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
124#define ESR_ELx_SAS_SHIFT (22)
125#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
126#define ESR_ELx_SSE_SHIFT (21)
127#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
128#define ESR_ELx_SRT_SHIFT (16)
129#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
130#define ESR_ELx_SF_SHIFT (15)
131#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
132#define ESR_ELx_AR_SHIFT (14)
133#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
134#define ESR_ELx_CM_SHIFT (8)
135#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
136
137/* ISS field definitions for exceptions taken in to Hyp */
138#define ESR_ELx_CV (UL(1) << 24)
139#define ESR_ELx_COND_SHIFT (20)
140#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
141#define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
142#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
143#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
144#define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
145
146#define DISR_EL1_IDS (UL(1) << 24)
147/*
148 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
149 * different things in the future...
150 */
151#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
152
153/* ESR value templates for specific events */
154#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
155#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
156 ESR_ELx_WFx_ISS_WFI)
157
158/* BRK instruction trap from AArch64 state */
159#define ESR_ELx_VAL_BRK64(imm) \
160 ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \
161 ((imm) & 0xffff))
162
163/* ISS field definitions for System instruction traps */
164#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
165#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
166#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
167#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
168#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
169
170#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
171#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
172#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
173#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
174#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
175#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
176#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
177#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
178#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
179#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
180#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
181#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
182#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
183 ESR_ELx_SYS64_ISS_OP1_MASK | \
184 ESR_ELx_SYS64_ISS_OP2_MASK | \
185 ESR_ELx_SYS64_ISS_CRN_MASK | \
186 ESR_ELx_SYS64_ISS_CRM_MASK)
187#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
188 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
189 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
190 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
191 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
192 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
193
194#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
195 ESR_ELx_SYS64_ISS_DIR_MASK)
196#define ESR_ELx_SYS64_ISS_RT(esr) \
197 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
198/*
199 * User space cache operations have the following sysreg encoding
200 * in System instructions.
201 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
202 */
203#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
204#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
205#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
206#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
207#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
208
209#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
210 ESR_ELx_SYS64_ISS_OP1_MASK | \
211 ESR_ELx_SYS64_ISS_OP2_MASK | \
212 ESR_ELx_SYS64_ISS_CRN_MASK | \
213 ESR_ELx_SYS64_ISS_DIR_MASK)
214#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
215 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
216 ESR_ELx_SYS64_ISS_DIR_WRITE)
217/*
218 * User space MRS operations which are supported for emulation
219 * have the following sysreg encoding in System instructions.
220 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
221 */
222#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
223 ESR_ELx_SYS64_ISS_OP1_MASK | \
224 ESR_ELx_SYS64_ISS_CRN_MASK | \
225 ESR_ELx_SYS64_ISS_DIR_MASK)
226#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
227 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
228 ESR_ELx_SYS64_ISS_DIR_READ)
229
230#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
231#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
232 ESR_ELx_SYS64_ISS_DIR_READ)
233
234#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
235 ESR_ELx_SYS64_ISS_DIR_READ)
236
237#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
238 ESR_ELx_SYS64_ISS_DIR_READ)
239
240#define esr_sys64_to_sysreg(e) \
241 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
242 ESR_ELx_SYS64_ISS_OP0_SHIFT), \
243 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
244 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
245 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
246 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
247 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
248 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
249 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
250 ESR_ELx_SYS64_ISS_OP2_SHIFT))
251
252#define esr_cp15_to_sysreg(e) \
253 sys_reg(3, \
254 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
255 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
256 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
257 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
258 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
259 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
260 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
261 ESR_ELx_SYS64_ISS_OP2_SHIFT))
262
263/*
264 * ISS field definitions for floating-point exception traps
265 * (FP_EXC_32/FP_EXC_64).
266 *
267 * (The FPEXC_* constants are used instead for common bits.)
268 */
269
270#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
271
272/*
273 * ISS field definitions for CP15 accesses
274 */
275#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
276#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
277#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
278
279#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
280#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
281#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
282#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
283#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
284#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
285#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
286#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
287#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
288#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
289
290#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
291 ESR_ELx_CP15_32_ISS_OP2_MASK | \
292 ESR_ELx_CP15_32_ISS_CRN_MASK | \
293 ESR_ELx_CP15_32_ISS_CRM_MASK | \
294 ESR_ELx_CP15_32_ISS_DIR_MASK)
295#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
296 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
297 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
298 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
299 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
300
301#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
302#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
303#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
304
305#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
306#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
307
308#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
309#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
310
311#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
312#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
313#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
314#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
315
316#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
317 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
318 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
319
320#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
321 ESR_ELx_CP15_64_ISS_CRM_MASK | \
322 ESR_ELx_CP15_64_ISS_DIR_MASK)
323
324#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
325 ESR_ELx_CP15_64_ISS_DIR_READ)
326
327#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
328 ESR_ELx_CP15_32_ISS_DIR_READ)
329
330#ifndef __ASSEMBLY__
331#include <asm/types.h>
332
333static inline bool esr_is_data_abort(u32 esr)
334{
335 const u32 ec = ESR_ELx_EC(esr);
336
337 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
338}
339
340const char *esr_get_class_string(u32 esr);
341#endif /* __ASSEMBLY */
342
343#endif /* __ASM_ESR_H */