tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / include / dt-bindings / clock / qcom,gcc-ipq8074.h
at v5.1-rc7 374 lines 13 kB view raw
1/* 2 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 15#define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 16 17#define GPLL0 0 18#define GPLL0_MAIN 1 19#define GCC_SLEEP_CLK_SRC 2 20#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 21#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 22#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 23#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 24#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 25#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 26#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 27#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 28#define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 29#define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 30#define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 31#define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 32#define BLSP1_UART1_APPS_CLK_SRC 15 33#define BLSP1_UART2_APPS_CLK_SRC 16 34#define BLSP1_UART3_APPS_CLK_SRC 17 35#define BLSP1_UART4_APPS_CLK_SRC 18 36#define BLSP1_UART5_APPS_CLK_SRC 19 37#define BLSP1_UART6_APPS_CLK_SRC 20 38#define GCC_BLSP1_AHB_CLK 21 39#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 40#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 41#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 42#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 43#define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 44#define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 45#define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 46#define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 47#define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 48#define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 49#define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 50#define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 51#define GCC_BLSP1_UART1_APPS_CLK 34 52#define GCC_BLSP1_UART2_APPS_CLK 35 53#define GCC_BLSP1_UART3_APPS_CLK 36 54#define GCC_BLSP1_UART4_APPS_CLK 37 55#define GCC_BLSP1_UART5_APPS_CLK 38 56#define GCC_BLSP1_UART6_APPS_CLK 39 57#define GCC_PRNG_AHB_CLK 40 58#define GCC_QPIC_AHB_CLK 41 59#define GCC_QPIC_CLK 42 60#define PCNOC_BFDCD_CLK_SRC 43 61#define GPLL2_MAIN 44 62#define GPLL2 45 63#define GPLL4_MAIN 46 64#define GPLL4 47 65#define GPLL6_MAIN 48 66#define GPLL6 49 67#define UBI32_PLL_MAIN 50 68#define UBI32_PLL 51 69#define NSS_CRYPTO_PLL_MAIN 52 70#define NSS_CRYPTO_PLL 53 71#define PCIE0_AXI_CLK_SRC 54 72#define PCIE0_AUX_CLK_SRC 55 73#define PCIE0_PIPE_CLK_SRC 56 74#define PCIE1_AXI_CLK_SRC 57 75#define PCIE1_AUX_CLK_SRC 58 76#define PCIE1_PIPE_CLK_SRC 59 77#define SDCC1_APPS_CLK_SRC 60 78#define SDCC1_ICE_CORE_CLK_SRC 61 79#define SDCC2_APPS_CLK_SRC 62 80#define USB0_MASTER_CLK_SRC 63 81#define USB0_AUX_CLK_SRC 64 82#define USB0_MOCK_UTMI_CLK_SRC 65 83#define USB0_PIPE_CLK_SRC 66 84#define USB1_MASTER_CLK_SRC 67 85#define USB1_AUX_CLK_SRC 68 86#define USB1_MOCK_UTMI_CLK_SRC 69 87#define USB1_PIPE_CLK_SRC 70 88#define GCC_XO_CLK_SRC 71 89#define SYSTEM_NOC_BFDCD_CLK_SRC 72 90#define NSS_CE_CLK_SRC 73 91#define NSS_NOC_BFDCD_CLK_SRC 74 92#define NSS_CRYPTO_CLK_SRC 75 93#define NSS_UBI0_CLK_SRC 76 94#define NSS_UBI0_DIV_CLK_SRC 77 95#define NSS_UBI1_CLK_SRC 78 96#define NSS_UBI1_DIV_CLK_SRC 79 97#define UBI_MPT_CLK_SRC 80 98#define NSS_IMEM_CLK_SRC 81 99#define NSS_PPE_CLK_SRC 82 100#define NSS_PORT1_RX_CLK_SRC 83 101#define NSS_PORT1_RX_DIV_CLK_SRC 84 102#define NSS_PORT1_TX_CLK_SRC 85 103#define NSS_PORT1_TX_DIV_CLK_SRC 86 104#define NSS_PORT2_RX_CLK_SRC 87 105#define NSS_PORT2_RX_DIV_CLK_SRC 88 106#define NSS_PORT2_TX_CLK_SRC 89 107#define NSS_PORT2_TX_DIV_CLK_SRC 90 108#define NSS_PORT3_RX_CLK_SRC 91 109#define NSS_PORT3_RX_DIV_CLK_SRC 92 110#define NSS_PORT3_TX_CLK_SRC 93 111#define NSS_PORT3_TX_DIV_CLK_SRC 94 112#define NSS_PORT4_RX_CLK_SRC 95 113#define NSS_PORT4_RX_DIV_CLK_SRC 96 114#define NSS_PORT4_TX_CLK_SRC 97 115#define NSS_PORT4_TX_DIV_CLK_SRC 98 116#define NSS_PORT5_RX_CLK_SRC 99 117#define NSS_PORT5_RX_DIV_CLK_SRC 100 118#define NSS_PORT5_TX_CLK_SRC 101 119#define NSS_PORT5_TX_DIV_CLK_SRC 102 120#define NSS_PORT6_RX_CLK_SRC 103 121#define NSS_PORT6_RX_DIV_CLK_SRC 104 122#define NSS_PORT6_TX_CLK_SRC 105 123#define NSS_PORT6_TX_DIV_CLK_SRC 106 124#define CRYPTO_CLK_SRC 107 125#define GP1_CLK_SRC 108 126#define GP2_CLK_SRC 109 127#define GP3_CLK_SRC 110 128#define GCC_PCIE0_AHB_CLK 111 129#define GCC_PCIE0_AUX_CLK 112 130#define GCC_PCIE0_AXI_M_CLK 113 131#define GCC_PCIE0_AXI_S_CLK 114 132#define GCC_PCIE0_PIPE_CLK 115 133#define GCC_SYS_NOC_PCIE0_AXI_CLK 116 134#define GCC_PCIE1_AHB_CLK 117 135#define GCC_PCIE1_AUX_CLK 118 136#define GCC_PCIE1_AXI_M_CLK 119 137#define GCC_PCIE1_AXI_S_CLK 120 138#define GCC_PCIE1_PIPE_CLK 121 139#define GCC_SYS_NOC_PCIE1_AXI_CLK 122 140#define GCC_USB0_AUX_CLK 123 141#define GCC_SYS_NOC_USB0_AXI_CLK 124 142#define GCC_USB0_MASTER_CLK 125 143#define GCC_USB0_MOCK_UTMI_CLK 126 144#define GCC_USB0_PHY_CFG_AHB_CLK 127 145#define GCC_USB0_PIPE_CLK 128 146#define GCC_USB0_SLEEP_CLK 129 147#define GCC_USB1_AUX_CLK 130 148#define GCC_SYS_NOC_USB1_AXI_CLK 131 149#define GCC_USB1_MASTER_CLK 132 150#define GCC_USB1_MOCK_UTMI_CLK 133 151#define GCC_USB1_PHY_CFG_AHB_CLK 134 152#define GCC_USB1_PIPE_CLK 135 153#define GCC_USB1_SLEEP_CLK 136 154#define GCC_SDCC1_AHB_CLK 137 155#define GCC_SDCC1_APPS_CLK 138 156#define GCC_SDCC1_ICE_CORE_CLK 139 157#define GCC_SDCC2_AHB_CLK 140 158#define GCC_SDCC2_APPS_CLK 141 159#define GCC_MEM_NOC_NSS_AXI_CLK 142 160#define GCC_NSS_CE_APB_CLK 143 161#define GCC_NSS_CE_AXI_CLK 144 162#define GCC_NSS_CFG_CLK 145 163#define GCC_NSS_CRYPTO_CLK 146 164#define GCC_NSS_CSR_CLK 147 165#define GCC_NSS_EDMA_CFG_CLK 148 166#define GCC_NSS_EDMA_CLK 149 167#define GCC_NSS_IMEM_CLK 150 168#define GCC_NSS_NOC_CLK 151 169#define GCC_NSS_PPE_BTQ_CLK 152 170#define GCC_NSS_PPE_CFG_CLK 153 171#define GCC_NSS_PPE_CLK 154 172#define GCC_NSS_PPE_IPE_CLK 155 173#define GCC_NSS_PTP_REF_CLK 156 174#define GCC_NSSNOC_CE_APB_CLK 157 175#define GCC_NSSNOC_CE_AXI_CLK 158 176#define GCC_NSSNOC_CRYPTO_CLK 159 177#define GCC_NSSNOC_PPE_CFG_CLK 160 178#define GCC_NSSNOC_PPE_CLK 161 179#define GCC_NSSNOC_QOSGEN_REF_CLK 162 180#define GCC_NSSNOC_SNOC_CLK 163 181#define GCC_NSSNOC_TIMEOUT_REF_CLK 164 182#define GCC_NSSNOC_UBI0_AHB_CLK 165 183#define GCC_NSSNOC_UBI1_AHB_CLK 166 184#define GCC_UBI0_AHB_CLK 167 185#define GCC_UBI0_AXI_CLK 168 186#define GCC_UBI0_NC_AXI_CLK 169 187#define GCC_UBI0_CORE_CLK 170 188#define GCC_UBI0_MPT_CLK 171 189#define GCC_UBI1_AHB_CLK 172 190#define GCC_UBI1_AXI_CLK 173 191#define GCC_UBI1_NC_AXI_CLK 174 192#define GCC_UBI1_CORE_CLK 175 193#define GCC_UBI1_MPT_CLK 176 194#define GCC_CMN_12GPLL_AHB_CLK 177 195#define GCC_CMN_12GPLL_SYS_CLK 178 196#define GCC_MDIO_AHB_CLK 179 197#define GCC_UNIPHY0_AHB_CLK 180 198#define GCC_UNIPHY0_SYS_CLK 181 199#define GCC_UNIPHY1_AHB_CLK 182 200#define GCC_UNIPHY1_SYS_CLK 183 201#define GCC_UNIPHY2_AHB_CLK 184 202#define GCC_UNIPHY2_SYS_CLK 185 203#define GCC_NSS_PORT1_RX_CLK 186 204#define GCC_NSS_PORT1_TX_CLK 187 205#define GCC_NSS_PORT2_RX_CLK 188 206#define GCC_NSS_PORT2_TX_CLK 189 207#define GCC_NSS_PORT3_RX_CLK 190 208#define GCC_NSS_PORT3_TX_CLK 191 209#define GCC_NSS_PORT4_RX_CLK 192 210#define GCC_NSS_PORT4_TX_CLK 193 211#define GCC_NSS_PORT5_RX_CLK 194 212#define GCC_NSS_PORT5_TX_CLK 195 213#define GCC_NSS_PORT6_RX_CLK 196 214#define GCC_NSS_PORT6_TX_CLK 197 215#define GCC_PORT1_MAC_CLK 198 216#define GCC_PORT2_MAC_CLK 199 217#define GCC_PORT3_MAC_CLK 200 218#define GCC_PORT4_MAC_CLK 201 219#define GCC_PORT5_MAC_CLK 202 220#define GCC_PORT6_MAC_CLK 203 221#define GCC_UNIPHY0_PORT1_RX_CLK 204 222#define GCC_UNIPHY0_PORT1_TX_CLK 205 223#define GCC_UNIPHY0_PORT2_RX_CLK 206 224#define GCC_UNIPHY0_PORT2_TX_CLK 207 225#define GCC_UNIPHY0_PORT3_RX_CLK 208 226#define GCC_UNIPHY0_PORT3_TX_CLK 209 227#define GCC_UNIPHY0_PORT4_RX_CLK 210 228#define GCC_UNIPHY0_PORT4_TX_CLK 211 229#define GCC_UNIPHY0_PORT5_RX_CLK 212 230#define GCC_UNIPHY0_PORT5_TX_CLK 213 231#define GCC_UNIPHY1_PORT5_RX_CLK 214 232#define GCC_UNIPHY1_PORT5_TX_CLK 215 233#define GCC_UNIPHY2_PORT6_RX_CLK 216 234#define GCC_UNIPHY2_PORT6_TX_CLK 217 235#define GCC_CRYPTO_AHB_CLK 218 236#define GCC_CRYPTO_AXI_CLK 219 237#define GCC_CRYPTO_CLK 220 238#define GCC_GP1_CLK 221 239#define GCC_GP2_CLK 222 240#define GCC_GP3_CLK 223 241 242#define GCC_BLSP1_BCR 0 243#define GCC_BLSP1_QUP1_BCR 1 244#define GCC_BLSP1_UART1_BCR 2 245#define GCC_BLSP1_QUP2_BCR 3 246#define GCC_BLSP1_UART2_BCR 4 247#define GCC_BLSP1_QUP3_BCR 5 248#define GCC_BLSP1_UART3_BCR 6 249#define GCC_BLSP1_QUP4_BCR 7 250#define GCC_BLSP1_UART4_BCR 8 251#define GCC_BLSP1_QUP5_BCR 9 252#define GCC_BLSP1_UART5_BCR 10 253#define GCC_BLSP1_QUP6_BCR 11 254#define GCC_BLSP1_UART6_BCR 12 255#define GCC_IMEM_BCR 13 256#define GCC_SMMU_BCR 14 257#define GCC_APSS_TCU_BCR 15 258#define GCC_SMMU_XPU_BCR 16 259#define GCC_PCNOC_TBU_BCR 17 260#define GCC_SMMU_CFG_BCR 18 261#define GCC_PRNG_BCR 19 262#define GCC_BOOT_ROM_BCR 20 263#define GCC_CRYPTO_BCR 21 264#define GCC_WCSS_BCR 22 265#define GCC_WCSS_Q6_BCR 23 266#define GCC_NSS_BCR 24 267#define GCC_SEC_CTRL_BCR 25 268#define GCC_ADSS_BCR 26 269#define GCC_DDRSS_BCR 27 270#define GCC_SYSTEM_NOC_BCR 28 271#define GCC_PCNOC_BCR 29 272#define GCC_TCSR_BCR 30 273#define GCC_QDSS_BCR 31 274#define GCC_DCD_BCR 32 275#define GCC_MSG_RAM_BCR 33 276#define GCC_MPM_BCR 34 277#define GCC_SPMI_BCR 35 278#define GCC_SPDM_BCR 36 279#define GCC_RBCPR_BCR 37 280#define GCC_RBCPR_MX_BCR 38 281#define GCC_TLMM_BCR 39 282#define GCC_RBCPR_WCSS_BCR 40 283#define GCC_USB0_PHY_BCR 41 284#define GCC_USB3PHY_0_PHY_BCR 42 285#define GCC_USB0_BCR 43 286#define GCC_USB1_PHY_BCR 44 287#define GCC_USB3PHY_1_PHY_BCR 45 288#define GCC_USB1_BCR 46 289#define GCC_QUSB2_0_PHY_BCR 47 290#define GCC_QUSB2_1_PHY_BCR 48 291#define GCC_SDCC1_BCR 49 292#define GCC_SDCC2_BCR 50 293#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 294#define GCC_SNOC_BUS_TIMEOUT2_BCR 52 295#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 296#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 297#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 298#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 299#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 300#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 301#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 302#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 303#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 304#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 305#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 306#define GCC_UNIPHY0_BCR 64 307#define GCC_UNIPHY1_BCR 65 308#define GCC_UNIPHY2_BCR 66 309#define GCC_CMN_12GPLL_BCR 67 310#define GCC_QPIC_BCR 68 311#define GCC_MDIO_BCR 69 312#define GCC_PCIE1_TBU_BCR 70 313#define GCC_WCSS_CORE_TBU_BCR 71 314#define GCC_WCSS_Q6_TBU_BCR 72 315#define GCC_USB0_TBU_BCR 73 316#define GCC_USB1_TBU_BCR 74 317#define GCC_PCIE0_TBU_BCR 75 318#define GCC_NSS_NOC_TBU_BCR 76 319#define GCC_PCIE0_BCR 77 320#define GCC_PCIE0_PHY_BCR 78 321#define GCC_PCIE0PHY_PHY_BCR 79 322#define GCC_PCIE0_LINK_DOWN_BCR 80 323#define GCC_PCIE1_BCR 81 324#define GCC_PCIE1_PHY_BCR 82 325#define GCC_PCIE1PHY_PHY_BCR 83 326#define GCC_PCIE1_LINK_DOWN_BCR 84 327#define GCC_DCC_BCR 85 328#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 329#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 330#define GCC_SMMU_CATS_BCR 88 331#define GCC_UBI0_AXI_ARES 89 332#define GCC_UBI0_AHB_ARES 90 333#define GCC_UBI0_NC_AXI_ARES 91 334#define GCC_UBI0_DBG_ARES 92 335#define GCC_UBI0_CORE_CLAMP_ENABLE 93 336#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 337#define GCC_UBI1_AXI_ARES 95 338#define GCC_UBI1_AHB_ARES 96 339#define GCC_UBI1_NC_AXI_ARES 97 340#define GCC_UBI1_DBG_ARES 98 341#define GCC_UBI1_CORE_CLAMP_ENABLE 99 342#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 343#define GCC_NSS_CFG_ARES 101 344#define GCC_NSS_IMEM_ARES 102 345#define GCC_NSS_NOC_ARES 103 346#define GCC_NSS_CRYPTO_ARES 104 347#define GCC_NSS_CSR_ARES 105 348#define GCC_NSS_CE_APB_ARES 106 349#define GCC_NSS_CE_AXI_ARES 107 350#define GCC_NSSNOC_CE_APB_ARES 108 351#define GCC_NSSNOC_CE_AXI_ARES 109 352#define GCC_NSSNOC_UBI0_AHB_ARES 110 353#define GCC_NSSNOC_UBI1_AHB_ARES 111 354#define GCC_NSSNOC_SNOC_ARES 112 355#define GCC_NSSNOC_CRYPTO_ARES 113 356#define GCC_NSSNOC_ATB_ARES 114 357#define GCC_NSSNOC_QOSGEN_REF_ARES 115 358#define GCC_NSSNOC_TIMEOUT_REF_ARES 116 359#define GCC_PCIE0_PIPE_ARES 117 360#define GCC_PCIE0_SLEEP_ARES 118 361#define GCC_PCIE0_CORE_STICKY_ARES 119 362#define GCC_PCIE0_AXI_MASTER_ARES 120 363#define GCC_PCIE0_AXI_SLAVE_ARES 121 364#define GCC_PCIE0_AHB_ARES 122 365#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 366#define GCC_PCIE1_PIPE_ARES 124 367#define GCC_PCIE1_SLEEP_ARES 125 368#define GCC_PCIE1_CORE_STICKY_ARES 126 369#define GCC_PCIE1_AXI_MASTER_ARES 127 370#define GCC_PCIE1_AXI_SLAVE_ARES 128 371#define GCC_PCIE1_AHB_ARES 129 372#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 373 374#endif